Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017 Andes Technology Corporation |
| 4 | * Rick Chen, Andes Technology Corporation <rick@andestech.com> |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __CONFIG_H |
| 8 | #define __CONFIG_H |
| 9 | |
Pragnesh Patel | 02038c3 | 2021-01-17 18:11:25 +0530 | [diff] [blame] | 10 | #define RISCV_MMODE_TIMERBASE 0xe6000000 |
| 11 | #define RISCV_MMODE_TIMER_FREQ 60000000 |
| 12 | |
| 13 | #define RISCV_SMODE_TIMER_FREQ 60000000 |
| 14 | |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 15 | /* |
| 16 | * CPU and Board Configuration Options |
| 17 | */ |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 18 | |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 19 | /* |
| 20 | * Miscellaneous configurable options |
| 21 | */ |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 22 | |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 23 | /* |
| 24 | * Physical Memory Map |
| 25 | */ |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 26 | #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ |
| 27 | #define PHYS_SDRAM_1 \ |
| 28 | (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ |
| 29 | #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ |
| 30 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 31 | #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_0 |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 32 | |
| 33 | /* |
| 34 | * Serial console configuration |
| 35 | */ |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 36 | #define CFG_SYS_NS16550_CLK 19660800 |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 37 | |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 38 | /* Init Stack Pointer */ |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 39 | |
Rick Chen | c616414 | 2018-05-29 11:04:23 +0800 | [diff] [blame] | 40 | /* support JEDEC */ |
Rick Chen | c616414 | 2018-05-29 11:04:23 +0800 | [diff] [blame] | 41 | #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 42 | #define CFG_SYS_FLASH_BASE PHYS_FLASH_1 |
| 43 | #define CFG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } |
Rick Chen | c616414 | 2018-05-29 11:04:23 +0800 | [diff] [blame] | 44 | |
Rick Chen | c616414 | 2018-05-29 11:04:23 +0800 | [diff] [blame] | 45 | /* max number of memory banks */ |
| 46 | /* |
| 47 | * There are 4 banks supported for this Controller, |
| 48 | * but we have only 1 bank connected to flash on board |
| 49 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 50 | #define CFG_SYS_FLASH_BANKS_SIZES {0x4000000} |
Rick Chen | c616414 | 2018-05-29 11:04:23 +0800 | [diff] [blame] | 51 | |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 52 | /* environments */ |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 53 | |
| 54 | /* SPI FLASH */ |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 55 | |
| 56 | /* |
| 57 | * For booting Linux, the board info and command line data |
| 58 | * have to be in the first 16 MB of memory, since this is |
| 59 | * the maximum mapped by the Linux kernel during initialization. |
| 60 | */ |
| 61 | |
| 62 | /* Initial Memory map for Linux*/ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 63 | #define CFG_SYS_BOOTMAPSZ (64 << 20) |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 64 | /* Increase max gunzip size */ |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 65 | |
Leo Yu-Chi Liang | 919a0e7 | 2021-11-04 09:53:26 +0800 | [diff] [blame] | 66 | /* Support autoboot from RAM (kernel image is loaded via debug port) */ |
| 67 | #define KERNEL_IMAGE_ADDR "0x2000000 " |
| 68 | #define BOOTENV_DEV_NAME_RAM(devtypeu, devtypel, instance) \ |
| 69 | "ram " |
| 70 | #define BOOTENV_DEV_RAM(devtypeu, devtypel, instance) \ |
| 71 | "bootcmd_ram=" \ |
| 72 | "booti " \ |
| 73 | KERNEL_IMAGE_ADDR \ |
| 74 | "- $fdtcontroladdr\0" |
| 75 | |
Alexander Graf | 438b9be | 2018-04-23 07:59:49 +0200 | [diff] [blame] | 76 | /* When we use RAM as ENV */ |
Alexander Graf | 438b9be | 2018-04-23 07:59:49 +0200 | [diff] [blame] | 77 | |
| 78 | /* Enable distro boot */ |
| 79 | #define BOOT_TARGET_DEVICES(func) \ |
| 80 | func(MMC, mmc, 0) \ |
Leo Yu-Chi Liang | 919a0e7 | 2021-11-04 09:53:26 +0800 | [diff] [blame] | 81 | func(DHCP, dhcp, na) \ |
| 82 | func(RAM, ram, na) |
Alexander Graf | 438b9be | 2018-04-23 07:59:49 +0200 | [diff] [blame] | 83 | #include <config_distro_bootcmd.h> |
| 84 | |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 85 | #define CFG_EXTRA_ENV_SETTINGS \ |
Yu Chien Peter Lin | aa51465 | 2023-07-04 19:13:21 +0800 | [diff] [blame] | 86 | "fdt_high=0xffffffffffffffff\0" \ |
| 87 | "initrd_high=0xffffffffffffffff\0" \ |
| 88 | "kernel_addr_r=0x00600000\0" \ |
| 89 | "kernel_comp_addr_r=0x04600000\0" \ |
| 90 | "kernel_comp_size=0x04000000\0" \ |
| 91 | "pxefile_addr_r=0x08600000\0" \ |
| 92 | "scriptaddr=0x08700000\0" \ |
| 93 | "fdt_addr_r=0x08800000\0" \ |
| 94 | "ramdisk_addr_r=0x08900000\0" \ |
Alexander Graf | 438b9be | 2018-04-23 07:59:49 +0200 | [diff] [blame] | 95 | BOOTENV |
| 96 | |
Rick Chen | b46a18b | 2017-12-26 13:55:54 +0800 | [diff] [blame] | 97 | #endif /* __CONFIG_H */ |