blob: 03e04e6e68051ded8caf714d4ed83956143e16ce [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Rick Chenb46a18b2017-12-26 13:55:54 +08002/*
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
Rick Chenb46a18b2017-12-26 13:55:54 +08005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Pragnesh Patel02038c32021-01-17 18:11:25 +053010#define RISCV_MMODE_TIMERBASE 0xe6000000
11#define RISCV_MMODE_TIMER_FREQ 60000000
12
13#define RISCV_SMODE_TIMER_FREQ 60000000
14
Rick Chenb46a18b2017-12-26 13:55:54 +080015/*
16 * CPU and Board Configuration Options
17 */
Rick Chenb46a18b2017-12-26 13:55:54 +080018
Rick Chenb46a18b2017-12-26 13:55:54 +080019/*
20 * Miscellaneous configurable options
21 */
Rick Chenb46a18b2017-12-26 13:55:54 +080022
Rick Chenb46a18b2017-12-26 13:55:54 +080023/*
24 * Physical Memory Map
25 */
Rick Chenb46a18b2017-12-26 13:55:54 +080026#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
27#define PHYS_SDRAM_1 \
28 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
29#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
30#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
Tom Rinibb4dd962022-11-16 13:10:37 -050031#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_0
Rick Chenb46a18b2017-12-26 13:55:54 +080032
33/*
34 * Serial console configuration
35 */
Tom Rinidf6a2152022-11-16 13:10:28 -050036#define CFG_SYS_NS16550_CLK 19660800
Rick Chenb46a18b2017-12-26 13:55:54 +080037
Rick Chenb46a18b2017-12-26 13:55:54 +080038/* Init Stack Pointer */
Rick Chenb46a18b2017-12-26 13:55:54 +080039
Rick Chenc6164142018-05-29 11:04:23 +080040/* support JEDEC */
Rick Chenc6164142018-05-29 11:04:23 +080041#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050042#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
43#define CFG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
Rick Chenc6164142018-05-29 11:04:23 +080044
Rick Chenc6164142018-05-29 11:04:23 +080045/* max number of memory banks */
46/*
47 * There are 4 banks supported for this Controller,
48 * but we have only 1 bank connected to flash on board
49*/
Tom Rini6a5dccc2022-11-16 13:10:41 -050050#define CFG_SYS_FLASH_BANKS_SIZES {0x4000000}
Rick Chenc6164142018-05-29 11:04:23 +080051
52/* max number of sectors on one chip */
53#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
Rick Chenc6164142018-05-29 11:04:23 +080054
Rick Chenb46a18b2017-12-26 13:55:54 +080055/* environments */
Rick Chenb46a18b2017-12-26 13:55:54 +080056
57/* SPI FLASH */
Rick Chenb46a18b2017-12-26 13:55:54 +080058
59/*
60 * For booting Linux, the board info and command line data
61 * have to be in the first 16 MB of memory, since this is
62 * the maximum mapped by the Linux kernel during initialization.
63 */
64
65/* Initial Memory map for Linux*/
Tom Rini6a5dccc2022-11-16 13:10:41 -050066#define CFG_SYS_BOOTMAPSZ (64 << 20)
Rick Chenb46a18b2017-12-26 13:55:54 +080067/* Increase max gunzip size */
Rick Chenb46a18b2017-12-26 13:55:54 +080068
Leo Yu-Chi Liang919a0e72021-11-04 09:53:26 +080069/* Support autoboot from RAM (kernel image is loaded via debug port) */
70#define KERNEL_IMAGE_ADDR "0x2000000 "
71#define BOOTENV_DEV_NAME_RAM(devtypeu, devtypel, instance) \
72 "ram "
73#define BOOTENV_DEV_RAM(devtypeu, devtypel, instance) \
74 "bootcmd_ram=" \
75 "booti " \
76 KERNEL_IMAGE_ADDR \
77 "- $fdtcontroladdr\0"
78
Alexander Graf438b9be2018-04-23 07:59:49 +020079/* When we use RAM as ENV */
Alexander Graf438b9be2018-04-23 07:59:49 +020080
81/* Enable distro boot */
82#define BOOT_TARGET_DEVICES(func) \
83 func(MMC, mmc, 0) \
Leo Yu-Chi Liang919a0e72021-11-04 09:53:26 +080084 func(DHCP, dhcp, na) \
85 func(RAM, ram, na)
Alexander Graf438b9be2018-04-23 07:59:49 +020086#include <config_distro_bootcmd.h>
87
88#define CONFIG_EXTRA_ENV_SETTINGS \
89 "kernel_addr_r=0x00080000\0" \
90 "pxefile_addr_r=0x01f00000\0" \
91 "scriptaddr=0x01f00000\0" \
92 "fdt_addr_r=0x02000000\0" \
93 "ramdisk_addr_r=0x02800000\0" \
94 BOOTENV
95
Rick Chenb46a18b2017-12-26 13:55:54 +080096#endif /* __CONFIG_H */