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git01.mediatek.com / filogic / uboot / 3263e748a19043c290316fe7d2aefa15c2866dcb / . / test / dm / reset.c
blob: f5f366151fcd2ad7d7eb13ba84c66ecacabe8c79 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]2/*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]4 */
5
6#include <common.h>
7#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]8#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -0700[diff] [blame]9#include <malloc.h>
Jagan Tekidcd48c32019-02-28 00:26:56 +0530[diff] [blame]10#include <reset.h>
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]11#include <dm/test.h>
12#include <asm/reset.h>
Simon Glass75c4d412020-07-19 10:15:37 -0600[diff] [blame]13#include <test/test.h>
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]14#include <test/ut.h>
15
16/* This must match the specifier for mbox-names="test" in the DT node */
17#define TEST_RESET_ID 2
18
Neil Armstrong20c633d2018-04-03 11:40:51 +0200[diff] [blame]19/* This is the other reset phandle specifier handled by bulk */
20#define OTHER_RESET_ID 2
21
Jagan Tekidcd48c32019-02-28 00:26:56 +0530[diff] [blame]22/* Base test of the reset uclass */
23static int dm_test_reset_base(struct unit_test_state *uts)
24{
25 struct udevice *dev;
26 struct reset_ctl reset_method1;
27 struct reset_ctl reset_method2;
28
29 /* Get the device using the reset device */
30 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test",
31 &dev));
32
33 /* Get the same reset port in 2 different ways and compare */
34 ut_assertok(reset_get_by_index(dev, 1, &reset_method1));
35 ut_assertok(reset_get_by_index_nodev(dev_ofnode(dev), 1,
36 &reset_method2));
37 ut_asserteq(reset_method1.id, reset_method2.id);
38
39 return 0;
40}
41
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]42DM_TEST(dm_test_reset_base, UT_TESTF_SCAN_FDT);
Jagan Tekidcd48c32019-02-28 00:26:56 +0530[diff] [blame]43
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]44static int dm_test_reset(struct unit_test_state *uts)
45{
46 struct udevice *dev_reset;
47 struct udevice *dev_test;
48
49 ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "reset-ctl",
50 &dev_reset));
51 ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
52
53 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test",
54 &dev_test));
55 ut_assertok(sandbox_reset_test_get(dev_test));
56
57 ut_assertok(sandbox_reset_test_assert(dev_test));
58 ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID));
59
60 ut_assertok(sandbox_reset_test_deassert(dev_test));
61 ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
62
63 ut_assertok(sandbox_reset_test_free(dev_test));
64
65 return 0;
66}
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]67DM_TEST(dm_test_reset, UT_TESTF_SCAN_FDT);
Neil Armstrong20c633d2018-04-03 11:40:51 +0200[diff] [blame]68
69static int dm_test_reset_bulk(struct unit_test_state *uts)
70{
71 struct udevice *dev_reset;
72 struct udevice *dev_test;
73
74 ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "reset-ctl",
75 &dev_reset));
76 ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
77 ut_asserteq(0, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
78
79 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test",
80 &dev_test));
81 ut_assertok(sandbox_reset_test_get_bulk(dev_test));
82
83 ut_assertok(sandbox_reset_test_assert_bulk(dev_test));
84 ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID));
85 ut_asserteq(1, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
86
87 ut_assertok(sandbox_reset_test_deassert_bulk(dev_test));
88 ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
89 ut_asserteq(0, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
90
91 ut_assertok(sandbox_reset_test_release_bulk(dev_test));
92 ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID));
93 ut_asserteq(1, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
94
95 return 0;
96}
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]97DM_TEST(dm_test_reset_bulk, UT_TESTF_SCAN_FDT);