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git01.mediatek.com / filogic / uboot / 3263e748a19043c290316fe7d2aefa15c2866dcb / . / arch / x86 / cpu / quark / Kconfig
blob: 2fee38aed79c23895d47de83779a1cebc3afbcb0 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1# SPDX-License-Identifier: GPL-2.0+
Bin Meng81da5a82015-02-02 22:35:27 +0800[diff] [blame]2#
3# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
Bin Meng81da5a82015-02-02 22:35:27 +0800[diff] [blame]4
5config INTEL_QUARK
6 bool
7 select HAVE_RMU
Bin Meng6f40e7c2017-07-30 06:23:13 -0700[diff] [blame]8 select ARCH_EARLY_INIT_R
Bin Mengb0d42d72017-07-30 06:23:12 -0700[diff] [blame]9 select ARCH_MISC_INIT
Bin Meng1949a9a2017-07-30 06:23:14 -0700[diff] [blame]10 imply ENABLE_MRC_CACHE
Bin Mengac432012017-07-30 06:23:23 -0700[diff] [blame]11 imply ETH_DESIGNWARE
12 imply ICH_SPI
Bin Mengce9d1b02017-07-30 06:23:28 -0700[diff] [blame]13 imply INTEL_ICH6_GPIO
Bin Mengac432012017-07-30 06:23:23 -0700[diff] [blame]14 imply MMC
15 imply MMC_PCI
16 imply MMC_SDHCI
17 imply MMC_SDHCI_SDMA
18 imply SPI_FLASH
19 imply SYS_NS16550
Bin Meng5b5d1732017-07-30 06:23:27 -0700[diff] [blame]20 imply USB
21 imply USB_EHCI_HCD
Bin Meng81da5a82015-02-02 22:35:27 +0800[diff] [blame]22
23if INTEL_QUARK
24
25config HAVE_RMU
26 bool "Add a Remote Management Unit (RMU) binary"
Simon Glassf69c0092020-07-19 13:55:52 -0600[diff] [blame]27 select ROM_NEEDS_BLOBS
Bin Meng81da5a82015-02-02 22:35:27 +0800[diff] [blame]28 help
29 Select this option to add a Remote Management Unit (RMU) binary
30 to the resulting U-Boot image. It is a data block (up to 64K) of
31 machine-specific code which must be put in the flash for the RMU
32 within the Quark SoC processor to access when powered up before
33 system BIOS is executed.
34
35config RMU_FILE
36 string "Remote Management Unit (RMU) binary filename"
37 depends on HAVE_RMU
38 default "rmu.bin"
39 help
40 The filename of the file to use as Remote Management Unit (RMU)
41 binary in the board directory.
42
43config RMU_ADDR
44 hex "Remote Management Unit (RMU) binary location"
45 depends on HAVE_RMU
46 default 0xfff00000
47 help
48 The location of the RMU binary is determined by a strap. It must be
49 put in flash at a location matching the strap-determined base address.
50
51 The default base address of 0xfff00000 indicates that the binary must
52 be located at offset 0 from the beginning of a 1MB flash device.
53
54config HAVE_CMC
55 bool
56 default HAVE_RMU
57
58config CMC_FILE
59 string
60 depends on HAVE_CMC
61 default RMU_FILE
62
63config CMC_ADDR
64 hex
65 depends on HAVE_CMC
66 default RMU_ADDR
67
68config ESRAM_BASE
69 hex
70 default 0x80000000
71 help
72 Embedded SRAM (eSRAM) memory-mapped base address.
73
74config PCIE_ECAM_BASE
75 hex
76 default 0xe0000000
77
78config RCBA_BASE
79 hex
80 default 0xfed1c000
81 help
82 Root Complex register block memory-mapped base address.
83
84config ACPI_PM1_BASE
85 hex
86 default 0x1000
87 help
Chris Packhamcdd8df22019-01-13 22:13:22 +1300[diff] [blame]88 ACPI Power Management 1 (PM1) i/o-mapped base address.
Bin Meng81da5a82015-02-02 22:35:27 +0800[diff] [blame]89 This device is defined in ACPI specification, with 16 bytes in size.
90
91config ACPI_PBLK_BASE
92 hex
93 default 0x1010
94 help
95 ACPI Processor Block (PBLK) i/o-mapped base address.
96 This device is defined in ACPI specification, with 16 bytes in size.
97
98config SPI_DMA_BASE
99 hex
100 default 0x1020
101 help
102 SPI DMA i/o-mapped base address.
103
104config GPIO_BASE
105 hex
106 default 0x1080
107 help
108 GPIO i/o-mapped base address.
109
110config ACPI_GPE0_BASE
111 hex
112 default 0x1100
113 help
114 ACPI General Purpose Event 0 (GPE0) i/o-mapped base address.
115 This device is defined in ACPI specification, with 64 bytes in size.
116
117config WDT_BASE
118 hex
119 default 0x1140
120 help
121 Watchdog timer i/o-mapped base address.
122
123config SYS_CAR_ADDR
124 hex
125 default ESRAM_BASE
126
127config SYS_CAR_SIZE
128 hex
129 default 0x8000
130 help
131 Space in bytes in eSRAM used as Cache-As-ARM (CAR).
132 Note this size must not exceed eSRAM's total size.
133
Bin Mengb4315682018-10-13 20:52:11 -0700[diff] [blame]134config X86_TSC_TIMER_EARLY_FREQ
135 int
136 default 400
137
Bin Meng81da5a82015-02-02 22:35:27 +0800[diff] [blame]138endif