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git01.mediatek.com / filogic / uboot / ce9d1b0e48b7a7b7bec1a7852ee25147b6accb99 / . / arch / x86 / cpu / quark / Kconfig
blob: 7ec46e95ef79e0a16b9c70ee5c8f74fa04a0651c [file] [log] [blame]
Bin Meng81da5a82015-02-02 22:35:27 +0800[diff] [blame]1#
2# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3#
4# SPDX-License-Identifier: GPL-2.0+
5#
6
7config INTEL_QUARK
8 bool
9 select HAVE_RMU
Bin Meng6f40e7c2017-07-30 06:23:13 -0700[diff] [blame]10 select ARCH_EARLY_INIT_R
Bin Mengb0d42d72017-07-30 06:23:12 -0700[diff] [blame]11 select ARCH_MISC_INIT
Bin Meng1949a9a2017-07-30 06:23:14 -0700[diff] [blame]12 imply ENABLE_MRC_CACHE
Bin Mengac432012017-07-30 06:23:23 -0700[diff] [blame]13 imply ENV_IS_IN_SPI_FLASH
14 imply ETH_DESIGNWARE
15 imply ICH_SPI
Bin Mengce9d1b02017-07-30 06:23:28 -0700[diff] [blame^]16 imply INTEL_ICH6_GPIO
Bin Mengac432012017-07-30 06:23:23 -0700[diff] [blame]17 imply MMC
18 imply MMC_PCI
19 imply MMC_SDHCI
20 imply MMC_SDHCI_SDMA
21 imply SPI_FLASH
22 imply SYS_NS16550
Bin Meng5b5d1732017-07-30 06:23:27 -0700[diff] [blame]23 imply USB
24 imply USB_EHCI_HCD
Bin Meng81da5a82015-02-02 22:35:27 +0800[diff] [blame]25
26if INTEL_QUARK
27
28config HAVE_RMU
29 bool "Add a Remote Management Unit (RMU) binary"
30 help
31 Select this option to add a Remote Management Unit (RMU) binary
32 to the resulting U-Boot image. It is a data block (up to 64K) of
33 machine-specific code which must be put in the flash for the RMU
34 within the Quark SoC processor to access when powered up before
35 system BIOS is executed.
36
37config RMU_FILE
38 string "Remote Management Unit (RMU) binary filename"
39 depends on HAVE_RMU
40 default "rmu.bin"
41 help
42 The filename of the file to use as Remote Management Unit (RMU)
43 binary in the board directory.
44
45config RMU_ADDR
46 hex "Remote Management Unit (RMU) binary location"
47 depends on HAVE_RMU
48 default 0xfff00000
49 help
50 The location of the RMU binary is determined by a strap. It must be
51 put in flash at a location matching the strap-determined base address.
52
53 The default base address of 0xfff00000 indicates that the binary must
54 be located at offset 0 from the beginning of a 1MB flash device.
55
56config HAVE_CMC
57 bool
58 default HAVE_RMU
59
60config CMC_FILE
61 string
62 depends on HAVE_CMC
63 default RMU_FILE
64
65config CMC_ADDR
66 hex
67 depends on HAVE_CMC
68 default RMU_ADDR
69
70config ESRAM_BASE
71 hex
72 default 0x80000000
73 help
74 Embedded SRAM (eSRAM) memory-mapped base address.
75
76config PCIE_ECAM_BASE
77 hex
78 default 0xe0000000
79
80config RCBA_BASE
81 hex
82 default 0xfed1c000
83 help
84 Root Complex register block memory-mapped base address.
85
86config ACPI_PM1_BASE
87 hex
88 default 0x1000
89 help
90 ACPI Power Managment 1 (PM1) i/o-mapped base address.
91 This device is defined in ACPI specification, with 16 bytes in size.
92
93config ACPI_PBLK_BASE
94 hex
95 default 0x1010
96 help
97 ACPI Processor Block (PBLK) i/o-mapped base address.
98 This device is defined in ACPI specification, with 16 bytes in size.
99
100config SPI_DMA_BASE
101 hex
102 default 0x1020
103 help
104 SPI DMA i/o-mapped base address.
105
106config GPIO_BASE
107 hex
108 default 0x1080
109 help
110 GPIO i/o-mapped base address.
111
112config ACPI_GPE0_BASE
113 hex
114 default 0x1100
115 help
116 ACPI General Purpose Event 0 (GPE0) i/o-mapped base address.
117 This device is defined in ACPI specification, with 64 bytes in size.
118
119config WDT_BASE
120 hex
121 default 0x1140
122 help
123 Watchdog timer i/o-mapped base address.
124
125config SYS_CAR_ADDR
126 hex
127 default ESRAM_BASE
128
129config SYS_CAR_SIZE
130 hex
131 default 0x8000
132 help
133 Space in bytes in eSRAM used as Cache-As-ARM (CAR).
134 Note this size must not exceed eSRAM's total size.
135
Bin Meng81da5a82015-02-02 22:35:27 +0800[diff] [blame]136endif