Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Cadence Sierra PHY Driver |
| 4 | * |
| 5 | * Based on the linux driver provided by Cadence |
| 6 | * |
| 7 | * Copyright (c) 2018 Cadence Design Systems |
| 8 | * Author: Alan Douglas <adouglas@cadence.com> |
| 9 | * |
Nishanth Menon | eaa39c6 | 2023-11-01 15:56:03 -0500 | [diff] [blame] | 10 | * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 11 | * Jean-Jacques Hiblot <jjhiblot@ti.com> |
| 12 | * |
| 13 | */ |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 14 | #include <clk.h> |
Aswath Govindraju | f01608f | 2022-01-28 13:41:50 +0530 | [diff] [blame] | 15 | #include <linux/delay.h> |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 16 | #include <linux/clk-provider.h> |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 17 | #include <generic-phy.h> |
| 18 | #include <reset.h> |
| 19 | #include <dm/device.h> |
| 20 | #include <dm/device-internal.h> |
| 21 | #include <dm/device_compat.h> |
| 22 | #include <dm/lists.h> |
| 23 | #include <dm/read.h> |
| 24 | #include <dm/uclass.h> |
| 25 | #include <dm/devres.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <dt-bindings/phy/phy.h> |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 28 | #include <dt-bindings/phy/phy-cadence.h> |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 29 | #include <regmap.h> |
| 30 | |
Aswath Govindraju | f01608f | 2022-01-28 13:41:50 +0530 | [diff] [blame] | 31 | #define usleep_range(a, b) udelay((b)) |
| 32 | |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 33 | #define NUM_SSC_MODE 3 |
Swapnil Jakhade | 547eec4 | 2022-01-28 13:41:48 +0530 | [diff] [blame] | 34 | #define NUM_PHY_TYPE 4 |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 35 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 36 | /* PHY register offsets */ |
| 37 | #define SIERRA_COMMON_CDB_OFFSET 0x0 |
| 38 | #define SIERRA_MACRO_ID_REG 0x0 |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 39 | #define SIERRA_CMN_PLLLC_GEN_PREG 0x42 |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 40 | #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 |
| 41 | #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 |
| 42 | #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A |
| 43 | #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B |
| 44 | #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F |
| 45 | #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 46 | #define SIERRA_CMN_PLLLC_DSMCORR_PREG 0x51 |
| 47 | #define SIERRA_CMN_PLLLC_SS_PREG 0x52 |
| 48 | #define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG 0x53 |
| 49 | #define SIERRA_CMN_PLLLC_SSTWOPT_PREG 0x54 |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 50 | #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 51 | #define SIERRA_CMN_REFRCV_PREG 0x98 |
| 52 | #define SIERRA_CMN_REFRCV1_PREG 0xB8 |
| 53 | #define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 54 | #define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63 |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 55 | #define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA |
| 56 | #define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0 |
| 57 | #define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2 |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 58 | |
| 59 | #define SIERRA_LANE_CDB_OFFSET(ln, offset) \ |
| 60 | (0x4000 + ((ln) * (0x800 >> (2 - (offset))))) |
| 61 | |
| 62 | #define SIERRA_DET_STANDEC_A_PREG 0x000 |
| 63 | #define SIERRA_DET_STANDEC_B_PREG 0x001 |
| 64 | #define SIERRA_DET_STANDEC_C_PREG 0x002 |
| 65 | #define SIERRA_DET_STANDEC_D_PREG 0x003 |
| 66 | #define SIERRA_DET_STANDEC_E_PREG 0x004 |
| 67 | #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 |
| 68 | #define SIERRA_PSM_A0IN_TMR_PREG 0x009 |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 69 | #define SIERRA_PSM_A3IN_TMR_PREG 0x00C |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 70 | #define SIERRA_PSM_DIAG_PREG 0x015 |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 71 | #define SIERRA_PSC_LN_A3_PREG 0x023 |
| 72 | #define SIERRA_PSC_LN_A4_PREG 0x024 |
| 73 | #define SIERRA_PSC_LN_IDLE_PREG 0x026 |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 74 | #define SIERRA_PSC_TX_A0_PREG 0x028 |
| 75 | #define SIERRA_PSC_TX_A1_PREG 0x029 |
| 76 | #define SIERRA_PSC_TX_A2_PREG 0x02A |
| 77 | #define SIERRA_PSC_TX_A3_PREG 0x02B |
| 78 | #define SIERRA_PSC_RX_A0_PREG 0x030 |
| 79 | #define SIERRA_PSC_RX_A1_PREG 0x031 |
| 80 | #define SIERRA_PSC_RX_A2_PREG 0x032 |
| 81 | #define SIERRA_PSC_RX_A3_PREG 0x033 |
| 82 | #define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 83 | #define SIERRA_PLLCTRL_GEN_A_PREG 0x03B |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 84 | #define SIERRA_PLLCTRL_GEN_D_PREG 0x03E |
| 85 | #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F |
| 86 | #define SIERRA_PLLCTRL_STATUS_PREG 0x044 |
| 87 | #define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B |
| 88 | #define SIERRA_DFE_BIASTRIM_PREG 0x04C |
| 89 | #define SIERRA_DRVCTRL_ATTEN_PREG 0x06A |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 90 | #define SIERRA_DRVCTRL_BOOST_PREG 0x06F |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 91 | #define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 |
| 92 | #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085 |
| 93 | #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086 |
| 94 | #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 |
| 95 | #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 96 | #define SIERRA_CREQ_DCBIASATTEN_OVR_PREG 0x08C |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 97 | #define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 98 | #define SIERRA_RX_CTLE_CAL_PREG 0x08F |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 99 | #define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 |
| 100 | #define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 |
| 101 | #define SIERRA_CREQ_EQ_CTRL_PREG 0x093 |
| 102 | #define SIERRA_CREQ_SPARE_PREG 0x096 |
| 103 | #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097 |
| 104 | #define SIERRA_CTLELUT_CTRL_PREG 0x098 |
| 105 | #define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 |
| 106 | #define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 |
| 107 | #define SIERRA_DEQ_PHALIGN_CTRL 0x0C4 |
| 108 | #define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8 |
| 109 | #define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9 |
| 110 | #define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD |
| 111 | #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE |
| 112 | #define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0 |
| 113 | #define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8 |
| 114 | #define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0 |
| 115 | #define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 |
| 116 | #define SIERRA_DEQ_GLUT0 0x0E8 |
| 117 | #define SIERRA_DEQ_GLUT1 0x0E9 |
| 118 | #define SIERRA_DEQ_GLUT2 0x0EA |
| 119 | #define SIERRA_DEQ_GLUT3 0x0EB |
| 120 | #define SIERRA_DEQ_GLUT4 0x0EC |
| 121 | #define SIERRA_DEQ_GLUT5 0x0ED |
| 122 | #define SIERRA_DEQ_GLUT6 0x0EE |
| 123 | #define SIERRA_DEQ_GLUT7 0x0EF |
| 124 | #define SIERRA_DEQ_GLUT8 0x0F0 |
| 125 | #define SIERRA_DEQ_GLUT9 0x0F1 |
| 126 | #define SIERRA_DEQ_GLUT10 0x0F2 |
| 127 | #define SIERRA_DEQ_GLUT11 0x0F3 |
| 128 | #define SIERRA_DEQ_GLUT12 0x0F4 |
| 129 | #define SIERRA_DEQ_GLUT13 0x0F5 |
| 130 | #define SIERRA_DEQ_GLUT14 0x0F6 |
| 131 | #define SIERRA_DEQ_GLUT15 0x0F7 |
| 132 | #define SIERRA_DEQ_GLUT16 0x0F8 |
| 133 | #define SIERRA_DEQ_ALUT0 0x108 |
| 134 | #define SIERRA_DEQ_ALUT1 0x109 |
| 135 | #define SIERRA_DEQ_ALUT2 0x10A |
| 136 | #define SIERRA_DEQ_ALUT3 0x10B |
| 137 | #define SIERRA_DEQ_ALUT4 0x10C |
| 138 | #define SIERRA_DEQ_ALUT5 0x10D |
| 139 | #define SIERRA_DEQ_ALUT6 0x10E |
| 140 | #define SIERRA_DEQ_ALUT7 0x10F |
| 141 | #define SIERRA_DEQ_ALUT8 0x110 |
| 142 | #define SIERRA_DEQ_ALUT9 0x111 |
| 143 | #define SIERRA_DEQ_ALUT10 0x112 |
| 144 | #define SIERRA_DEQ_ALUT11 0x113 |
| 145 | #define SIERRA_DEQ_ALUT12 0x114 |
| 146 | #define SIERRA_DEQ_ALUT13 0x115 |
| 147 | #define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128 |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 148 | #define SIERRA_DEQ_DFETAP0 0x129 |
| 149 | #define SIERRA_DEQ_DFETAP1 0x12B |
| 150 | #define SIERRA_DEQ_DFETAP2 0x12D |
| 151 | #define SIERRA_DEQ_DFETAP3 0x12F |
| 152 | #define SIERRA_DEQ_DFETAP4 0x131 |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 153 | #define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134 |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 154 | #define SIERRA_DEQ_PRECUR_PREG 0x138 |
| 155 | #define SIERRA_DEQ_POSTCUR_PREG 0x140 |
| 156 | #define SIERRA_DEQ_POSTCUR_DECR_PREG 0x142 |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 157 | #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 |
| 158 | #define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 159 | #define SIERRA_DEQ_TAU_CTRL3_PREG 0x152 |
| 160 | #define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x158 |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 161 | #define SIERRA_DEQ_PICTRL_PREG 0x161 |
| 162 | #define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 |
| 163 | #define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 |
| 164 | #define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174 |
| 165 | #define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 166 | #define SIERRA_CPI_RESBIAS_BIN_PREG 0x17E |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 167 | #define SIERRA_CPI_TRIM_PREG 0x17F |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 168 | #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183 |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 169 | #define SIERRA_EPI_CTRL_PREG 0x187 |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 170 | #define SIERRA_LFPSDET_SUPPORT_PREG 0x188 |
| 171 | #define SIERRA_LFPSFILT_NS_PREG 0x18A |
| 172 | #define SIERRA_LFPSFILT_RD_PREG 0x18B |
| 173 | #define SIERRA_LFPSFILT_MP_PREG 0x18C |
| 174 | #define SIERRA_SIGDET_SUPPORT_PREG 0x190 |
| 175 | #define SIERRA_SDFILT_H2L_A_PREG 0x191 |
| 176 | #define SIERRA_SDFILT_L2H_PREG 0x193 |
| 177 | #define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E |
| 178 | #define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F |
| 179 | #define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0 |
| 180 | #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F |
| 181 | #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 |
| 182 | |
Swapnil Jakhade | 5b6b3dc | 2022-01-28 13:41:43 +0530 | [diff] [blame] | 183 | #define SIERRA_PHY_PCS_COMMON_OFFSET 0xc000 |
Swapnil Jakhade | aa20b30 | 2022-01-28 13:41:44 +0530 | [diff] [blame] | 184 | #define SIERRA_PHY_PIPE_CMN_CTRL1 0x0 |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 185 | #define SIERRA_PHY_PLL_CFG 0xe |
| 186 | |
Swapnil Jakhade | 13a6208 | 2022-01-28 13:41:45 +0530 | [diff] [blame] | 187 | /* PHY PMA common registers */ |
| 188 | #define SIERRA_PHY_PMA_COMMON_OFFSET 0xe000 |
| 189 | #define SIERRA_PHY_PMA_CMN_CTRL 0x0 |
| 190 | |
Swapnil Jakhade | b5c512f | 2022-01-28 13:41:46 +0530 | [diff] [blame] | 191 | /* PHY PCS lane registers */ |
| 192 | #define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, offset) \ |
| 193 | (0xD000 + ((ln) * (0x800 >> (3 - (offset))))) |
| 194 | #define SIERRA_PHY_ISO_LINK_CTRL 0xB |
| 195 | |
Swapnil Jakhade | 547eec4 | 2022-01-28 13:41:48 +0530 | [diff] [blame] | 196 | /* PHY PMA lane registers */ |
| 197 | #define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, offset) \ |
| 198 | (0xF000 + ((ln) * (0x800 >> (3 - (offset))))) |
| 199 | #define SIERRA_PHY_PMA_XCVR_CTRL 0x000 |
| 200 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 201 | #define SIERRA_MACRO_ID 0x00007364 |
| 202 | #define SIERRA_MAX_LANES 16 |
| 203 | #define PLL_LOCK_TIME 100 |
| 204 | |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 205 | #define CDNS_SIERRA_INPUT_CLOCKS 5 |
Kishon Vijay Abraham I | d604252 | 2022-01-28 13:41:33 +0530 | [diff] [blame] | 206 | enum cdns_sierra_clock_input { |
| 207 | PHY_CLK, |
| 208 | CMN_REFCLK_DIG_DIV, |
| 209 | CMN_REFCLK1_DIG_DIV, |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 210 | PLL0_REFCLK, |
| 211 | PLL1_REFCLK, |
Kishon Vijay Abraham I | d604252 | 2022-01-28 13:41:33 +0530 | [diff] [blame] | 212 | }; |
| 213 | |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 214 | #define SIERRA_NUM_CMN_PLLC 2 |
| 215 | #define SIERRA_NUM_CMN_PLLC_PARENTS 2 |
| 216 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 217 | static const struct reg_field macro_id_type = |
| 218 | REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); |
| 219 | static const struct reg_field phy_pll_cfg_1 = |
| 220 | REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); |
Swapnil Jakhade | 13a6208 | 2022-01-28 13:41:45 +0530 | [diff] [blame] | 221 | static const struct reg_field pma_cmn_ready = |
| 222 | REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0); |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 223 | static const struct reg_field pllctrl_lock = |
| 224 | REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); |
Swapnil Jakhade | b5c512f | 2022-01-28 13:41:46 +0530 | [diff] [blame] | 225 | static const struct reg_field phy_iso_link_ctrl_1 = |
| 226 | REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1); |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 227 | |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 228 | static const char * const clk_names[] = { |
| 229 | [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc", |
| 230 | [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1", |
| 231 | }; |
| 232 | |
| 233 | enum cdns_sierra_cmn_plllc { |
| 234 | CMN_PLLLC, |
| 235 | CMN_PLLLC1, |
| 236 | }; |
| 237 | |
| 238 | struct cdns_sierra_pll_mux_reg_fields { |
| 239 | struct reg_field pfdclk_sel_preg; |
| 240 | struct reg_field plllc1en_field; |
| 241 | struct reg_field termen_field; |
| 242 | }; |
| 243 | |
| 244 | static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = { |
| 245 | [CMN_PLLLC] = { |
| 246 | .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1), |
| 247 | .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8), |
| 248 | .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0), |
| 249 | }, |
| 250 | [CMN_PLLLC1] = { |
| 251 | .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1), |
| 252 | .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8), |
| 253 | .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0), |
| 254 | }, |
| 255 | }; |
| 256 | |
| 257 | struct cdns_sierra_pll_mux { |
| 258 | struct cdns_sierra_phy *sp; |
| 259 | struct clk *clk; |
| 260 | struct clk *parent_clks[2]; |
| 261 | struct regmap_field *pfdclk_sel_preg; |
| 262 | struct regmap_field *plllc1en_field; |
| 263 | struct regmap_field *termen_field; |
| 264 | }; |
| 265 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 266 | #define reset_control_assert(rst) cdns_reset_assert(rst) |
| 267 | #define reset_control_deassert(rst) cdns_reset_deassert(rst) |
| 268 | #define reset_control reset_ctl |
| 269 | |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 270 | enum cdns_sierra_phy_type { |
| 271 | TYPE_NONE, |
| 272 | TYPE_PCIE, |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 273 | TYPE_USB, |
| 274 | TYPE_QSGMII |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 275 | }; |
| 276 | |
| 277 | enum cdns_sierra_ssc_mode { |
| 278 | NO_SSC, |
| 279 | EXTERNAL_SSC, |
| 280 | INTERNAL_SSC |
| 281 | }; |
| 282 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 283 | struct cdns_sierra_inst { |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 284 | enum cdns_sierra_phy_type phy_type; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 285 | u32 num_lanes; |
| 286 | u32 mlane; |
| 287 | struct reset_ctl_bulk *lnk_rst; |
Swapnil Jakhade | 0d372ea | 2022-01-28 13:41:42 +0530 | [diff] [blame] | 288 | enum cdns_sierra_ssc_mode ssc_mode; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 289 | }; |
| 290 | |
| 291 | struct cdns_reg_pairs { |
| 292 | u16 val; |
| 293 | u32 off; |
| 294 | }; |
| 295 | |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 296 | struct cdns_sierra_vals { |
| 297 | const struct cdns_reg_pairs *reg_pairs; |
| 298 | u32 num_regs; |
| 299 | }; |
| 300 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 301 | struct cdns_sierra_data { |
| 302 | u32 id_value; |
| 303 | u8 block_offset_shift; |
| 304 | u8 reg_offset_shift; |
Swapnil Jakhade | aa20b30 | 2022-01-28 13:41:44 +0530 | [diff] [blame] | 305 | struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] |
| 306 | [NUM_SSC_MODE]; |
Swapnil Jakhade | 547eec4 | 2022-01-28 13:41:48 +0530 | [diff] [blame] | 307 | struct cdns_sierra_vals *phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] |
| 308 | [NUM_SSC_MODE]; |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 309 | struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] |
| 310 | [NUM_SSC_MODE]; |
| 311 | struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] |
| 312 | [NUM_SSC_MODE]; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 313 | }; |
| 314 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 315 | struct cdns_sierra_phy { |
| 316 | struct udevice *dev; |
| 317 | void *base; |
| 318 | size_t size; |
| 319 | struct regmap *regmap; |
| 320 | struct cdns_sierra_data *init_data; |
Aswath Govindraju | 11fcd0e | 2022-01-28 13:41:35 +0530 | [diff] [blame] | 321 | struct cdns_sierra_inst *phys[SIERRA_MAX_LANES]; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 322 | struct reset_control *phy_rst; |
| 323 | struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; |
Swapnil Jakhade | 5b6b3dc | 2022-01-28 13:41:43 +0530 | [diff] [blame] | 324 | struct regmap *regmap_phy_pcs_common_cdb; |
Swapnil Jakhade | b5c512f | 2022-01-28 13:41:46 +0530 | [diff] [blame] | 325 | struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES]; |
Swapnil Jakhade | 13a6208 | 2022-01-28 13:41:45 +0530 | [diff] [blame] | 326 | struct regmap *regmap_phy_pma_common_cdb; |
Swapnil Jakhade | 547eec4 | 2022-01-28 13:41:48 +0530 | [diff] [blame] | 327 | struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES]; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 328 | struct regmap *regmap_common_cdb; |
| 329 | struct regmap_field *macro_id_type; |
| 330 | struct regmap_field *phy_pll_cfg_1; |
Swapnil Jakhade | 13a6208 | 2022-01-28 13:41:45 +0530 | [diff] [blame] | 331 | struct regmap_field *pma_cmn_ready; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 332 | struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 333 | struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC]; |
| 334 | struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC]; |
| 335 | struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC]; |
Kishon Vijay Abraham I | d604252 | 2022-01-28 13:41:33 +0530 | [diff] [blame] | 336 | struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; |
Swapnil Jakhade | b5c512f | 2022-01-28 13:41:46 +0530 | [diff] [blame] | 337 | struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES]; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 338 | int nsubnodes; |
| 339 | u32 num_lanes; |
| 340 | bool autoconf; |
Aswath Govindraju | f01608f | 2022-01-28 13:41:50 +0530 | [diff] [blame] | 341 | unsigned int already_configured; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 342 | }; |
| 343 | |
| 344 | static inline int cdns_reset_assert(struct reset_control *rst) |
| 345 | { |
| 346 | if (rst) |
| 347 | return reset_assert(rst); |
| 348 | else |
| 349 | return 0; |
| 350 | } |
| 351 | |
| 352 | static inline int cdns_reset_deassert(struct reset_control *rst) |
| 353 | { |
| 354 | if (rst) |
| 355 | return reset_deassert(rst); |
| 356 | else |
| 357 | return 0; |
| 358 | } |
| 359 | |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 360 | static int cdns_sierra_link_init(struct phy *gphy) |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 361 | { |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 362 | struct cdns_sierra_inst *ins = dev_get_priv(gphy->dev); |
| 363 | struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev->parent); |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 364 | struct cdns_sierra_data *init_data = phy->init_data; |
| 365 | struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals; |
| 366 | enum cdns_sierra_phy_type phy_type = ins->phy_type; |
Swapnil Jakhade | 0d372ea | 2022-01-28 13:41:42 +0530 | [diff] [blame] | 367 | enum cdns_sierra_ssc_mode ssc = ins->ssc_mode; |
Swapnil Jakhade | 547eec4 | 2022-01-28 13:41:48 +0530 | [diff] [blame] | 368 | struct cdns_sierra_vals *phy_pma_ln_vals; |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 369 | const struct cdns_reg_pairs *reg_pairs; |
Swapnil Jakhade | aa20b30 | 2022-01-28 13:41:44 +0530 | [diff] [blame] | 370 | struct cdns_sierra_vals *pcs_cmn_vals; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 371 | struct regmap *regmap = phy->regmap; |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 372 | u32 num_regs; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 373 | int i, j; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 374 | |
| 375 | /* Initialise the PHY registers, unless auto configured */ |
Aswath Govindraju | f01608f | 2022-01-28 13:41:50 +0530 | [diff] [blame] | 376 | if (phy->autoconf || phy->already_configured || phy->nsubnodes > 1) |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 377 | return 0; |
| 378 | |
Kishon Vijay Abraham I | d604252 | 2022-01-28 13:41:33 +0530 | [diff] [blame] | 379 | clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); |
| 380 | clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 381 | |
Swapnil Jakhade | aa20b30 | 2022-01-28 13:41:44 +0530 | [diff] [blame] | 382 | /* PHY PCS common registers configurations */ |
| 383 | pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc]; |
| 384 | if (pcs_cmn_vals) { |
| 385 | reg_pairs = pcs_cmn_vals->reg_pairs; |
| 386 | num_regs = pcs_cmn_vals->num_regs; |
| 387 | regmap = phy->regmap_phy_pcs_common_cdb; |
| 388 | for (i = 0; i < num_regs; i++) |
| 389 | regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); |
| 390 | } |
| 391 | |
Swapnil Jakhade | 547eec4 | 2022-01-28 13:41:48 +0530 | [diff] [blame] | 392 | /* PHY PMA lane registers configurations */ |
| 393 | phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc]; |
| 394 | if (phy_pma_ln_vals) { |
| 395 | reg_pairs = phy_pma_ln_vals->reg_pairs; |
| 396 | num_regs = phy_pma_ln_vals->num_regs; |
| 397 | for (i = 0; i < ins->num_lanes; i++) { |
| 398 | regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane]; |
| 399 | for (j = 0; j < num_regs; j++) |
| 400 | regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); |
| 401 | } |
| 402 | } |
| 403 | |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 404 | /* PMA common registers configurations */ |
| 405 | pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc]; |
| 406 | if (pma_cmn_vals) { |
| 407 | reg_pairs = pma_cmn_vals->reg_pairs; |
| 408 | num_regs = pma_cmn_vals->num_regs; |
| 409 | regmap = phy->regmap_common_cdb; |
| 410 | for (i = 0; i < num_regs; i++) |
| 411 | regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 412 | } |
| 413 | |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 414 | /* PMA TX lane registers configurations */ |
| 415 | pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc]; |
| 416 | if (pma_ln_vals) { |
| 417 | reg_pairs = pma_ln_vals->reg_pairs; |
| 418 | num_regs = pma_ln_vals->num_regs; |
| 419 | for (i = 0; i < ins->num_lanes; i++) { |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 420 | regmap = phy->regmap_lane_cdb[i + ins->mlane]; |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 421 | for (j = 0; j < num_regs; j++) |
| 422 | regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 423 | } |
| 424 | } |
| 425 | |
| 426 | return 0; |
| 427 | } |
| 428 | |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 429 | static int cdns_sierra_link_on(struct phy *gphy) |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 430 | { |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 431 | struct cdns_sierra_inst *ins = dev_get_priv(gphy->dev); |
| 432 | struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev->parent); |
| 433 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 434 | struct udevice *dev = gphy->dev; |
| 435 | u32 val; |
| 436 | int ret; |
| 437 | |
Aswath Govindraju | f01608f | 2022-01-28 13:41:50 +0530 | [diff] [blame] | 438 | if (sp->already_configured) { |
| 439 | usleep_range(5000, 10000); |
| 440 | return 0; |
| 441 | } |
| 442 | |
Swapnil Jakhade | 547eec4 | 2022-01-28 13:41:48 +0530 | [diff] [blame] | 443 | if (sp->nsubnodes == 1) { |
| 444 | /* Take the PHY out of reset */ |
| 445 | ret = reset_control_deassert(sp->phy_rst); |
| 446 | if (ret) { |
| 447 | dev_err(dev, "Failed to take the PHY out of reset\n"); |
| 448 | return ret; |
| 449 | } |
Kishon Vijay Abraham I | 1ff2b71 | 2022-01-28 13:41:29 +0530 | [diff] [blame] | 450 | } |
| 451 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 452 | /* Take the PHY lane group out of reset */ |
| 453 | ret = reset_deassert_bulk(ins->lnk_rst); |
| 454 | if (ret) { |
| 455 | dev_err(dev, "Failed to take the PHY lane out of reset\n"); |
| 456 | return ret; |
| 457 | } |
| 458 | |
Swapnil Jakhade | b5c512f | 2022-01-28 13:41:46 +0530 | [diff] [blame] | 459 | if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) { |
| 460 | ret = regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane], |
| 461 | val, !val, 1000, PLL_LOCK_TIME); |
| 462 | if (ret) { |
| 463 | dev_err(dev, "Timeout waiting for PHY status ready\n"); |
| 464 | return ret; |
| 465 | } |
| 466 | } |
| 467 | |
Swapnil Jakhade | 13a6208 | 2022-01-28 13:41:45 +0530 | [diff] [blame] | 468 | /* |
| 469 | * Wait for cmn_ready assertion |
| 470 | * PHY_PMA_CMN_CTRL[0] == 1 |
| 471 | */ |
| 472 | ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val, |
| 473 | 1000, PLL_LOCK_TIME); |
| 474 | if (ret) { |
| 475 | dev_err(dev, "Timeout waiting for CMN ready\n"); |
| 476 | return ret; |
| 477 | } |
| 478 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 479 | ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane], |
| 480 | val, val, 1000, PLL_LOCK_TIME); |
| 481 | if (ret < 0) |
| 482 | dev_err(dev, "PLL lock of lane failed\n"); |
| 483 | |
| 484 | reset_control_assert(sp->phy_rst); |
| 485 | reset_control_deassert(sp->phy_rst); |
| 486 | |
| 487 | return ret; |
| 488 | } |
| 489 | |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 490 | static int cdns_sierra_link_off(struct phy *gphy) |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 491 | { |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 492 | struct cdns_sierra_inst *ins = dev_get_priv(gphy->dev); |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 493 | |
| 494 | return reset_assert_bulk(ins->lnk_rst); |
| 495 | } |
| 496 | |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 497 | static int cdns_sierra_link_reset(struct phy *gphy) |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 498 | { |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 499 | struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev->parent); |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 500 | |
| 501 | reset_control_assert(sp->phy_rst); |
| 502 | reset_control_deassert(sp->phy_rst); |
| 503 | return 0; |
| 504 | }; |
| 505 | |
| 506 | static const struct phy_ops ops = { |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 507 | .init = cdns_sierra_link_init, |
| 508 | .power_on = cdns_sierra_link_on, |
| 509 | .power_off = cdns_sierra_link_off, |
| 510 | .reset = cdns_sierra_link_reset, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 511 | }; |
| 512 | |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 513 | struct cdns_sierra_pll_mux_sel { |
| 514 | enum cdns_sierra_cmn_plllc mux_sel; |
| 515 | u32 table[2]; |
| 516 | const char *node_name; |
| 517 | u32 num_parents; |
| 518 | u32 parents[2]; |
| 519 | }; |
| 520 | |
| 521 | static struct cdns_sierra_pll_mux_sel pll_clk_mux_sel[] = { |
| 522 | { |
| 523 | .num_parents = 2, |
| 524 | .parents = { PLL0_REFCLK, PLL1_REFCLK }, |
| 525 | .mux_sel = CMN_PLLLC, |
| 526 | .table = { 0, 1 }, |
| 527 | .node_name = "pll_cmnlc", |
| 528 | }, |
| 529 | { |
| 530 | .num_parents = 2, |
| 531 | .parents = { PLL1_REFCLK, PLL0_REFCLK }, |
| 532 | .mux_sel = CMN_PLLLC1, |
| 533 | .table = { 1, 0 }, |
| 534 | .node_name = "pll_cmnlc1", |
| 535 | }, |
| 536 | }; |
| 537 | |
| 538 | static int cdns_sierra_pll_mux_set_parent(struct clk *clk, struct clk *parent) |
| 539 | { |
| 540 | struct udevice *dev = clk->dev; |
| 541 | struct cdns_sierra_pll_mux *priv = dev_get_priv(dev); |
| 542 | struct cdns_sierra_pll_mux_sel *data = dev_get_plat(dev); |
| 543 | struct cdns_sierra_phy *sp = priv->sp; |
| 544 | int ret; |
| 545 | int i; |
| 546 | |
| 547 | for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) { |
| 548 | if (parent->dev == priv->parent_clks[i]->dev) |
| 549 | break; |
| 550 | } |
| 551 | |
| 552 | if (i == ARRAY_SIZE(priv->parent_clks)) |
| 553 | return -EINVAL; |
| 554 | |
| 555 | ret = regmap_field_write(sp->cmn_refrcv_refclk_plllc1en_preg[data[clk->id].mux_sel], i); |
| 556 | ret |= regmap_field_write(sp->cmn_refrcv_refclk_termen_preg[data[clk->id].mux_sel], i); |
| 557 | ret |= regmap_field_write(sp->cmn_plllc_pfdclk1_sel_preg[data[clk->id].mux_sel], |
| 558 | data[clk->id].table[i]); |
| 559 | |
| 560 | return ret; |
| 561 | } |
| 562 | |
| 563 | static const struct clk_ops cdns_sierra_pll_mux_ops = { |
| 564 | .set_parent = cdns_sierra_pll_mux_set_parent, |
| 565 | }; |
| 566 | |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 567 | static int cdns_sierra_pll_mux_probe(struct udevice *dev) |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 568 | { |
| 569 | struct cdns_sierra_pll_mux *priv = dev_get_priv(dev); |
| 570 | struct cdns_sierra_phy *sp = dev_get_priv(dev->parent); |
| 571 | struct cdns_sierra_pll_mux_sel *data = dev_get_plat(dev); |
| 572 | struct clk *clk; |
| 573 | int i, j; |
| 574 | |
| 575 | for (j = 0; j < SIERRA_NUM_CMN_PLLC; j++) { |
| 576 | for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) { |
| 577 | clk = sp->input_clks[data[j].parents[i]]; |
| 578 | if (IS_ERR_OR_NULL(clk)) { |
| 579 | dev_err(dev, "No parent clock for PLL mux clocks\n"); |
| 580 | return IS_ERR(clk) ? PTR_ERR(clk) : -ENOENT; |
| 581 | } |
| 582 | priv->parent_clks[i] = clk; |
| 583 | } |
| 584 | } |
| 585 | |
| 586 | priv->sp = dev_get_priv(dev->parent); |
| 587 | |
| 588 | return 0; |
| 589 | } |
| 590 | |
| 591 | U_BOOT_DRIVER(cdns_sierra_pll_mux_clk) = { |
| 592 | .name = "cdns_sierra_mux_clk", |
| 593 | .id = UCLASS_CLK, |
| 594 | .priv_auto = sizeof(struct cdns_sierra_pll_mux), |
| 595 | .ops = &cdns_sierra_pll_mux_ops, |
| 596 | .probe = cdns_sierra_pll_mux_probe, |
| 597 | .plat_auto = sizeof(struct cdns_sierra_pll_mux_sel) * SIERRA_NUM_CMN_PLLC, |
| 598 | }; |
| 599 | |
| 600 | static int cdns_sierra_pll_bind_of_clocks(struct cdns_sierra_phy *sp) |
| 601 | { |
| 602 | struct udevice *dev = sp->dev; |
| 603 | struct driver *cdns_sierra_clk_drv; |
| 604 | struct cdns_sierra_pll_mux_sel *data = pll_clk_mux_sel; |
| 605 | int i, rc; |
| 606 | |
| 607 | cdns_sierra_clk_drv = lists_driver_lookup_name("cdns_sierra_mux_clk"); |
| 608 | if (!cdns_sierra_clk_drv) { |
| 609 | dev_err(dev, "Can not find driver 'cdns_sierra_mux_clk'\n"); |
| 610 | return -ENOENT; |
| 611 | } |
| 612 | |
| 613 | rc = device_bind(dev, cdns_sierra_clk_drv, "pll_mux_clk", |
| 614 | data, dev_ofnode(dev), NULL); |
| 615 | if (rc) { |
| 616 | dev_err(dev, "cannot bind driver for clock %s\n", |
| 617 | clk_names[i]); |
| 618 | } |
| 619 | |
| 620 | return 0; |
| 621 | } |
| 622 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 623 | static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, |
| 624 | ofnode child) |
| 625 | { |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 626 | u32 phy_type; |
| 627 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 628 | if (ofnode_read_u32(child, "reg", &inst->mlane)) |
| 629 | return -EINVAL; |
| 630 | |
| 631 | if (ofnode_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) |
| 632 | return -EINVAL; |
| 633 | |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 634 | if (ofnode_read_u32(child, "cdns,phy-type", &phy_type)) |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 635 | return -EINVAL; |
| 636 | |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 637 | switch (phy_type) { |
| 638 | case PHY_TYPE_PCIE: |
| 639 | inst->phy_type = TYPE_PCIE; |
| 640 | break; |
| 641 | case PHY_TYPE_USB3: |
| 642 | inst->phy_type = TYPE_USB; |
| 643 | break; |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 644 | case PHY_TYPE_QSGMII: |
| 645 | inst->phy_type = TYPE_QSGMII; |
| 646 | break; |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 647 | default: |
| 648 | return -EINVAL; |
| 649 | } |
| 650 | |
Swapnil Jakhade | 0d372ea | 2022-01-28 13:41:42 +0530 | [diff] [blame] | 651 | inst->ssc_mode = EXTERNAL_SSC; |
| 652 | ofnode_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode); |
| 653 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 654 | return 0; |
| 655 | } |
| 656 | |
| 657 | static struct regmap *cdns_regmap_init(struct udevice *dev, void __iomem *base, |
| 658 | u32 block_offset, u8 block_offset_shift, |
| 659 | u8 reg_offset_shift) |
| 660 | { |
| 661 | struct cdns_sierra_phy *sp = dev_get_priv(dev); |
| 662 | struct regmap_config config; |
| 663 | |
| 664 | config.r_start = (ulong)(base + (block_offset << block_offset_shift)); |
| 665 | config.r_size = sp->size - (block_offset << block_offset_shift); |
| 666 | config.reg_offset_shift = reg_offset_shift; |
| 667 | config.width = REGMAP_SIZE_16; |
| 668 | |
| 669 | return devm_regmap_init(dev, NULL, NULL, &config); |
| 670 | } |
| 671 | |
| 672 | static int cdns_regfield_init(struct cdns_sierra_phy *sp) |
| 673 | { |
| 674 | struct udevice *dev = sp->dev; |
| 675 | struct regmap_field *field; |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 676 | struct reg_field reg_field; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 677 | struct regmap *regmap; |
| 678 | int i; |
| 679 | |
| 680 | regmap = sp->regmap_common_cdb; |
| 681 | field = devm_regmap_field_alloc(dev, regmap, macro_id_type); |
| 682 | if (IS_ERR(field)) { |
| 683 | dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); |
| 684 | return PTR_ERR(field); |
| 685 | } |
| 686 | sp->macro_id_type = field; |
| 687 | |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 688 | for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { |
| 689 | reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg; |
| 690 | field = devm_regmap_field_alloc(dev, regmap, reg_field); |
| 691 | if (IS_ERR(field)) { |
| 692 | dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i); |
| 693 | return PTR_ERR(field); |
| 694 | } |
| 695 | sp->cmn_plllc_pfdclk1_sel_preg[i] = field; |
| 696 | |
| 697 | reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field; |
| 698 | field = devm_regmap_field_alloc(dev, regmap, reg_field); |
| 699 | if (IS_ERR(field)) { |
| 700 | dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i); |
| 701 | return PTR_ERR(field); |
| 702 | } |
| 703 | sp->cmn_refrcv_refclk_plllc1en_preg[i] = field; |
| 704 | |
| 705 | reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field; |
| 706 | field = devm_regmap_field_alloc(dev, regmap, reg_field); |
| 707 | if (IS_ERR(field)) { |
| 708 | dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i); |
| 709 | return PTR_ERR(field); |
| 710 | } |
| 711 | sp->cmn_refrcv_refclk_termen_preg[i] = field; |
| 712 | } |
| 713 | |
Swapnil Jakhade | 5b6b3dc | 2022-01-28 13:41:43 +0530 | [diff] [blame] | 714 | regmap = sp->regmap_phy_pcs_common_cdb; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 715 | field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); |
| 716 | if (IS_ERR(field)) { |
| 717 | dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); |
| 718 | return PTR_ERR(field); |
| 719 | } |
| 720 | sp->phy_pll_cfg_1 = field; |
| 721 | |
Swapnil Jakhade | 13a6208 | 2022-01-28 13:41:45 +0530 | [diff] [blame] | 722 | regmap = sp->regmap_phy_pma_common_cdb; |
| 723 | field = devm_regmap_field_alloc(dev, regmap, pma_cmn_ready); |
| 724 | if (IS_ERR(field)) { |
| 725 | dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n"); |
| 726 | return PTR_ERR(field); |
| 727 | } |
| 728 | sp->pma_cmn_ready = field; |
| 729 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 730 | for (i = 0; i < SIERRA_MAX_LANES; i++) { |
| 731 | regmap = sp->regmap_lane_cdb[i]; |
| 732 | field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock); |
| 733 | if (IS_ERR(field)) { |
| 734 | dev_err(dev, "P%d_ENABLE reg field init failed\n", i); |
| 735 | return PTR_ERR(field); |
| 736 | } |
Swapnil Jakhade | b5c512f | 2022-01-28 13:41:46 +0530 | [diff] [blame] | 737 | sp->pllctrl_lock[i] = field; |
| 738 | } |
| 739 | |
| 740 | for (i = 0; i < SIERRA_MAX_LANES; i++) { |
| 741 | regmap = sp->regmap_phy_pcs_lane_cdb[i]; |
| 742 | field = devm_regmap_field_alloc(dev, regmap, phy_iso_link_ctrl_1); |
| 743 | if (IS_ERR(field)) { |
| 744 | dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n", i); |
| 745 | return PTR_ERR(field); |
| 746 | } |
| 747 | sp->phy_iso_link_ctrl_1[i] = field; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 748 | } |
| 749 | |
| 750 | return 0; |
| 751 | } |
| 752 | |
| 753 | static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, |
| 754 | void __iomem *base, u8 block_offset_shift, |
| 755 | u8 reg_offset_shift) |
| 756 | { |
| 757 | struct udevice *dev = sp->dev; |
| 758 | struct regmap *regmap; |
| 759 | u32 block_offset; |
| 760 | int i; |
| 761 | |
| 762 | for (i = 0; i < SIERRA_MAX_LANES; i++) { |
| 763 | block_offset = SIERRA_LANE_CDB_OFFSET(i, reg_offset_shift); |
| 764 | regmap = cdns_regmap_init(dev, base, block_offset, |
| 765 | block_offset_shift, reg_offset_shift); |
| 766 | if (IS_ERR(regmap)) { |
| 767 | dev_err(dev, "Failed to init lane CDB regmap\n"); |
| 768 | return PTR_ERR(regmap); |
| 769 | } |
| 770 | sp->regmap_lane_cdb[i] = regmap; |
| 771 | } |
| 772 | |
| 773 | regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, |
| 774 | block_offset_shift, reg_offset_shift); |
| 775 | if (IS_ERR(regmap)) { |
| 776 | dev_err(dev, "Failed to init common CDB regmap\n"); |
| 777 | return PTR_ERR(regmap); |
| 778 | } |
| 779 | sp->regmap_common_cdb = regmap; |
| 780 | |
Swapnil Jakhade | 5b6b3dc | 2022-01-28 13:41:43 +0530 | [diff] [blame] | 781 | regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PCS_COMMON_OFFSET, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 782 | block_offset_shift, reg_offset_shift); |
| 783 | if (IS_ERR(regmap)) { |
Swapnil Jakhade | 5b6b3dc | 2022-01-28 13:41:43 +0530 | [diff] [blame] | 784 | dev_err(dev, "Failed to init PHY PCS common CDB regmap\n"); |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 785 | return PTR_ERR(regmap); |
| 786 | } |
Swapnil Jakhade | 5b6b3dc | 2022-01-28 13:41:43 +0530 | [diff] [blame] | 787 | sp->regmap_phy_pcs_common_cdb = regmap; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 788 | |
Swapnil Jakhade | b5c512f | 2022-01-28 13:41:46 +0530 | [diff] [blame] | 789 | for (i = 0; i < SIERRA_MAX_LANES; i++) { |
| 790 | block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i, reg_offset_shift); |
| 791 | regmap = cdns_regmap_init(dev, base, block_offset, |
| 792 | block_offset_shift, reg_offset_shift); |
| 793 | if (IS_ERR(regmap)) { |
| 794 | dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n"); |
| 795 | return PTR_ERR(regmap); |
| 796 | } |
| 797 | sp->regmap_phy_pcs_lane_cdb[i] = regmap; |
| 798 | } |
| 799 | |
Swapnil Jakhade | 13a6208 | 2022-01-28 13:41:45 +0530 | [diff] [blame] | 800 | regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PMA_COMMON_OFFSET, |
| 801 | block_offset_shift, reg_offset_shift); |
| 802 | if (IS_ERR(regmap)) { |
| 803 | dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); |
| 804 | return PTR_ERR(regmap); |
| 805 | } |
| 806 | sp->regmap_phy_pma_common_cdb = regmap; |
| 807 | |
Swapnil Jakhade | 547eec4 | 2022-01-28 13:41:48 +0530 | [diff] [blame] | 808 | for (i = 0; i < SIERRA_MAX_LANES; i++) { |
| 809 | block_offset = SIERRA_PHY_PMA_LANE_CDB_OFFSET(i, reg_offset_shift); |
| 810 | regmap = cdns_regmap_init(dev, base, block_offset, |
| 811 | block_offset_shift, reg_offset_shift); |
| 812 | if (IS_ERR(regmap)) { |
| 813 | dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n"); |
| 814 | return PTR_ERR(regmap); |
| 815 | } |
| 816 | sp->regmap_phy_pma_lane_cdb[i] = regmap; |
| 817 | } |
| 818 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 819 | return 0; |
| 820 | } |
| 821 | |
Swapnil Jakhade | 547eec4 | 2022-01-28 13:41:48 +0530 | [diff] [blame] | 822 | static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp) |
| 823 | { |
| 824 | const struct cdns_sierra_data *init_data = sp->init_data; |
| 825 | enum cdns_sierra_phy_type phy_t1, phy_t2, tmp_phy_type; |
| 826 | struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals; |
| 827 | struct cdns_sierra_vals *phy_pma_ln_vals; |
| 828 | const struct cdns_reg_pairs *reg_pairs; |
| 829 | struct cdns_sierra_vals *pcs_cmn_vals; |
| 830 | int i, j, node, mlane, num_lanes, ret; |
| 831 | enum cdns_sierra_ssc_mode ssc; |
| 832 | struct regmap *regmap; |
| 833 | u32 num_regs; |
| 834 | |
| 835 | /* Maximum 2 links (subnodes) are supported */ |
| 836 | if (sp->nsubnodes != 2) |
| 837 | return -EINVAL; |
| 838 | |
| 839 | clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000); |
| 840 | clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); |
| 841 | |
| 842 | /* PHY configured to use both PLL LC and LC1 */ |
| 843 | regmap_field_write(sp->phy_pll_cfg_1, 0x1); |
| 844 | |
| 845 | phy_t1 = sp->phys[0]->phy_type; |
| 846 | phy_t2 = sp->phys[1]->phy_type; |
| 847 | |
| 848 | /* |
| 849 | * First configure the PHY for first link with phy_t1. Get the array |
| 850 | * values as [phy_t1][phy_t2][ssc]. |
| 851 | */ |
| 852 | for (node = 0; node < sp->nsubnodes; node++) { |
| 853 | if (node == 1) { |
| 854 | /* |
| 855 | * If first link with phy_t1 is configured, then |
| 856 | * configure the PHY for second link with phy_t2. |
| 857 | * Get the array values as [phy_t2][phy_t1][ssc]. |
| 858 | */ |
| 859 | tmp_phy_type = phy_t1; |
| 860 | phy_t1 = phy_t2; |
| 861 | phy_t2 = tmp_phy_type; |
| 862 | } |
| 863 | |
| 864 | mlane = sp->phys[node]->mlane; |
| 865 | ssc = sp->phys[node]->ssc_mode; |
| 866 | num_lanes = sp->phys[node]->num_lanes; |
| 867 | |
| 868 | /* PHY PCS common registers configurations */ |
| 869 | pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc]; |
| 870 | if (pcs_cmn_vals) { |
| 871 | reg_pairs = pcs_cmn_vals->reg_pairs; |
| 872 | num_regs = pcs_cmn_vals->num_regs; |
| 873 | regmap = sp->regmap_phy_pcs_common_cdb; |
| 874 | for (i = 0; i < num_regs; i++) |
| 875 | regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); |
| 876 | } |
| 877 | |
| 878 | /* PHY PMA lane registers configurations */ |
| 879 | phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc]; |
| 880 | if (phy_pma_ln_vals) { |
| 881 | reg_pairs = phy_pma_ln_vals->reg_pairs; |
| 882 | num_regs = phy_pma_ln_vals->num_regs; |
| 883 | for (i = 0; i < num_lanes; i++) { |
| 884 | regmap = sp->regmap_phy_pma_lane_cdb[i + mlane]; |
| 885 | for (j = 0; j < num_regs; j++) |
| 886 | regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); |
| 887 | } |
| 888 | } |
| 889 | |
| 890 | /* PMA common registers configurations */ |
| 891 | pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc]; |
| 892 | if (pma_cmn_vals) { |
| 893 | reg_pairs = pma_cmn_vals->reg_pairs; |
| 894 | num_regs = pma_cmn_vals->num_regs; |
| 895 | regmap = sp->regmap_common_cdb; |
| 896 | for (i = 0; i < num_regs; i++) |
| 897 | regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); |
| 898 | } |
| 899 | |
| 900 | /* PMA TX lane registers configurations */ |
| 901 | pma_ln_vals = init_data->pma_ln_vals[phy_t1][phy_t2][ssc]; |
| 902 | if (pma_ln_vals) { |
| 903 | reg_pairs = pma_ln_vals->reg_pairs; |
| 904 | num_regs = pma_ln_vals->num_regs; |
| 905 | for (i = 0; i < num_lanes; i++) { |
| 906 | regmap = sp->regmap_lane_cdb[i + mlane]; |
| 907 | for (j = 0; j < num_regs; j++) |
| 908 | regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); |
| 909 | } |
| 910 | } |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 911 | |
| 912 | if (phy_t1 == TYPE_QSGMII) |
| 913 | reset_deassert_bulk(sp->phys[node]->lnk_rst); |
Swapnil Jakhade | 547eec4 | 2022-01-28 13:41:48 +0530 | [diff] [blame] | 914 | } |
| 915 | |
| 916 | /* Take the PHY out of reset */ |
| 917 | ret = reset_control_deassert(sp->phy_rst); |
| 918 | if (ret) |
| 919 | return ret; |
| 920 | |
| 921 | return 0; |
| 922 | } |
| 923 | |
Kishon Vijay Abraham I | 47d0bcb | 2022-01-28 13:41:31 +0530 | [diff] [blame] | 924 | static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, |
| 925 | struct udevice *dev) |
| 926 | { |
| 927 | struct clk *clk; |
| 928 | int ret; |
| 929 | |
Kishon Vijay Abraham I | 47d0bcb | 2022-01-28 13:41:31 +0530 | [diff] [blame] | 930 | clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); |
| 931 | if (IS_ERR(clk)) { |
| 932 | dev_err(dev, "cmn_refclk_dig_div clock not found\n"); |
| 933 | ret = PTR_ERR(clk); |
| 934 | return ret; |
| 935 | } |
Kishon Vijay Abraham I | d604252 | 2022-01-28 13:41:33 +0530 | [diff] [blame] | 936 | sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; |
Kishon Vijay Abraham I | 47d0bcb | 2022-01-28 13:41:31 +0530 | [diff] [blame] | 937 | |
| 938 | clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); |
| 939 | if (IS_ERR(clk)) { |
| 940 | dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); |
| 941 | ret = PTR_ERR(clk); |
| 942 | return ret; |
| 943 | } |
Kishon Vijay Abraham I | d604252 | 2022-01-28 13:41:33 +0530 | [diff] [blame] | 944 | sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; |
Kishon Vijay Abraham I | 47d0bcb | 2022-01-28 13:41:31 +0530 | [diff] [blame] | 945 | |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 946 | clk = devm_clk_get_optional(dev, "pll0_refclk"); |
| 947 | if (IS_ERR(clk)) { |
| 948 | dev_err(dev, "pll0_refclk clock not found\n"); |
| 949 | ret = PTR_ERR(clk); |
| 950 | return ret; |
| 951 | } |
| 952 | sp->input_clks[PLL0_REFCLK] = clk; |
| 953 | |
| 954 | clk = devm_clk_get_optional(dev, "pll1_refclk"); |
| 955 | if (IS_ERR(clk)) { |
| 956 | dev_err(dev, "pll1_refclk clock not found\n"); |
| 957 | ret = PTR_ERR(clk); |
| 958 | return ret; |
| 959 | } |
| 960 | sp->input_clks[PLL1_REFCLK] = clk; |
| 961 | |
Kishon Vijay Abraham I | 47d0bcb | 2022-01-28 13:41:31 +0530 | [diff] [blame] | 962 | return 0; |
| 963 | } |
| 964 | |
Aswath Govindraju | f01608f | 2022-01-28 13:41:50 +0530 | [diff] [blame] | 965 | static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp) |
| 966 | { |
| 967 | struct udevice *dev = sp->dev; |
| 968 | struct clk *clk; |
| 969 | int ret; |
| 970 | |
| 971 | clk = devm_clk_get_optional(dev, "phy_clk"); |
| 972 | if (IS_ERR(clk)) { |
| 973 | dev_err(dev, "failed to get clock phy_clk\n"); |
| 974 | return PTR_ERR(clk); |
| 975 | } |
| 976 | sp->input_clks[PHY_CLK] = clk; |
| 977 | |
| 978 | ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); |
| 979 | if (ret) |
| 980 | return ret; |
| 981 | |
| 982 | return 0; |
| 983 | } |
Kishon Vijay Abraham I | 12fbc5c | 2022-01-28 13:41:32 +0530 | [diff] [blame] | 984 | static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, |
| 985 | struct udevice *dev) |
| 986 | { |
| 987 | struct reset_control *rst; |
| 988 | |
| 989 | rst = devm_reset_control_get(dev, "sierra_reset"); |
| 990 | if (IS_ERR(rst)) { |
| 991 | dev_err(dev, "failed to get reset\n"); |
| 992 | return PTR_ERR(rst); |
| 993 | } |
| 994 | sp->phy_rst = rst; |
| 995 | |
| 996 | return 0; |
| 997 | } |
| 998 | |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 999 | static int cdns_sierra_phy_bind(struct udevice *dev) |
Aswath Govindraju | 11fcd0e | 2022-01-28 13:41:35 +0530 | [diff] [blame] | 1000 | { |
Aswath Govindraju | 11fcd0e | 2022-01-28 13:41:35 +0530 | [diff] [blame] | 1001 | struct driver *link_drv; |
| 1002 | ofnode child; |
| 1003 | int rc; |
| 1004 | |
| 1005 | link_drv = lists_driver_lookup_name("sierra_phy_link"); |
| 1006 | if (!link_drv) { |
| 1007 | dev_err(dev, "Cannot find driver 'sierra_phy_link'\n"); |
| 1008 | return -ENOENT; |
| 1009 | } |
| 1010 | |
| 1011 | ofnode_for_each_subnode(child, dev_ofnode(dev)) { |
| 1012 | if (!(ofnode_name_eq(child, "phy") || |
| 1013 | ofnode_name_eq(child, "link"))) |
| 1014 | continue; |
| 1015 | |
| 1016 | rc = device_bind(dev, link_drv, "link", NULL, child, NULL); |
| 1017 | if (rc) { |
| 1018 | dev_err(dev, "cannot bind driver for link\n"); |
| 1019 | return rc; |
| 1020 | } |
| 1021 | } |
| 1022 | |
| 1023 | return 0; |
| 1024 | } |
| 1025 | |
| 1026 | static int cdns_sierra_link_probe(struct udevice *dev) |
| 1027 | { |
| 1028 | struct cdns_sierra_inst *inst = dev_get_priv(dev); |
| 1029 | struct cdns_sierra_phy *sp = dev_get_priv(dev->parent); |
| 1030 | struct reset_ctl_bulk *rst; |
| 1031 | int ret, node; |
| 1032 | |
| 1033 | rst = devm_reset_bulk_get_by_node(dev, dev_ofnode(dev)); |
| 1034 | if (IS_ERR(rst)) { |
| 1035 | ret = PTR_ERR(rst); |
| 1036 | dev_err(dev, "failed to get reset\n"); |
| 1037 | return ret; |
| 1038 | } |
| 1039 | inst->lnk_rst = rst; |
| 1040 | |
| 1041 | ret = cdns_sierra_get_optional(inst, dev_ofnode(dev)); |
| 1042 | if (ret) { |
| 1043 | dev_err(dev, "missing property in node\n"); |
| 1044 | return ret; |
| 1045 | } |
| 1046 | node = sp->nsubnodes; |
| 1047 | sp->phys[node] = inst; |
| 1048 | sp->nsubnodes += 1; |
| 1049 | sp->num_lanes += inst->num_lanes; |
| 1050 | |
| 1051 | /* If more than one subnode, configure the PHY as multilink */ |
Aswath Govindraju | f01608f | 2022-01-28 13:41:50 +0530 | [diff] [blame] | 1052 | if (!sp->autoconf && !sp->already_configured && sp->nsubnodes > 1) { |
Swapnil Jakhade | 547eec4 | 2022-01-28 13:41:48 +0530 | [diff] [blame] | 1053 | ret = cdns_sierra_phy_configure_multilink(sp); |
| 1054 | if (ret) |
| 1055 | return ret; |
| 1056 | } |
Aswath Govindraju | 11fcd0e | 2022-01-28 13:41:35 +0530 | [diff] [blame] | 1057 | |
| 1058 | return 0; |
| 1059 | } |
| 1060 | |
| 1061 | U_BOOT_DRIVER(sierra_phy_link) = { |
| 1062 | .name = "sierra_phy_link", |
| 1063 | .id = UCLASS_PHY, |
| 1064 | .probe = cdns_sierra_link_probe, |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 1065 | .ops = &ops, |
Aswath Govindraju | 11fcd0e | 2022-01-28 13:41:35 +0530 | [diff] [blame] | 1066 | .priv_auto = sizeof(struct cdns_sierra_inst), |
| 1067 | }; |
| 1068 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1069 | static int cdns_sierra_phy_probe(struct udevice *dev) |
| 1070 | { |
| 1071 | struct cdns_sierra_phy *sp = dev_get_priv(dev); |
| 1072 | struct cdns_sierra_data *data; |
| 1073 | unsigned int id_value; |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 1074 | int ret; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1075 | |
| 1076 | sp->dev = dev; |
| 1077 | |
| 1078 | sp->base = devfdt_remap_addr_index(dev, 0); |
| 1079 | if (!sp->base) { |
| 1080 | dev_err(dev, "unable to map regs\n"); |
| 1081 | return -ENOMEM; |
| 1082 | } |
| 1083 | devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&sp->size); |
| 1084 | |
| 1085 | /* Get init data for this PHY */ |
| 1086 | data = (struct cdns_sierra_data *)dev_get_driver_data(dev); |
| 1087 | sp->init_data = data; |
| 1088 | |
| 1089 | ret = cdns_regmap_init_blocks(sp, sp->base, data->block_offset_shift, |
| 1090 | data->reg_offset_shift); |
| 1091 | if (ret) |
| 1092 | return ret; |
| 1093 | |
| 1094 | ret = cdns_regfield_init(sp); |
| 1095 | if (ret) |
| 1096 | return ret; |
| 1097 | |
Kishon Vijay Abraham I | 47d0bcb | 2022-01-28 13:41:31 +0530 | [diff] [blame] | 1098 | ret = cdns_sierra_phy_get_clocks(sp, dev); |
| 1099 | if (ret) |
| 1100 | return ret; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1101 | |
Aswath Govindraju | 304341f | 2022-01-28 13:41:36 +0530 | [diff] [blame] | 1102 | ret = cdns_sierra_pll_bind_of_clocks(sp); |
| 1103 | if (ret) |
| 1104 | return ret; |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1105 | |
Aswath Govindraju | f01608f | 2022-01-28 13:41:50 +0530 | [diff] [blame] | 1106 | regmap_field_read(sp->pma_cmn_ready, &sp->already_configured); |
Kishon Vijay Abraham I | 12fbc5c | 2022-01-28 13:41:32 +0530 | [diff] [blame] | 1107 | |
Aswath Govindraju | f01608f | 2022-01-28 13:41:50 +0530 | [diff] [blame] | 1108 | if (!sp->already_configured) { |
| 1109 | ret = cdns_sierra_phy_clk(sp); |
| 1110 | if (ret) |
| 1111 | return ret; |
| 1112 | |
| 1113 | ret = cdns_sierra_phy_get_resets(sp, dev); |
| 1114 | if (ret) |
| 1115 | return ret; |
| 1116 | } |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1117 | |
| 1118 | /* Check that PHY is present */ |
| 1119 | regmap_field_read(sp->macro_id_type, &id_value); |
| 1120 | if (sp->init_data->id_value != id_value) { |
| 1121 | dev_err(dev, "PHY not found 0x%x vs 0x%x\n", |
| 1122 | sp->init_data->id_value, id_value); |
| 1123 | ret = -EINVAL; |
| 1124 | goto clk_disable; |
| 1125 | } |
| 1126 | |
| 1127 | sp->autoconf = dev_read_bool(dev, "cdns,autoconf"); |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1128 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1129 | dev_info(dev, "sierra probed\n"); |
| 1130 | return 0; |
| 1131 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1132 | clk_disable: |
Aswath Govindraju | f01608f | 2022-01-28 13:41:50 +0530 | [diff] [blame] | 1133 | if (!sp->already_configured) |
| 1134 | clk_disable_unprepare(sp->input_clks[PHY_CLK]); |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1135 | return ret; |
| 1136 | } |
| 1137 | |
| 1138 | static int cdns_sierra_phy_remove(struct udevice *dev) |
| 1139 | { |
| 1140 | struct cdns_sierra_phy *phy = dev_get_priv(dev); |
| 1141 | int i; |
| 1142 | |
| 1143 | reset_control_assert(phy->phy_rst); |
| 1144 | |
| 1145 | /* |
| 1146 | * The device level resets will be put automatically. |
| 1147 | * Need to put the subnode resets here though. |
| 1148 | */ |
| 1149 | for (i = 0; i < phy->nsubnodes; i++) |
Aswath Govindraju | 11fcd0e | 2022-01-28 13:41:35 +0530 | [diff] [blame] | 1150 | reset_assert_bulk(phy->phys[i]->lnk_rst); |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1151 | |
Kishon Vijay Abraham I | 25f8b37 | 2022-01-28 13:41:34 +0530 | [diff] [blame] | 1152 | clk_disable_unprepare(phy->input_clks[PHY_CLK]); |
| 1153 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1154 | return 0; |
| 1155 | } |
| 1156 | |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 1157 | /* QSGMII PHY PMA lane configuration */ |
| 1158 | static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = { |
| 1159 | {0x9010, SIERRA_PHY_PMA_XCVR_CTRL} |
| 1160 | }; |
| 1161 | |
| 1162 | static struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = { |
| 1163 | .reg_pairs = qsgmii_phy_pma_ln_regs, |
| 1164 | .num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs), |
| 1165 | }; |
| 1166 | |
| 1167 | /* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */ |
| 1168 | static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = { |
| 1169 | {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG}, |
| 1170 | {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG}, |
| 1171 | {0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG} |
| 1172 | }; |
| 1173 | |
| 1174 | static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = { |
| 1175 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
| 1176 | {0x0252, SIERRA_DET_STANDEC_E_PREG}, |
| 1177 | {0x0004, SIERRA_PSC_LN_IDLE_PREG}, |
| 1178 | {0x0FFE, SIERRA_PSC_RX_A0_PREG}, |
| 1179 | {0x0011, SIERRA_PLLCTRL_SUBRATE_PREG}, |
| 1180 | {0x0001, SIERRA_PLLCTRL_GEN_A_PREG}, |
| 1181 | {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, |
| 1182 | {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, |
| 1183 | {0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
| 1184 | {0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, |
| 1185 | {0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG}, |
| 1186 | {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, |
| 1187 | {0x8422, SIERRA_CTLELUT_CTRL_PREG}, |
| 1188 | {0x4111, SIERRA_DFE_ECMP_RATESEL_PREG}, |
| 1189 | {0x4111, SIERRA_DFE_SMP_RATESEL_PREG}, |
| 1190 | {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, |
| 1191 | {0x9595, SIERRA_DEQ_VGATUNE_CTRL_PREG}, |
| 1192 | {0x0186, SIERRA_DEQ_GLUT0}, |
| 1193 | {0x0186, SIERRA_DEQ_GLUT1}, |
| 1194 | {0x0186, SIERRA_DEQ_GLUT2}, |
| 1195 | {0x0186, SIERRA_DEQ_GLUT3}, |
| 1196 | {0x0186, SIERRA_DEQ_GLUT4}, |
| 1197 | {0x0861, SIERRA_DEQ_ALUT0}, |
| 1198 | {0x07E0, SIERRA_DEQ_ALUT1}, |
| 1199 | {0x079E, SIERRA_DEQ_ALUT2}, |
| 1200 | {0x071D, SIERRA_DEQ_ALUT3}, |
| 1201 | {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG}, |
| 1202 | {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, |
| 1203 | {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
| 1204 | {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG}, |
| 1205 | {0x0033, SIERRA_DEQ_PICTRL_PREG}, |
| 1206 | {0x0660, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, |
| 1207 | {0x00D5, SIERRA_CPI_OUTBUF_RATESEL_PREG}, |
| 1208 | {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG}, |
| 1209 | {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
| 1210 | {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG} |
| 1211 | }; |
| 1212 | |
| 1213 | static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_cmn_vals = { |
| 1214 | .reg_pairs = qsgmii_100_no_ssc_plllc1_cmn_regs, |
| 1215 | .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_cmn_regs), |
| 1216 | }; |
| 1217 | |
| 1218 | static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_ln_vals = { |
| 1219 | .reg_pairs = qsgmii_100_no_ssc_plllc1_ln_regs, |
| 1220 | .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_ln_regs), |
| 1221 | }; |
| 1222 | |
Swapnil Jakhade | aa20b30 | 2022-01-28 13:41:44 +0530 | [diff] [blame] | 1223 | /* PCIE PHY PCS common configuration */ |
| 1224 | static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = { |
| 1225 | {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1} |
| 1226 | }; |
| 1227 | |
| 1228 | static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = { |
| 1229 | .reg_pairs = pcie_phy_pcs_cmn_regs, |
| 1230 | .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs), |
| 1231 | }; |
| 1232 | |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 1233 | /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc, pcie_links_using_plllc, pipe_bw_3 */ |
| 1234 | static const struct cdns_reg_pairs pcie_100_no_ssc_plllc_cmn_regs[] = { |
| 1235 | {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
| 1236 | {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
| 1237 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, |
| 1238 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG} |
| 1239 | }; |
| 1240 | |
| 1241 | /* |
| 1242 | * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc, |
| 1243 | * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz |
| 1244 | */ |
| 1245 | static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = { |
| 1246 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
| 1247 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
| 1248 | {0x0004, SIERRA_PSC_LN_A3_PREG}, |
| 1249 | {0x0004, SIERRA_PSC_LN_A4_PREG}, |
| 1250 | {0x0004, SIERRA_PSC_LN_IDLE_PREG}, |
| 1251 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
| 1252 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
| 1253 | {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
| 1254 | {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
| 1255 | {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
| 1256 | {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
| 1257 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
| 1258 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
| 1259 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
| 1260 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
| 1261 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
| 1262 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
| 1263 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
| 1264 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
| 1265 | {0x0041, SIERRA_DEQ_GLUT0}, |
| 1266 | {0x0082, SIERRA_DEQ_GLUT1}, |
| 1267 | {0x00C3, SIERRA_DEQ_GLUT2}, |
| 1268 | {0x0145, SIERRA_DEQ_GLUT3}, |
| 1269 | {0x0186, SIERRA_DEQ_GLUT4}, |
| 1270 | {0x09E7, SIERRA_DEQ_ALUT0}, |
| 1271 | {0x09A6, SIERRA_DEQ_ALUT1}, |
| 1272 | {0x0965, SIERRA_DEQ_ALUT2}, |
| 1273 | {0x08E3, SIERRA_DEQ_ALUT3}, |
| 1274 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
| 1275 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
| 1276 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
| 1277 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
| 1278 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
| 1279 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
| 1280 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
| 1281 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
| 1282 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
| 1283 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
| 1284 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
| 1285 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 1286 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
| 1287 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
| 1288 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
| 1289 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
| 1290 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
| 1291 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} |
| 1292 | }; |
| 1293 | |
| 1294 | static struct cdns_sierra_vals pcie_100_no_ssc_plllc_cmn_vals = { |
| 1295 | .reg_pairs = pcie_100_no_ssc_plllc_cmn_regs, |
| 1296 | .num_regs = ARRAY_SIZE(pcie_100_no_ssc_plllc_cmn_regs), |
| 1297 | }; |
| 1298 | |
| 1299 | static struct cdns_sierra_vals ml_pcie_100_no_ssc_ln_vals = { |
| 1300 | .reg_pairs = ml_pcie_100_no_ssc_ln_regs, |
| 1301 | .num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_ln_regs), |
| 1302 | }; |
| 1303 | |
| 1304 | /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc, pcie_links_using_plllc, pipe_bw_3 */ |
| 1305 | static const struct cdns_reg_pairs pcie_100_int_ssc_plllc_cmn_regs[] = { |
| 1306 | {0x000E, SIERRA_CMN_PLLLC_MODE_PREG}, |
| 1307 | {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
| 1308 | {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
| 1309 | {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, |
| 1310 | {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, |
| 1311 | {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG}, |
| 1312 | {0x7F80, SIERRA_CMN_PLLLC_SS_PREG}, |
| 1313 | {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG}, |
| 1314 | {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG}, |
| 1315 | {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, |
| 1316 | {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG} |
| 1317 | }; |
| 1318 | |
| 1319 | /* |
| 1320 | * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc, |
| 1321 | * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz |
| 1322 | */ |
| 1323 | static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = { |
| 1324 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
| 1325 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
| 1326 | {0x0004, SIERRA_PSC_LN_A3_PREG}, |
| 1327 | {0x0004, SIERRA_PSC_LN_A4_PREG}, |
| 1328 | {0x0004, SIERRA_PSC_LN_IDLE_PREG}, |
| 1329 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
| 1330 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
| 1331 | {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, |
| 1332 | {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
| 1333 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
| 1334 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
| 1335 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
| 1336 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
| 1337 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
| 1338 | {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, |
| 1339 | {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, |
| 1340 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
| 1341 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
| 1342 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
| 1343 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
| 1344 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
| 1345 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
| 1346 | {0x0041, SIERRA_DEQ_GLUT0}, |
| 1347 | {0x0082, SIERRA_DEQ_GLUT1}, |
| 1348 | {0x00C3, SIERRA_DEQ_GLUT2}, |
| 1349 | {0x0145, SIERRA_DEQ_GLUT3}, |
| 1350 | {0x0186, SIERRA_DEQ_GLUT4}, |
| 1351 | {0x09E7, SIERRA_DEQ_ALUT0}, |
| 1352 | {0x09A6, SIERRA_DEQ_ALUT1}, |
| 1353 | {0x0965, SIERRA_DEQ_ALUT2}, |
| 1354 | {0x08E3, SIERRA_DEQ_ALUT3}, |
| 1355 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
| 1356 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
| 1357 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
| 1358 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
| 1359 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
| 1360 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
| 1361 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
| 1362 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
| 1363 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
| 1364 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
| 1365 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
| 1366 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 1367 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
| 1368 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
| 1369 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
| 1370 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
| 1371 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
| 1372 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} |
| 1373 | }; |
| 1374 | |
| 1375 | static struct cdns_sierra_vals pcie_100_int_ssc_plllc_cmn_vals = { |
| 1376 | .reg_pairs = pcie_100_int_ssc_plllc_cmn_regs, |
| 1377 | .num_regs = ARRAY_SIZE(pcie_100_int_ssc_plllc_cmn_regs), |
| 1378 | }; |
| 1379 | |
| 1380 | static struct cdns_sierra_vals ml_pcie_100_int_ssc_ln_vals = { |
| 1381 | .reg_pairs = ml_pcie_100_int_ssc_ln_regs, |
| 1382 | .num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_ln_regs), |
| 1383 | }; |
| 1384 | |
| 1385 | /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc, pcie_links_using_plllc, pipe_bw_3 */ |
| 1386 | static const struct cdns_reg_pairs pcie_100_ext_ssc_plllc_cmn_regs[] = { |
| 1387 | {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
| 1388 | {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
| 1389 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, |
| 1390 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, |
| 1391 | {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} |
| 1392 | }; |
| 1393 | |
| 1394 | /* |
| 1395 | * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc, |
| 1396 | * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz |
| 1397 | */ |
| 1398 | static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = { |
| 1399 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
| 1400 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
| 1401 | {0x0004, SIERRA_PSC_LN_A3_PREG}, |
| 1402 | {0x0004, SIERRA_PSC_LN_A4_PREG}, |
| 1403 | {0x0004, SIERRA_PSC_LN_IDLE_PREG}, |
| 1404 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
| 1405 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
| 1406 | {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, |
| 1407 | {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
| 1408 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
| 1409 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
| 1410 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
| 1411 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
| 1412 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
| 1413 | {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, |
| 1414 | {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, |
| 1415 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
| 1416 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
| 1417 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
| 1418 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
| 1419 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
| 1420 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
| 1421 | {0x0041, SIERRA_DEQ_GLUT0}, |
| 1422 | {0x0082, SIERRA_DEQ_GLUT1}, |
| 1423 | {0x00C3, SIERRA_DEQ_GLUT2}, |
| 1424 | {0x0145, SIERRA_DEQ_GLUT3}, |
| 1425 | {0x0186, SIERRA_DEQ_GLUT4}, |
| 1426 | {0x09E7, SIERRA_DEQ_ALUT0}, |
| 1427 | {0x09A6, SIERRA_DEQ_ALUT1}, |
| 1428 | {0x0965, SIERRA_DEQ_ALUT2}, |
| 1429 | {0x08E3, SIERRA_DEQ_ALUT3}, |
| 1430 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
| 1431 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
| 1432 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
| 1433 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
| 1434 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
| 1435 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
| 1436 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
| 1437 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
| 1438 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
| 1439 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
| 1440 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
| 1441 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 1442 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
| 1443 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
| 1444 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
| 1445 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
| 1446 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
| 1447 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} |
| 1448 | }; |
| 1449 | |
| 1450 | static struct cdns_sierra_vals pcie_100_ext_ssc_plllc_cmn_vals = { |
| 1451 | .reg_pairs = pcie_100_ext_ssc_plllc_cmn_regs, |
| 1452 | .num_regs = ARRAY_SIZE(pcie_100_ext_ssc_plllc_cmn_regs), |
| 1453 | }; |
| 1454 | |
| 1455 | static struct cdns_sierra_vals ml_pcie_100_ext_ssc_ln_vals = { |
| 1456 | .reg_pairs = ml_pcie_100_ext_ssc_ln_regs, |
| 1457 | .num_regs = ARRAY_SIZE(ml_pcie_100_ext_ssc_ln_regs), |
| 1458 | }; |
| 1459 | |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1460 | /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */ |
| 1461 | static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = { |
| 1462 | {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
| 1463 | {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
| 1464 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, |
| 1465 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG} |
| 1466 | }; |
| 1467 | |
| 1468 | /* refclk100MHz_32b_PCIe_ln_no_ssc */ |
| 1469 | static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = { |
| 1470 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
| 1471 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
| 1472 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
| 1473 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
| 1474 | {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
| 1475 | {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
| 1476 | {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
| 1477 | {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
| 1478 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
| 1479 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
| 1480 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
| 1481 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
| 1482 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
| 1483 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
| 1484 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
| 1485 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
| 1486 | {0x0041, SIERRA_DEQ_GLUT0}, |
| 1487 | {0x0082, SIERRA_DEQ_GLUT1}, |
| 1488 | {0x00C3, SIERRA_DEQ_GLUT2}, |
| 1489 | {0x0145, SIERRA_DEQ_GLUT3}, |
| 1490 | {0x0186, SIERRA_DEQ_GLUT4}, |
| 1491 | {0x09E7, SIERRA_DEQ_ALUT0}, |
| 1492 | {0x09A6, SIERRA_DEQ_ALUT1}, |
| 1493 | {0x0965, SIERRA_DEQ_ALUT2}, |
| 1494 | {0x08E3, SIERRA_DEQ_ALUT3}, |
| 1495 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
| 1496 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
| 1497 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
| 1498 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
| 1499 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
| 1500 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
| 1501 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
| 1502 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
| 1503 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
| 1504 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
| 1505 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
| 1506 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 1507 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
| 1508 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
| 1509 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
| 1510 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
| 1511 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
| 1512 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} |
| 1513 | }; |
| 1514 | |
| 1515 | static struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = { |
| 1516 | .reg_pairs = cdns_pcie_cmn_regs_no_ssc, |
| 1517 | .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_no_ssc), |
| 1518 | }; |
| 1519 | |
| 1520 | static struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = { |
| 1521 | .reg_pairs = cdns_pcie_ln_regs_no_ssc, |
| 1522 | .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_no_ssc), |
| 1523 | }; |
| 1524 | |
| 1525 | /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */ |
| 1526 | static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = { |
| 1527 | {0x000E, SIERRA_CMN_PLLLC_MODE_PREG}, |
| 1528 | {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
| 1529 | {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
| 1530 | {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, |
| 1531 | {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, |
| 1532 | {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG}, |
| 1533 | {0x7F80, SIERRA_CMN_PLLLC_SS_PREG}, |
| 1534 | {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG}, |
| 1535 | {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG}, |
| 1536 | {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, |
| 1537 | {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG} |
| 1538 | }; |
| 1539 | |
| 1540 | /* refclk100MHz_32b_PCIe_ln_int_ssc */ |
| 1541 | static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = { |
| 1542 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
| 1543 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
| 1544 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
| 1545 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
| 1546 | {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, |
| 1547 | {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
| 1548 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
| 1549 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
| 1550 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
| 1551 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
| 1552 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
| 1553 | {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, |
| 1554 | {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, |
| 1555 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
| 1556 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
| 1557 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
| 1558 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
| 1559 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
| 1560 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
| 1561 | {0x0041, SIERRA_DEQ_GLUT0}, |
| 1562 | {0x0082, SIERRA_DEQ_GLUT1}, |
| 1563 | {0x00C3, SIERRA_DEQ_GLUT2}, |
| 1564 | {0x0145, SIERRA_DEQ_GLUT3}, |
| 1565 | {0x0186, SIERRA_DEQ_GLUT4}, |
| 1566 | {0x09E7, SIERRA_DEQ_ALUT0}, |
| 1567 | {0x09A6, SIERRA_DEQ_ALUT1}, |
| 1568 | {0x0965, SIERRA_DEQ_ALUT2}, |
| 1569 | {0x08E3, SIERRA_DEQ_ALUT3}, |
| 1570 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
| 1571 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
| 1572 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
| 1573 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
| 1574 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
| 1575 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
| 1576 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
| 1577 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
| 1578 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
| 1579 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
| 1580 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
| 1581 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 1582 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
| 1583 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
| 1584 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
| 1585 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
| 1586 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
| 1587 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} |
| 1588 | }; |
| 1589 | |
| 1590 | static struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = { |
| 1591 | .reg_pairs = cdns_pcie_cmn_regs_int_ssc, |
| 1592 | .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_int_ssc), |
| 1593 | }; |
| 1594 | |
| 1595 | static struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = { |
| 1596 | .reg_pairs = cdns_pcie_ln_regs_int_ssc, |
| 1597 | .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_int_ssc), |
| 1598 | }; |
| 1599 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1600 | /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ |
| 1601 | static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { |
| 1602 | {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
| 1603 | {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
| 1604 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, |
| 1605 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, |
| 1606 | {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} |
| 1607 | }; |
| 1608 | |
| 1609 | /* refclk100MHz_32b_PCIe_ln_ext_ssc */ |
| 1610 | static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1611 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
| 1612 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
| 1613 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
| 1614 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1615 | {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, |
| 1616 | {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
| 1617 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
| 1618 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
| 1619 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1620 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
| 1621 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1622 | {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1623 | {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, |
| 1624 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
| 1625 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
| 1626 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
| 1627 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
| 1628 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
| 1629 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
| 1630 | {0x0041, SIERRA_DEQ_GLUT0}, |
| 1631 | {0x0082, SIERRA_DEQ_GLUT1}, |
| 1632 | {0x00C3, SIERRA_DEQ_GLUT2}, |
| 1633 | {0x0145, SIERRA_DEQ_GLUT3}, |
| 1634 | {0x0186, SIERRA_DEQ_GLUT4}, |
| 1635 | {0x09E7, SIERRA_DEQ_ALUT0}, |
| 1636 | {0x09A6, SIERRA_DEQ_ALUT1}, |
| 1637 | {0x0965, SIERRA_DEQ_ALUT2}, |
| 1638 | {0x08E3, SIERRA_DEQ_ALUT3}, |
| 1639 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
| 1640 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
| 1641 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
| 1642 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
| 1643 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
| 1644 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
| 1645 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
| 1646 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
| 1647 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
| 1648 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
| 1649 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
| 1650 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 1651 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
| 1652 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
| 1653 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
| 1654 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
| 1655 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
| 1656 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1657 | }; |
| 1658 | |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1659 | static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = { |
| 1660 | .reg_pairs = cdns_pcie_cmn_regs_ext_ssc, |
| 1661 | .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), |
| 1662 | }; |
| 1663 | |
| 1664 | static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = { |
| 1665 | .reg_pairs = cdns_pcie_ln_regs_ext_ssc, |
| 1666 | .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), |
| 1667 | }; |
| 1668 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1669 | /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ |
| 1670 | static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { |
| 1671 | {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
| 1672 | {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
| 1673 | {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, |
| 1674 | {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} |
| 1675 | }; |
| 1676 | |
| 1677 | /* refclk100MHz_20b_USB_ln_ext_ssc */ |
| 1678 | static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { |
| 1679 | {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, |
| 1680 | {0x000F, SIERRA_DET_STANDEC_B_PREG}, |
Sanket Parmar | a366626 | 2022-01-28 13:41:28 +0530 | [diff] [blame] | 1681 | {0x55A5, SIERRA_DET_STANDEC_C_PREG}, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1682 | {0x69ad, SIERRA_DET_STANDEC_D_PREG}, |
| 1683 | {0x0241, SIERRA_DET_STANDEC_E_PREG}, |
Sanket Parmar | a366626 | 2022-01-28 13:41:28 +0530 | [diff] [blame] | 1684 | {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1685 | {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, |
| 1686 | {0xCF00, SIERRA_PSM_DIAG_PREG}, |
| 1687 | {0x001F, SIERRA_PSC_TX_A0_PREG}, |
| 1688 | {0x0007, SIERRA_PSC_TX_A1_PREG}, |
| 1689 | {0x0003, SIERRA_PSC_TX_A2_PREG}, |
| 1690 | {0x0003, SIERRA_PSC_TX_A3_PREG}, |
| 1691 | {0x0FFF, SIERRA_PSC_RX_A0_PREG}, |
Sanket Parmar | a366626 | 2022-01-28 13:41:28 +0530 | [diff] [blame] | 1692 | {0x0003, SIERRA_PSC_RX_A1_PREG}, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1693 | {0x0003, SIERRA_PSC_RX_A2_PREG}, |
| 1694 | {0x0001, SIERRA_PSC_RX_A3_PREG}, |
| 1695 | {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, |
| 1696 | {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, |
| 1697 | {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, |
| 1698 | {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, |
| 1699 | {0x2512, SIERRA_DFE_BIASTRIM_PREG}, |
| 1700 | {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, |
Sanket Parmar | a366626 | 2022-01-28 13:41:28 +0530 | [diff] [blame] | 1701 | {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, |
| 1702 | {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
| 1703 | {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1704 | {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, |
Sanket Parmar | a366626 | 2022-01-28 13:41:28 +0530 | [diff] [blame] | 1705 | {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1706 | {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, |
| 1707 | {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, |
Sanket Parmar | a366626 | 2022-01-28 13:41:28 +0530 | [diff] [blame] | 1708 | {0x0000, SIERRA_CREQ_SPARE_PREG}, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1709 | {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, |
Sanket Parmar | a366626 | 2022-01-28 13:41:28 +0530 | [diff] [blame] | 1710 | {0x8452, SIERRA_CTLELUT_CTRL_PREG}, |
| 1711 | {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, |
| 1712 | {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, |
| 1713 | {0x0003, SIERRA_DEQ_PHALIGN_CTRL}, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1714 | {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, |
| 1715 | {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
| 1716 | {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
| 1717 | {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
| 1718 | {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
| 1719 | {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
| 1720 | {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, |
Sanket Parmar | a366626 | 2022-01-28 13:41:28 +0530 | [diff] [blame] | 1721 | {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG}, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1722 | {0x0014, SIERRA_DEQ_GLUT0}, |
| 1723 | {0x0014, SIERRA_DEQ_GLUT1}, |
| 1724 | {0x0014, SIERRA_DEQ_GLUT2}, |
| 1725 | {0x0014, SIERRA_DEQ_GLUT3}, |
| 1726 | {0x0014, SIERRA_DEQ_GLUT4}, |
| 1727 | {0x0014, SIERRA_DEQ_GLUT5}, |
| 1728 | {0x0014, SIERRA_DEQ_GLUT6}, |
| 1729 | {0x0014, SIERRA_DEQ_GLUT7}, |
| 1730 | {0x0014, SIERRA_DEQ_GLUT8}, |
| 1731 | {0x0014, SIERRA_DEQ_GLUT9}, |
| 1732 | {0x0014, SIERRA_DEQ_GLUT10}, |
| 1733 | {0x0014, SIERRA_DEQ_GLUT11}, |
| 1734 | {0x0014, SIERRA_DEQ_GLUT12}, |
| 1735 | {0x0014, SIERRA_DEQ_GLUT13}, |
| 1736 | {0x0014, SIERRA_DEQ_GLUT14}, |
| 1737 | {0x0014, SIERRA_DEQ_GLUT15}, |
| 1738 | {0x0014, SIERRA_DEQ_GLUT16}, |
| 1739 | {0x0BAE, SIERRA_DEQ_ALUT0}, |
| 1740 | {0x0AEB, SIERRA_DEQ_ALUT1}, |
| 1741 | {0x0A28, SIERRA_DEQ_ALUT2}, |
| 1742 | {0x0965, SIERRA_DEQ_ALUT3}, |
| 1743 | {0x08A2, SIERRA_DEQ_ALUT4}, |
| 1744 | {0x07DF, SIERRA_DEQ_ALUT5}, |
| 1745 | {0x071C, SIERRA_DEQ_ALUT6}, |
| 1746 | {0x0659, SIERRA_DEQ_ALUT7}, |
| 1747 | {0x0596, SIERRA_DEQ_ALUT8}, |
| 1748 | {0x0514, SIERRA_DEQ_ALUT9}, |
| 1749 | {0x0492, SIERRA_DEQ_ALUT10}, |
| 1750 | {0x0410, SIERRA_DEQ_ALUT11}, |
| 1751 | {0x038E, SIERRA_DEQ_ALUT12}, |
| 1752 | {0x030C, SIERRA_DEQ_ALUT13}, |
| 1753 | {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, |
| 1754 | {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, |
| 1755 | {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, |
| 1756 | {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
| 1757 | {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, |
| 1758 | {0x0033, SIERRA_DEQ_PICTRL_PREG}, |
| 1759 | {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG}, |
| 1760 | {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, |
| 1761 | {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, |
| 1762 | {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, |
| 1763 | {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, |
| 1764 | {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, |
| 1765 | {0x000F, SIERRA_LFPSFILT_NS_PREG}, |
| 1766 | {0x0009, SIERRA_LFPSFILT_RD_PREG}, |
| 1767 | {0x0001, SIERRA_LFPSFILT_MP_PREG}, |
Sanket Parmar | a366626 | 2022-01-28 13:41:28 +0530 | [diff] [blame] | 1768 | {0x6013, SIERRA_SIGDET_SUPPORT_PREG}, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1769 | {0x8013, SIERRA_SDFILT_H2L_A_PREG}, |
| 1770 | {0x8009, SIERRA_SDFILT_L2H_PREG}, |
| 1771 | {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
| 1772 | {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
| 1773 | {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} |
| 1774 | }; |
| 1775 | |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1776 | static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = { |
| 1777 | .reg_pairs = cdns_usb_cmn_regs_ext_ssc, |
| 1778 | .num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), |
| 1779 | }; |
| 1780 | |
| 1781 | static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = { |
| 1782 | .reg_pairs = cdns_usb_ln_regs_ext_ssc, |
| 1783 | .num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), |
| 1784 | }; |
| 1785 | |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1786 | static const struct cdns_sierra_data cdns_map_sierra = { |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1787 | .id_value = SIERRA_MACRO_ID, |
| 1788 | .block_offset_shift = 0x2, |
| 1789 | .reg_offset_shift = 0x2, |
Swapnil Jakhade | aa20b30 | 2022-01-28 13:41:44 +0530 | [diff] [blame] | 1790 | .pcs_cmn_vals = { |
| 1791 | [TYPE_PCIE] = { |
| 1792 | [TYPE_NONE] = { |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1793 | [NO_SSC] = &pcie_phy_pcs_cmn_vals, |
Swapnil Jakhade | aa20b30 | 2022-01-28 13:41:44 +0530 | [diff] [blame] | 1794 | [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1795 | [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
Swapnil Jakhade | aa20b30 | 2022-01-28 13:41:44 +0530 | [diff] [blame] | 1796 | }, |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 1797 | [TYPE_QSGMII] = { |
| 1798 | [NO_SSC] = &pcie_phy_pcs_cmn_vals, |
| 1799 | [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
| 1800 | [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
| 1801 | }, |
Swapnil Jakhade | aa20b30 | 2022-01-28 13:41:44 +0530 | [diff] [blame] | 1802 | }, |
| 1803 | }, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1804 | .pma_cmn_vals = { |
| 1805 | [TYPE_PCIE] = { |
| 1806 | [TYPE_NONE] = { |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1807 | [NO_SSC] = &pcie_100_no_ssc_cmn_vals, |
| 1808 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals, |
| 1809 | [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1810 | }, |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 1811 | [TYPE_QSGMII] = { |
| 1812 | [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, |
| 1813 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, |
| 1814 | [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, |
| 1815 | }, |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1816 | }, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1817 | [TYPE_USB] = { |
| 1818 | [TYPE_NONE] = { |
| 1819 | [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, |
| 1820 | }, |
| 1821 | }, |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 1822 | [TYPE_QSGMII] = { |
| 1823 | [TYPE_PCIE] = { |
| 1824 | [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, |
| 1825 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, |
| 1826 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, |
| 1827 | }, |
| 1828 | }, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1829 | }, |
| 1830 | .pma_ln_vals = { |
| 1831 | [TYPE_PCIE] = { |
| 1832 | [TYPE_NONE] = { |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1833 | [NO_SSC] = &pcie_100_no_ssc_ln_vals, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1834 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals, |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1835 | [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1836 | }, |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 1837 | [TYPE_QSGMII] = { |
| 1838 | [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals, |
| 1839 | [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, |
| 1840 | [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, |
| 1841 | }, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1842 | }, |
| 1843 | [TYPE_USB] = { |
| 1844 | [TYPE_NONE] = { |
| 1845 | [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, |
| 1846 | }, |
| 1847 | }, |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 1848 | [TYPE_QSGMII] = { |
| 1849 | [TYPE_PCIE] = { |
| 1850 | [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, |
| 1851 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, |
| 1852 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, |
| 1853 | }, |
| 1854 | }, |
| 1855 | |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1856 | }, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1857 | }; |
| 1858 | |
| 1859 | static const struct cdns_sierra_data cdns_ti_map_sierra = { |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1860 | .id_value = SIERRA_MACRO_ID, |
| 1861 | .block_offset_shift = 0x0, |
| 1862 | .reg_offset_shift = 0x1, |
Swapnil Jakhade | aa20b30 | 2022-01-28 13:41:44 +0530 | [diff] [blame] | 1863 | .pcs_cmn_vals = { |
| 1864 | [TYPE_PCIE] = { |
| 1865 | [TYPE_NONE] = { |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1866 | [NO_SSC] = &pcie_phy_pcs_cmn_vals, |
Swapnil Jakhade | aa20b30 | 2022-01-28 13:41:44 +0530 | [diff] [blame] | 1867 | [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1868 | [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
Swapnil Jakhade | aa20b30 | 2022-01-28 13:41:44 +0530 | [diff] [blame] | 1869 | }, |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 1870 | [TYPE_QSGMII] = { |
| 1871 | [NO_SSC] = &pcie_phy_pcs_cmn_vals, |
| 1872 | [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
| 1873 | [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
| 1874 | }, |
| 1875 | }, |
| 1876 | }, |
| 1877 | .phy_pma_ln_vals = { |
| 1878 | [TYPE_QSGMII] = { |
| 1879 | [TYPE_PCIE] = { |
| 1880 | [NO_SSC] = &qsgmii_phy_pma_ln_vals, |
| 1881 | [EXTERNAL_SSC] = &qsgmii_phy_pma_ln_vals, |
| 1882 | [INTERNAL_SSC] = &qsgmii_phy_pma_ln_vals, |
| 1883 | }, |
Swapnil Jakhade | aa20b30 | 2022-01-28 13:41:44 +0530 | [diff] [blame] | 1884 | }, |
| 1885 | }, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1886 | .pma_cmn_vals = { |
| 1887 | [TYPE_PCIE] = { |
| 1888 | [TYPE_NONE] = { |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1889 | [NO_SSC] = &pcie_100_no_ssc_cmn_vals, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1890 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals, |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1891 | [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1892 | }, |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 1893 | [TYPE_QSGMII] = { |
| 1894 | [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, |
| 1895 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, |
| 1896 | [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, |
| 1897 | }, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1898 | }, |
| 1899 | [TYPE_USB] = { |
| 1900 | [TYPE_NONE] = { |
| 1901 | [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, |
| 1902 | }, |
| 1903 | }, |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 1904 | [TYPE_QSGMII] = { |
| 1905 | [TYPE_PCIE] = { |
| 1906 | [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, |
| 1907 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, |
| 1908 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, |
| 1909 | }, |
| 1910 | }, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1911 | }, |
| 1912 | .pma_ln_vals = { |
| 1913 | [TYPE_PCIE] = { |
| 1914 | [TYPE_NONE] = { |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1915 | [NO_SSC] = &pcie_100_no_ssc_ln_vals, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1916 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals, |
Swapnil Jakhade | 7b7f88b | 2022-01-28 13:41:47 +0530 | [diff] [blame] | 1917 | [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1918 | }, |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 1919 | [TYPE_QSGMII] = { |
| 1920 | [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals, |
| 1921 | [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, |
| 1922 | [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, |
| 1923 | }, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1924 | }, |
| 1925 | [TYPE_USB] = { |
| 1926 | [TYPE_NONE] = { |
| 1927 | [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, |
| 1928 | }, |
| 1929 | }, |
Swapnil Jakhade | e51f3e5 | 2022-01-28 13:41:49 +0530 | [diff] [blame] | 1930 | [TYPE_QSGMII] = { |
| 1931 | [TYPE_PCIE] = { |
| 1932 | [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, |
| 1933 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, |
| 1934 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, |
| 1935 | }, |
| 1936 | }, |
Swapnil Jakhade | e42a847 | 2022-01-28 13:41:40 +0530 | [diff] [blame] | 1937 | }, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1938 | }; |
| 1939 | |
| 1940 | static const struct udevice_id cdns_sierra_id_table[] = { |
| 1941 | { |
| 1942 | .compatible = "cdns,sierra-phy-t0", |
| 1943 | .data = (ulong)&cdns_map_sierra, |
| 1944 | }, |
| 1945 | { |
| 1946 | .compatible = "ti,sierra-phy-t0", |
| 1947 | .data = (ulong)&cdns_ti_map_sierra, |
| 1948 | }, |
| 1949 | {} |
| 1950 | }; |
| 1951 | |
| 1952 | U_BOOT_DRIVER(sierra_phy_provider) = { |
| 1953 | .name = "cdns,sierra", |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 1954 | .id = UCLASS_MISC, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1955 | .of_match = cdns_sierra_id_table, |
| 1956 | .probe = cdns_sierra_phy_probe, |
| 1957 | .remove = cdns_sierra_phy_remove, |
Aswath Govindraju | ac7540f | 2022-03-04 17:45:25 +0530 | [diff] [blame] | 1958 | .bind = cdns_sierra_phy_bind, |
Alan Douglas | fda76da | 2021-07-21 21:28:36 +0530 | [diff] [blame] | 1959 | .priv_auto = sizeof(struct cdns_sierra_phy), |
| 1960 | }; |