Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2019 Marvell International Ltd. |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 6 | #include <clk.h> |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 7 | #include <cpu_func.h> |
| 8 | #include <dm.h> |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 9 | #include <dm/device-internal.h> |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 10 | #include <dm/lists.h> |
| 11 | #include <env.h> |
| 12 | #include <errno.h> |
| 13 | #include <fdtdec.h> |
| 14 | #include <log.h> |
| 15 | #include <malloc.h> |
| 16 | #include <memalign.h> |
| 17 | #include <mmc.h> |
| 18 | #include <part.h> |
| 19 | #include <pci.h> |
| 20 | #include <pci_ids.h> |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 21 | #include <power/regulator.h> |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 22 | #include <time.h> |
| 23 | #include <watchdog.h> |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 24 | #include <asm/io.h> |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 25 | #include <linux/delay.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/libfdt.h> |
| 28 | |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 29 | #if defined(CONFIG_ARCH_OCTEON) |
| 30 | #include <mach/octeon-model.h> |
| 31 | #include <mach/cvmx-regs.h> |
| 32 | #include <mach/cvmx-mio-emm-defs.h> |
| 33 | #else |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 34 | #include <asm/arch/board.h> |
| 35 | #include <asm/arch/clock.h> |
| 36 | #include <asm/arch/csrs/csrs-mio_emm.h> |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 37 | #endif |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 38 | |
| 39 | #include "octeontx_hsmmc.h" |
| 40 | |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 41 | /* Use dummy implementation for MIPS Octeon to always return false */ |
| 42 | #if defined(CONFIG_ARCH_OCTEON) |
| 43 | #define otx_is_soc(ver) 0 |
| 44 | #endif |
| 45 | |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 46 | #define MMC_TIMEOUT_SHORT 20 /* in ms */ |
| 47 | #define MMC_TIMEOUT_LONG 1000 |
| 48 | #define MMC_TIMEOUT_ERASE 10000 |
| 49 | |
| 50 | #define MMC_DEFAULT_DATA_IN_TAP 10 |
| 51 | #define MMC_DEFAULT_CMD_IN_TAP 10 |
| 52 | #define MMC_DEFAULT_CMD_OUT_TAP 39 |
| 53 | #define MMC_DEFAULT_DATA_OUT_TAP 39 |
| 54 | #define MMC_DEFAULT_HS200_CMD_IN_TAP 24 |
| 55 | #define MMC_DEFAULT_HS200_DATA_IN_TAP 24 |
| 56 | #define MMC_DEFAULT_HS200_CMD_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5) |
| 57 | #define MMC_DEFAULT_HS200_DATA_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5) |
| 58 | #define MMC_DEFAULT_HS400_CMD_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5) |
| 59 | #define MMC_DEFAULT_HS400_DATA_OUT_TAP (otx_is_soc(CN95XX) ? 5 : 3) |
| 60 | #define MMC_DEFAULT_HS200_CMD_OUT_DLY 800 /* Delay in ps */ |
| 61 | #define MMC_DEFAULT_HS200_DATA_OUT_DLY 800 /* Delay in ps */ |
| 62 | #define MMC_DEFAULT_HS400_CMD_OUT_DLY 800 /* Delay in ps */ |
| 63 | #define MMC_DEFAULT_HS400_DATA_OUT_DLY 400 /* Delay in ps */ |
| 64 | #define MMC_DEFAULT_SD_UHS_SDR104_CMD_OUT_TAP MMC_DEFAULT_HS200_CMD_OUT_TAP |
| 65 | #define MMC_DEFAULT_SD_UHS_SDR104_DATA_OUT_TAP MMC_DEFAULT_HS200_DATA_OUT_TAP |
| 66 | #define MMC_LEGACY_DEFAULT_CMD_OUT_TAP 39 |
| 67 | #define MMC_LEGACY_DEFAULT_DATA_OUT_TAP 39 |
| 68 | #define MMC_SD_LEGACY_DEFAULT_CMD_OUT_TAP 63 |
| 69 | #define MMC_SD_LEGACY_DEFAULT_DATA_OUT_TAP 63 |
| 70 | #define MMC_HS_CMD_OUT_TAP 32 |
| 71 | #define MMC_HS_DATA_OUT_TAP 32 |
| 72 | #define MMC_SD_HS_CMD_OUT_TAP 26 |
| 73 | #define MMC_SD_HS_DATA_OUT_TAP 26 |
| 74 | #define MMC_SD_UHS_SDR25_CMD_OUT_TAP 26 |
| 75 | #define MMC_SD_UHS_SDR25_DATA_OUT_TAP 26 |
| 76 | #define MMC_SD_UHS_SDR50_CMD_OUT_TAP 26 |
| 77 | #define MMC_SD_UHS_SDR50_DATA_OUT_TAP 26 |
| 78 | #define MMC_DEFAULT_TAP_DELAY 4 |
| 79 | #define TOTAL_NO_OF_TAPS 512 |
| 80 | static void octeontx_mmc_switch_to(struct mmc *mmc); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 81 | static void set_wdog(struct mmc *mmc, u64 us); |
| 82 | static void do_switch(struct mmc *mmc, union mio_emm_switch emm_switch); |
| 83 | static int octeontx_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
| 84 | struct mmc_data *data); |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 85 | static int octeontx_mmc_configure_delay(struct mmc *mmc); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 86 | static int octeontx_mmc_calibrate_delay(struct mmc *mmc); |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 87 | #if !defined(CONFIG_ARCH_OCTEON) |
| 88 | static int octeontx2_mmc_calc_delay(struct mmc *mmc, int delay); |
| 89 | static void octeontx_mmc_set_timing(struct mmc *mmc); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 90 | static int octeontx_mmc_set_input_bus_timing(struct mmc *mmc); |
| 91 | static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc); |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 92 | #endif |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 93 | |
| 94 | static bool host_probed; |
| 95 | |
| 96 | /** |
| 97 | * Get the slot data structure from a MMC data structure |
| 98 | */ |
| 99 | static inline struct octeontx_mmc_slot *mmc_to_slot(struct mmc *mmc) |
| 100 | { |
| 101 | return container_of(mmc, struct octeontx_mmc_slot, mmc); |
| 102 | } |
| 103 | |
| 104 | static inline struct octeontx_mmc_host *mmc_to_host(struct mmc *mmc) |
| 105 | { |
| 106 | return mmc_to_slot(mmc)->host; |
| 107 | } |
| 108 | |
| 109 | static inline struct octeontx_mmc_slot *dev_to_mmc_slot(struct udevice *dev) |
| 110 | { |
| 111 | return dev_get_priv(dev); |
| 112 | } |
| 113 | |
| 114 | static inline struct mmc *dev_to_mmc(struct udevice *dev) |
| 115 | { |
| 116 | return &((struct octeontx_mmc_slot *)dev_get_priv(dev))->mmc; |
| 117 | } |
| 118 | |
| 119 | #ifdef DEBUG |
| 120 | const char *mmc_reg_str(u64 reg) |
| 121 | { |
| 122 | if (reg == MIO_EMM_DMA_CFG()) |
| 123 | return "MIO_EMM_DMA_CFG"; |
| 124 | if (reg == MIO_EMM_DMA_ADR()) |
| 125 | return "MIO_EMM_DMA_ADR"; |
| 126 | if (reg == MIO_EMM_DMA_INT()) |
| 127 | return "MIO_EMM_DMA_INT"; |
| 128 | if (reg == MIO_EMM_CFG()) |
| 129 | return "MIO_EMM_CFG"; |
| 130 | if (reg == MIO_EMM_MODEX(0)) |
| 131 | return "MIO_EMM_MODE0"; |
| 132 | if (reg == MIO_EMM_MODEX(1)) |
| 133 | return "MIO_EMM_MODE1"; |
| 134 | if (reg == MIO_EMM_MODEX(2)) |
| 135 | return "MIO_EMM_MODE2"; |
| 136 | if (reg == MIO_EMM_MODEX(3)) |
| 137 | return "MIO_EMM_MODE3"; |
| 138 | if (reg == MIO_EMM_IO_CTL()) |
| 139 | return "MIO_EMM_IO_CTL"; |
| 140 | if (reg == MIO_EMM_SWITCH()) |
| 141 | return "MIO_EMM_SWITCH"; |
| 142 | if (reg == MIO_EMM_DMA()) |
| 143 | return "MIO_EMM_DMA"; |
| 144 | if (reg == MIO_EMM_CMD()) |
| 145 | return "MIO_EMM_CMD"; |
| 146 | if (reg == MIO_EMM_RSP_STS()) |
| 147 | return "MIO_EMM_RSP_STS"; |
| 148 | if (reg == MIO_EMM_RSP_LO()) |
| 149 | return "MIO_EMM_RSP_LO"; |
| 150 | if (reg == MIO_EMM_RSP_HI()) |
| 151 | return "MIO_EMM_RSP_HI"; |
| 152 | if (reg == MIO_EMM_INT()) |
| 153 | return "MIO_EMM_INT"; |
| 154 | if (reg == MIO_EMM_WDOG()) |
| 155 | return "MIO_EMM_WDOG"; |
| 156 | if (reg == MIO_EMM_DMA_ARG()) |
| 157 | return "MIO_EMM_DMA_ARG"; |
| 158 | if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) { |
| 159 | if (reg == MIO_EMM_SAMPLE()) |
| 160 | return "MIO_EMM_SAMPLE"; |
| 161 | } |
| 162 | if (reg == MIO_EMM_STS_MASK()) |
| 163 | return "MIO_EMM_STS_MASK"; |
| 164 | if (reg == MIO_EMM_RCA()) |
| 165 | return "MIO_EMM_RCA"; |
| 166 | if (reg == MIO_EMM_BUF_IDX()) |
| 167 | return "MIO_EMM_BUF_IDX"; |
| 168 | if (reg == MIO_EMM_BUF_DAT()) |
| 169 | return "MIO_EMM_BUF_DAT"; |
| 170 | if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) { |
| 171 | if (reg == MIO_EMM_CALB()) |
| 172 | return "MIO_EMM_CALB"; |
| 173 | if (reg == MIO_EMM_TAP()) |
| 174 | return "MIO_EMM_TAP"; |
| 175 | if (reg == MIO_EMM_TIMING()) |
| 176 | return "MIO_EMM_TIMING"; |
| 177 | if (reg == MIO_EMM_DEBUG()) |
| 178 | return "MIO_EMM_DEBUG"; |
| 179 | } |
| 180 | |
| 181 | return "UNKNOWN"; |
| 182 | } |
| 183 | #endif |
| 184 | |
| 185 | static void octeontx_print_rsp_sts(struct mmc *mmc) |
| 186 | { |
| 187 | #ifdef DEBUG |
| 188 | union mio_emm_rsp_sts emm_rsp_sts; |
| 189 | const struct octeontx_mmc_host *host = mmc_to_host(mmc); |
| 190 | static const char * const ctype_xor_str[] = { |
| 191 | "No data", |
| 192 | "Read data into Dbuf", |
| 193 | "Write data from Dbuf", |
| 194 | "Reserved" |
| 195 | }; |
| 196 | |
| 197 | static const char * const rtype_xor_str[] = { |
| 198 | "No response", |
| 199 | "R1, 48 bits", |
| 200 | "R2, 136 bits", |
| 201 | "R3, 48 bits", |
| 202 | "R4, 48 bits", |
| 203 | "R5, 48 bits", |
| 204 | "Reserved 6", |
| 205 | "Reserved 7" |
| 206 | }; |
| 207 | |
| 208 | emm_rsp_sts.u = readq(host->base_addr + MIO_EMM_RSP_STS()); |
| 209 | printf("\nMIO_EMM_RSP_STS: 0x%016llx\n", emm_rsp_sts.u); |
| 210 | printf(" 60-61: bus_id: %u\n", emm_rsp_sts.s.bus_id); |
| 211 | printf(" 59: cmd_val: %s\n", |
| 212 | emm_rsp_sts.s.cmd_val ? "yes" : "no"); |
| 213 | printf(" 58: switch_val: %s\n", |
| 214 | emm_rsp_sts.s.switch_val ? "yes" : "no"); |
| 215 | printf(" 57: dma_val: %s\n", |
| 216 | emm_rsp_sts.s.dma_val ? "yes" : "no"); |
| 217 | printf(" 56: dma_pend: %s\n", |
| 218 | emm_rsp_sts.s.dma_pend ? "yes" : "no"); |
| 219 | printf(" 28: dbuf_err: %s\n", |
| 220 | emm_rsp_sts.s.dbuf_err ? "yes" : "no"); |
| 221 | printf(" 23: dbuf: %u\n", emm_rsp_sts.s.dbuf); |
| 222 | printf(" 22: blk_timeout: %s\n", |
| 223 | emm_rsp_sts.s.blk_timeout ? "yes" : "no"); |
| 224 | printf(" 21: blk_crc_err: %s\n", |
| 225 | emm_rsp_sts.s.blk_crc_err ? "yes" : "no"); |
| 226 | printf(" 20: rsp_busybit: %s\n", |
| 227 | emm_rsp_sts.s.rsp_busybit ? "yes" : "no"); |
| 228 | printf(" 19: stp_timeout: %s\n", |
| 229 | emm_rsp_sts.s.stp_timeout ? "yes" : "no"); |
| 230 | printf(" 18: stp_crc_err: %s\n", |
| 231 | emm_rsp_sts.s.stp_crc_err ? "yes" : "no"); |
| 232 | printf(" 17: stp_bad_sts: %s\n", |
| 233 | emm_rsp_sts.s.stp_bad_sts ? "yes" : "no"); |
| 234 | printf(" 16: stp_val: %s\n", |
| 235 | emm_rsp_sts.s.stp_val ? "yes" : "no"); |
| 236 | printf(" 15: rsp_timeout: %s\n", |
| 237 | emm_rsp_sts.s.rsp_timeout ? "yes" : "no"); |
| 238 | printf(" 14: rsp_crc_err: %s\n", |
| 239 | emm_rsp_sts.s.rsp_crc_err ? "yes" : "no"); |
| 240 | printf(" 13: rsp_bad_sts: %s\n", |
| 241 | emm_rsp_sts.s.rsp_bad_sts ? "yes" : "no"); |
| 242 | printf(" 12: rsp_val: %s\n", |
| 243 | emm_rsp_sts.s.rsp_val ? "yes" : "no"); |
| 244 | printf(" 9-11: rsp_type: %s\n", |
| 245 | rtype_xor_str[emm_rsp_sts.s.rsp_type]); |
| 246 | printf(" 7-8: cmd_type: %s\n", |
| 247 | ctype_xor_str[emm_rsp_sts.s.cmd_type]); |
| 248 | printf(" 1-6: cmd_idx: %u\n", |
| 249 | emm_rsp_sts.s.cmd_idx); |
| 250 | printf(" 0: cmd_done: %s\n", |
| 251 | emm_rsp_sts.s.cmd_done ? "yes" : "no"); |
| 252 | #endif |
| 253 | } |
| 254 | |
| 255 | static inline u64 read_csr(struct mmc *mmc, u64 reg) |
| 256 | { |
| 257 | const struct octeontx_mmc_host *host = mmc_to_host(mmc); |
| 258 | u64 value = readq(host->base_addr + reg); |
| 259 | #ifdef DEBUG_CSR |
| 260 | printf(" %s: %s(0x%p) => 0x%llx\n", __func__, |
| 261 | mmc_reg_str(reg), host->base_addr + reg, |
| 262 | value); |
| 263 | #endif |
| 264 | return value; |
| 265 | } |
| 266 | |
| 267 | /** |
| 268 | * Writes to a CSR register |
| 269 | * |
| 270 | * @param[in] mmc pointer to mmc data structure |
| 271 | * @param reg register offset |
| 272 | * @param value value to write to register |
| 273 | */ |
| 274 | static inline void write_csr(struct mmc *mmc, u64 reg, u64 value) |
| 275 | { |
| 276 | const struct octeontx_mmc_host *host = mmc_to_host(mmc); |
| 277 | void *addr = host->base_addr + reg; |
| 278 | |
| 279 | #ifdef DEBUG_CSR |
| 280 | printf(" %s: %s(0x%p) <= 0x%llx\n", __func__, mmc_reg_str(reg), |
| 281 | addr, value); |
| 282 | #endif |
| 283 | writeq(value, addr); |
| 284 | } |
| 285 | |
| 286 | #ifdef DEBUG |
| 287 | static void mmc_print_status(u32 status) |
| 288 | { |
| 289 | #ifdef DEBUG_STATUS |
| 290 | static const char * const state[] = { |
| 291 | "Idle", /* 0 */ |
| 292 | "Ready", /* 1 */ |
| 293 | "Ident", /* 2 */ |
| 294 | "Standby", /* 3 */ |
| 295 | "Tran", /* 4 */ |
| 296 | "Data", /* 5 */ |
| 297 | "Receive", /* 6 */ |
| 298 | "Program", /* 7 */ |
| 299 | "Dis", /* 8 */ |
| 300 | "Btst", /* 9 */ |
| 301 | "Sleep", /* 10 */ |
| 302 | "reserved", /* 11 */ |
| 303 | "reserved", /* 12 */ |
| 304 | "reserved", /* 13 */ |
| 305 | "reserved", /* 14 */ |
| 306 | "reserved" /* 15 */ }; |
| 307 | if (status & R1_APP_CMD) |
| 308 | puts("MMC ACMD\n"); |
| 309 | if (status & R1_SWITCH_ERROR) |
| 310 | puts("MMC switch error\n"); |
| 311 | if (status & R1_READY_FOR_DATA) |
| 312 | puts("MMC ready for data\n"); |
| 313 | printf("MMC %s state\n", state[R1_CURRENT_STATE(status)]); |
| 314 | if (status & R1_ERASE_RESET) |
| 315 | puts("MMC erase reset\n"); |
| 316 | if (status & R1_WP_ERASE_SKIP) |
| 317 | puts("MMC partial erase due to write protected blocks\n"); |
| 318 | if (status & R1_CID_CSD_OVERWRITE) |
| 319 | puts("MMC CID/CSD overwrite error\n"); |
| 320 | if (status & R1_ERROR) |
| 321 | puts("MMC undefined device error\n"); |
| 322 | if (status & R1_CC_ERROR) |
| 323 | puts("MMC device error\n"); |
| 324 | if (status & R1_CARD_ECC_FAILED) |
| 325 | puts("MMC internal ECC failed to correct data\n"); |
| 326 | if (status & R1_ILLEGAL_COMMAND) |
| 327 | puts("MMC illegal command\n"); |
| 328 | if (status & R1_COM_CRC_ERROR) |
| 329 | puts("MMC CRC of previous command failed\n"); |
| 330 | if (status & R1_LOCK_UNLOCK_FAILED) |
| 331 | puts("MMC sequence or password error in lock/unlock device command\n"); |
| 332 | if (status & R1_CARD_IS_LOCKED) |
| 333 | puts("MMC device locked by host\n"); |
| 334 | if (status & R1_WP_VIOLATION) |
| 335 | puts("MMC attempt to program write protected block\n"); |
| 336 | if (status & R1_ERASE_PARAM) |
| 337 | puts("MMC invalid selection of erase groups for erase\n"); |
| 338 | if (status & R1_ERASE_SEQ_ERROR) |
| 339 | puts("MMC error in sequence of erase commands\n"); |
| 340 | if (status & R1_BLOCK_LEN_ERROR) |
| 341 | puts("MMC block length error\n"); |
| 342 | if (status & R1_ADDRESS_ERROR) |
| 343 | puts("MMC address misalign error\n"); |
| 344 | if (status & R1_OUT_OF_RANGE) |
| 345 | puts("MMC address out of range\n"); |
| 346 | #endif |
| 347 | } |
| 348 | #endif |
| 349 | |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 350 | #if !defined(CONFIG_ARCH_OCTEON) |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 351 | /** |
| 352 | * Print out all of the register values where mmc is optional |
| 353 | * |
| 354 | * @param mmc MMC device (can be NULL) |
| 355 | * @param host Pointer to host data structure (can be NULL if mmc is !NULL) |
| 356 | */ |
| 357 | static void octeontx_mmc_print_registers2(struct mmc *mmc, |
| 358 | struct octeontx_mmc_host *host) |
| 359 | { |
| 360 | struct octeontx_mmc_slot *slot = mmc ? mmc->priv : NULL; |
| 361 | union mio_emm_dma_cfg emm_dma_cfg; |
| 362 | union mio_emm_dma_adr emm_dma_adr; |
| 363 | union mio_emm_dma_int emm_dma_int; |
| 364 | union mio_emm_cfg emm_cfg; |
| 365 | union mio_emm_modex emm_mode; |
| 366 | union mio_emm_switch emm_switch; |
| 367 | union mio_emm_dma emm_dma; |
| 368 | union mio_emm_cmd emm_cmd; |
| 369 | union mio_emm_rsp_sts emm_rsp_sts; |
| 370 | union mio_emm_rsp_lo emm_rsp_lo; |
| 371 | union mio_emm_rsp_hi emm_rsp_hi; |
| 372 | union mio_emm_int emm_int; |
| 373 | union mio_emm_wdog emm_wdog; |
| 374 | union mio_emm_sample emm_sample; |
| 375 | union mio_emm_calb emm_calb; |
| 376 | union mio_emm_tap emm_tap; |
| 377 | union mio_emm_timing emm_timing; |
| 378 | union mio_emm_io_ctl io_ctl; |
| 379 | union mio_emm_debug emm_debug; |
| 380 | union mio_emm_sts_mask emm_sts_mask; |
| 381 | union mio_emm_rca emm_rca; |
| 382 | int bus; |
| 383 | |
| 384 | static const char * const bus_width_str[] = { |
| 385 | "1-bit data bus (power on)", |
| 386 | "4-bit data bus", |
| 387 | "8-bit data bus", |
| 388 | "reserved (3)", |
| 389 | "reserved (4)", |
| 390 | "4-bit data bus (dual data rate)", |
| 391 | "8-bit data bus (dual data rate)", |
| 392 | "reserved (7)", |
| 393 | "reserved (8)", |
| 394 | "invalid (9)", |
| 395 | "invalid (10)", |
| 396 | "invalid (11)", |
| 397 | "invalid (12)", |
| 398 | "invalid (13)", |
| 399 | "invalid (14)", |
| 400 | "invalid (15)", |
| 401 | }; |
| 402 | static const char * const ctype_xor_str[] = { |
| 403 | "No data", |
| 404 | "Read data into Dbuf", |
| 405 | "Write data from Dbuf", |
| 406 | "Reserved" |
| 407 | }; |
| 408 | |
| 409 | static const char * const rtype_xor_str[] = { |
| 410 | "No response", |
| 411 | "R1, 48 bits", |
| 412 | "R2, 136 bits", |
| 413 | "R3, 48 bits", |
| 414 | "R4, 48 bits", |
| 415 | "R5, 48 bits", |
| 416 | "Reserved 6", |
| 417 | "Reserved 7" |
| 418 | }; |
| 419 | |
| 420 | if (!host && mmc) |
| 421 | host = mmc_to_host(mmc); |
| 422 | |
| 423 | if (mmc) |
| 424 | printf("%s: bus id: %u\n", __func__, slot->bus_id); |
| 425 | emm_dma_cfg.u = readq(host->base_addr + MIO_EMM_DMA_CFG()); |
| 426 | printf("MIO_EMM_DMA_CFG: 0x%016llx\n", |
| 427 | emm_dma_cfg.u); |
| 428 | printf(" 63: en: %s\n", |
| 429 | emm_dma_cfg.s.en ? "enabled" : "disabled"); |
| 430 | printf(" 62: rw: %s\n", |
| 431 | emm_dma_cfg.s.rw ? "write" : "read"); |
| 432 | printf(" 61: clr: %s\n", |
| 433 | emm_dma_cfg.s.clr ? "clear" : "not clear"); |
| 434 | printf(" 59: swap32: %s\n", |
| 435 | emm_dma_cfg.s.swap32 ? "yes" : "no"); |
| 436 | printf(" 58: swap16: %s\n", |
| 437 | emm_dma_cfg.s.swap16 ? "yes" : "no"); |
| 438 | printf(" 57: swap8: %s\n", |
| 439 | emm_dma_cfg.s.swap8 ? "yes" : "no"); |
| 440 | printf(" 56: endian: %s\n", |
| 441 | emm_dma_cfg.s.endian ? "little" : "big"); |
| 442 | printf(" 36-55: size: %u\n", |
| 443 | emm_dma_cfg.s.size); |
| 444 | |
| 445 | emm_dma_adr.u = readq(host->base_addr + MIO_EMM_DMA_ADR()); |
| 446 | printf("MIO_EMM_DMA_ADR: 0x%016llx\n", emm_dma_adr.u); |
| 447 | printf(" 0-49: adr: 0x%llx\n", |
| 448 | (u64)emm_dma_adr.s.adr); |
| 449 | |
| 450 | emm_dma_int.u = readq(host->base_addr + MIO_EMM_DMA_INT()); |
| 451 | printf("\nMIO_EMM_DMA_INT: 0x%016llx\n", |
| 452 | emm_dma_int.u); |
| 453 | printf(" 1: FIFO: %s\n", |
| 454 | emm_dma_int.s.fifo ? "yes" : "no"); |
| 455 | printf(" 0: Done: %s\n", |
| 456 | emm_dma_int.s.done ? "yes" : "no"); |
| 457 | emm_cfg.u = readq(host->base_addr + MIO_EMM_CFG()); |
| 458 | |
| 459 | printf("\nMIO_EMM_CFG: 0x%016llx\n", |
| 460 | emm_cfg.u); |
| 461 | printf(" 3: bus_ena3: %s\n", |
| 462 | emm_cfg.s.bus_ena & 0x08 ? "yes" : "no"); |
| 463 | printf(" 2: bus_ena2: %s\n", |
| 464 | emm_cfg.s.bus_ena & 0x04 ? "yes" : "no"); |
| 465 | printf(" 1: bus_ena1: %s\n", |
| 466 | emm_cfg.s.bus_ena & 0x02 ? "yes" : "no"); |
| 467 | printf(" 0: bus_ena0: %s\n", |
| 468 | emm_cfg.s.bus_ena & 0x01 ? "yes" : "no"); |
| 469 | for (bus = 0; bus < 4; bus++) { |
| 470 | emm_mode.u = readq(host->base_addr + MIO_EMM_MODEX(bus)); |
| 471 | printf("\nMIO_EMM_MODE%u: 0x%016llx\n", |
| 472 | bus, emm_mode.u); |
| 473 | if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) { |
| 474 | printf(" 50: hs400_timing: %s\n", |
| 475 | emm_mode.s.hs400_timing ? "yes" : "no"); |
| 476 | printf(" 49: hs200_timing: %s\n", |
| 477 | emm_mode.s.hs200_timing ? "yes" : "no"); |
| 478 | } |
| 479 | printf(" 48: hs_timing: %s\n", |
| 480 | emm_mode.s.hs_timing ? "yes" : "no"); |
| 481 | printf(" 40-42: bus_width: %s\n", |
| 482 | bus_width_str[emm_mode.s.bus_width]); |
| 483 | printf(" 32-35: power_class %u\n", |
| 484 | emm_mode.s.power_class); |
| 485 | printf(" 16-31: clk_hi: %u\n", |
| 486 | emm_mode.s.clk_hi); |
| 487 | printf(" 0-15: clk_lo: %u\n", |
| 488 | emm_mode.s.clk_lo); |
| 489 | } |
| 490 | |
| 491 | emm_switch.u = readq(host->base_addr + MIO_EMM_SWITCH()); |
| 492 | printf("\nMIO_EMM_SWITCH: 0x%016llx\n", emm_switch.u); |
| 493 | printf(" 60-61: bus_id: %u\n", emm_switch.s.bus_id); |
| 494 | printf(" 59: switch_exe: %s\n", |
| 495 | emm_switch.s.switch_exe ? "yes" : "no"); |
| 496 | printf(" 58: switch_err0: %s\n", |
| 497 | emm_switch.s.switch_err0 ? "yes" : "no"); |
| 498 | printf(" 57: switch_err1: %s\n", |
| 499 | emm_switch.s.switch_err1 ? "yes" : "no"); |
| 500 | printf(" 56: switch_err2: %s\n", |
| 501 | emm_switch.s.switch_err2 ? "yes" : "no"); |
| 502 | printf(" 48: hs_timing: %s\n", |
| 503 | emm_switch.s.hs_timing ? "yes" : "no"); |
| 504 | printf(" 42-40: bus_width: %s\n", |
| 505 | bus_width_str[emm_switch.s.bus_width]); |
| 506 | printf(" 32-35: power_class: %u\n", |
| 507 | emm_switch.s.power_class); |
| 508 | printf(" 16-31: clk_hi: %u\n", |
| 509 | emm_switch.s.clk_hi); |
| 510 | printf(" 0-15: clk_lo: %u\n", emm_switch.s.clk_lo); |
| 511 | |
| 512 | emm_dma.u = readq(host->base_addr + MIO_EMM_DMA()); |
| 513 | printf("\nMIO_EMM_DMA: 0x%016llx\n", emm_dma.u); |
| 514 | printf(" 60-61: bus_id: %u\n", emm_dma.s.bus_id); |
| 515 | printf(" 59: dma_val: %s\n", |
| 516 | emm_dma.s.dma_val ? "yes" : "no"); |
| 517 | printf(" 58: sector: %s mode\n", |
| 518 | emm_dma.s.sector ? "sector" : "byte"); |
| 519 | printf(" 57: dat_null: %s\n", |
| 520 | emm_dma.s.dat_null ? "yes" : "no"); |
| 521 | printf(" 51-56: thres: %u\n", emm_dma.s.thres); |
| 522 | printf(" 50: rel_wr: %s\n", |
| 523 | emm_dma.s.rel_wr ? "yes" : "no"); |
| 524 | printf(" 49: rw: %s\n", |
| 525 | emm_dma.s.rw ? "write" : "read"); |
| 526 | printf(" 48: multi: %s\n", |
| 527 | emm_dma.s.multi ? "yes" : "no"); |
| 528 | printf(" 32-47: block_cnt: %u\n", |
| 529 | emm_dma.s.block_cnt); |
| 530 | printf(" 0-31: card_addr: 0x%x\n", |
| 531 | emm_dma.s.card_addr); |
| 532 | |
| 533 | emm_cmd.u = readq(host->base_addr + MIO_EMM_CMD()); |
| 534 | printf("\nMIO_EMM_CMD: 0x%016llx\n", emm_cmd.u); |
| 535 | printf("\n 62: skip_busy: %s\n", |
| 536 | emm_cmd.s.skip_busy ? "yes" : "no"); |
| 537 | printf(" 60-61: bus_id: %u\n", emm_cmd.s.bus_id); |
| 538 | printf(" 59: cmd_val: %s\n", |
| 539 | emm_cmd.s.cmd_val ? "yes" : "no"); |
| 540 | printf(" 55: dbuf: %u\n", emm_cmd.s.dbuf); |
| 541 | printf(" 49-54: offset: %u\n", emm_cmd.s.offset); |
| 542 | printf(" 41-42: ctype_xor: %s\n", |
| 543 | ctype_xor_str[emm_cmd.s.ctype_xor]); |
| 544 | printf(" 38-40: rtype_xor: %s\n", |
| 545 | rtype_xor_str[emm_cmd.s.rtype_xor]); |
| 546 | printf(" 32-37: cmd_idx: %u\n", emm_cmd.s.cmd_idx); |
| 547 | printf(" 0-31: arg: 0x%x\n", emm_cmd.s.arg); |
| 548 | |
| 549 | emm_rsp_sts.u = readq(host->base_addr + MIO_EMM_RSP_STS()); |
| 550 | printf("\nMIO_EMM_RSP_STS: 0x%016llx\n", emm_rsp_sts.u); |
| 551 | printf(" 60-61: bus_id: %u\n", emm_rsp_sts.s.bus_id); |
| 552 | printf(" 59: cmd_val: %s\n", |
| 553 | emm_rsp_sts.s.cmd_val ? "yes" : "no"); |
| 554 | printf(" 58: switch_val: %s\n", |
| 555 | emm_rsp_sts.s.switch_val ? "yes" : "no"); |
| 556 | printf(" 57: dma_val: %s\n", |
| 557 | emm_rsp_sts.s.dma_val ? "yes" : "no"); |
| 558 | printf(" 56: dma_pend: %s\n", |
| 559 | emm_rsp_sts.s.dma_pend ? "yes" : "no"); |
| 560 | printf(" 28: dbuf_err: %s\n", |
| 561 | emm_rsp_sts.s.dbuf_err ? "yes" : "no"); |
| 562 | printf(" 23: dbuf: %u\n", emm_rsp_sts.s.dbuf); |
| 563 | printf(" 22: blk_timeout: %s\n", |
| 564 | emm_rsp_sts.s.blk_timeout ? "yes" : "no"); |
| 565 | printf(" 21: blk_crc_err: %s\n", |
| 566 | emm_rsp_sts.s.blk_crc_err ? "yes" : "no"); |
| 567 | printf(" 20: rsp_busybit: %s\n", |
| 568 | emm_rsp_sts.s.rsp_busybit ? "yes" : "no"); |
| 569 | printf(" 19: stp_timeout: %s\n", |
| 570 | emm_rsp_sts.s.stp_timeout ? "yes" : "no"); |
| 571 | printf(" 18: stp_crc_err: %s\n", |
| 572 | emm_rsp_sts.s.stp_crc_err ? "yes" : "no"); |
| 573 | printf(" 17: stp_bad_sts: %s\n", |
| 574 | emm_rsp_sts.s.stp_bad_sts ? "yes" : "no"); |
| 575 | printf(" 16: stp_val: %s\n", |
| 576 | emm_rsp_sts.s.stp_val ? "yes" : "no"); |
| 577 | printf(" 15: rsp_timeout: %s\n", |
| 578 | emm_rsp_sts.s.rsp_timeout ? "yes" : "no"); |
| 579 | printf(" 14: rsp_crc_err: %s\n", |
| 580 | emm_rsp_sts.s.rsp_crc_err ? "yes" : "no"); |
| 581 | printf(" 13: rsp_bad_sts: %s\n", |
| 582 | emm_rsp_sts.s.rsp_bad_sts ? "yes" : "no"); |
| 583 | printf(" 12: rsp_val: %s\n", |
| 584 | emm_rsp_sts.s.rsp_val ? "yes" : "no"); |
| 585 | printf(" 9-11: rsp_type: %s\n", |
| 586 | rtype_xor_str[emm_rsp_sts.s.rsp_type]); |
| 587 | printf(" 7-8: cmd_type: %s\n", |
| 588 | ctype_xor_str[emm_rsp_sts.s.cmd_type]); |
| 589 | printf(" 1-6: cmd_idx: %u\n", |
| 590 | emm_rsp_sts.s.cmd_idx); |
| 591 | printf(" 0: cmd_done: %s\n", |
| 592 | emm_rsp_sts.s.cmd_done ? "yes" : "no"); |
| 593 | |
| 594 | emm_rsp_lo.u = readq(host->base_addr + MIO_EMM_RSP_LO()); |
| 595 | printf("\nMIO_EMM_RSP_STS_LO: 0x%016llx\n", emm_rsp_lo.u); |
| 596 | |
| 597 | emm_rsp_hi.u = readq(host->base_addr + MIO_EMM_RSP_HI()); |
| 598 | printf("\nMIO_EMM_RSP_STS_HI: 0x%016llx\n", emm_rsp_hi.u); |
| 599 | |
| 600 | emm_int.u = readq(host->base_addr + MIO_EMM_INT()); |
| 601 | printf("\nMIO_EMM_INT: 0x%016llx\n", emm_int.u); |
| 602 | printf(" 6: switch_err: %s\n", |
| 603 | emm_int.s.switch_err ? "yes" : "no"); |
| 604 | printf(" 5: switch_done: %s\n", |
| 605 | emm_int.s.switch_done ? "yes" : "no"); |
| 606 | printf(" 4: dma_err: %s\n", |
| 607 | emm_int.s.dma_err ? "yes" : "no"); |
| 608 | printf(" 3: cmd_err: %s\n", |
| 609 | emm_int.s.cmd_err ? "yes" : "no"); |
| 610 | printf(" 2: dma_done: %s\n", |
| 611 | emm_int.s.dma_done ? "yes" : "no"); |
| 612 | printf(" 1: cmd_done: %s\n", |
| 613 | emm_int.s.cmd_done ? "yes" : "no"); |
| 614 | printf(" 0: buf_done: %s\n", |
| 615 | emm_int.s.buf_done ? "yes" : "no"); |
| 616 | |
| 617 | emm_wdog.u = readq(host->base_addr + MIO_EMM_WDOG()); |
| 618 | printf("\nMIO_EMM_WDOG: 0x%016llx (%u)\n", |
| 619 | emm_wdog.u, emm_wdog.s.clk_cnt); |
| 620 | |
| 621 | if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) { |
| 622 | emm_sample.u = readq(host->base_addr + MIO_EMM_SAMPLE()); |
| 623 | printf("\nMIO_EMM_SAMPLE: 0x%016llx\n", |
| 624 | emm_sample.u); |
| 625 | printf(" 16-25: cmd_cnt: %u\n", |
| 626 | emm_sample.s.cmd_cnt); |
| 627 | printf(" 0-9: dat_cnt: %u\n", |
| 628 | emm_sample.s.dat_cnt); |
| 629 | } |
| 630 | |
| 631 | emm_sts_mask.u = readq(host->base_addr + MIO_EMM_STS_MASK()); |
| 632 | printf("\nMIO_EMM_STS_MASK: 0x%016llx\n", emm_sts_mask.u); |
| 633 | |
| 634 | emm_rca.u = readq(host->base_addr + MIO_EMM_RCA()); |
| 635 | printf("\nMIO_EMM_RCA: 0x%016llx\n", emm_rca.u); |
| 636 | printf(" 0-15: card_rca: 0x%04x\n", |
| 637 | emm_rca.s.card_rca); |
| 638 | if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) { |
| 639 | emm_calb.u = readq(host->base_addr + MIO_EMM_CALB()); |
| 640 | printf("\nMIO_EMM_CALB: 0x%016llx\n", |
| 641 | emm_calb.u); |
| 642 | printf(" 0: start: %u\n", |
| 643 | emm_calb.s.start); |
| 644 | emm_tap.u = readq(host->base_addr + MIO_EMM_TAP()); |
| 645 | printf("\nMIO_EMM_TAP: 0x%016llx\n", |
| 646 | emm_tap.u); |
| 647 | printf(" 7-0: delay: %u\n", emm_tap.s.delay); |
| 648 | emm_timing.u = readq(host->base_addr + MIO_EMM_TIMING()); |
| 649 | printf("\nMIO_EMM_TIMING: 0x%016llx\n", |
| 650 | emm_timing.u); |
| 651 | printf(" 53-48: cmd_in_tap: %u\n", |
| 652 | emm_timing.s.cmd_in_tap); |
| 653 | printf(" 37-32: cmd_out_tap: %u\n", |
| 654 | emm_timing.s.cmd_out_tap); |
| 655 | printf(" 21-16: data_in_tap: %u\n", |
| 656 | emm_timing.s.data_in_tap); |
| 657 | printf(" 5-0: data_out_tap: %u\n", |
| 658 | emm_timing.s.data_out_tap); |
| 659 | io_ctl.u = readq(host->base_addr + MIO_EMM_IO_CTL()); |
| 660 | printf("\nMIO_IO_CTL: 0x%016llx\n", io_ctl.u); |
| 661 | printf(" 3-2: drive: %u (%u mA)\n", |
| 662 | io_ctl.s.drive, 2 << io_ctl.s.drive); |
| 663 | printf(" 0: slew: %u %s\n", io_ctl.s.slew, |
| 664 | io_ctl.s.slew ? "high" : "low"); |
| 665 | emm_debug.u = readq(host->base_addr + MIO_EMM_DEBUG()); |
| 666 | printf("\nMIO_EMM_DEBUG: 0x%016llx\n", |
| 667 | emm_debug.u); |
| 668 | printf(" 21: rdsync_rst 0x%x\n", |
| 669 | emm_debug.s.rdsync_rst); |
| 670 | printf(" 20: emmc_clk_disable 0x%x\n", |
| 671 | emm_debug.s.emmc_clk_disable); |
| 672 | printf(" 19-16: dma_sm: 0x%x\n", |
| 673 | emm_debug.s.dma_sm); |
| 674 | printf(" 15-12: data_sm: 0x%x\n", |
| 675 | emm_debug.s.data_sm); |
| 676 | printf(" 11-8: cmd_sm: 0x%x\n", |
| 677 | emm_debug.s.cmd_sm); |
| 678 | printf(" 0: clk_on: 0x%x\n", |
| 679 | emm_debug.s.clk_on); |
| 680 | } |
| 681 | |
| 682 | puts("\n"); |
| 683 | } |
| 684 | |
| 685 | /** |
| 686 | * Print out all of the register values |
| 687 | * |
| 688 | * @param mmc MMC device |
| 689 | */ |
| 690 | static void octeontx_mmc_print_registers(struct mmc *mmc) |
| 691 | { |
| 692 | #ifdef DEBUG_REGISTERS |
| 693 | const int print = 1; |
| 694 | #else |
| 695 | const int print = 0; |
| 696 | #endif |
| 697 | if (print) |
| 698 | octeontx_mmc_print_registers2(mmc, mmc_to_host(mmc)); |
| 699 | } |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 700 | #else |
| 701 | static void octeontx_mmc_print_registers(struct mmc *mmc) |
| 702 | { |
| 703 | return; |
| 704 | } |
| 705 | #endif |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 706 | |
| 707 | static const struct octeontx_sd_mods octeontx_cr_types[] = { |
| 708 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD0 */ |
| 709 | { {0, 3}, {0, 3}, {0, 0} }, /* CMD1 */ |
| 710 | { {0, 2}, {0, 2}, {0, 0} }, /* CMD2 */ |
| 711 | { {0, 1}, {0, 3}, {0, 0} }, /* CMD3 SD_CMD_SEND_RELATIVE_ADDR 0, 2 */ |
| 712 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD4 */ |
| 713 | { {0, 1}, {0, 1}, {0, 0} }, /* CMD5 */ |
| 714 | { {0, 1}, {1, 1}, {0, 1} }, /* |
| 715 | * CMD6 SD_CMD_SWITCH_FUNC 1,0 |
| 716 | * (ACMD) SD_APP_SET_BUS_WIDTH |
| 717 | */ |
| 718 | { {0, 1}, {0, 1}, {0, 0} }, /* CMD7 */ |
| 719 | { {1, 1}, {0, 3}, {0, 0} }, /* CMD8 SD_CMD_SEND_IF_COND 1,2 */ |
| 720 | { {0, 2}, {0, 2}, {0, 0} }, /* CMD9 */ |
| 721 | { {0, 2}, {0, 2}, {0, 0} }, /* CMD10 */ |
| 722 | { {1, 1}, {0, 1}, {1, 1} }, /* CMD11 SD_CMD_SWITCH_UHS18V 1,0 */ |
| 723 | { {0, 1}, {0, 1}, {0, 0} }, /* CMD12 */ |
| 724 | { {0, 1}, {0, 1}, {1, 3} }, /* CMD13 (ACMD)) SD_CMD_APP_SD_STATUS 1,2 */ |
| 725 | { {1, 1}, {1, 1}, {0, 0} }, /* CMD14 */ |
| 726 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD15 */ |
| 727 | { {0, 1}, {0, 1}, {0, 0} }, /* CMD16 */ |
| 728 | { {1, 1}, {1, 1}, {0, 0} }, /* CMD17 */ |
| 729 | { {1, 1}, {1, 1}, {0, 0} }, /* CMD18 */ |
| 730 | { {3, 1}, {3, 1}, {0, 0} }, /* CMD19 */ |
| 731 | { {2, 1}, {0, 0}, {0, 0} }, /* CMD20 */ /* SD 2,0 */ |
| 732 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD21 */ |
| 733 | { {0, 0}, {0, 0}, {1, 1} }, /* CMD22 (ACMD) SD_APP_SEND_NUM_WR_BLKS 1,0 */ |
| 734 | { {0, 1}, {0, 1}, {0, 1} }, /* CMD23 */ /* SD ACMD 1,0 */ |
| 735 | { {2, 1}, {2, 1}, {2, 1} }, /* CMD24 */ |
| 736 | { {2, 1}, {2, 1}, {2, 1} }, /* CMD25 */ |
| 737 | { {2, 1}, {2, 1}, {2, 1} }, /* CMD26 */ |
| 738 | { {2, 1}, {2, 1}, {2, 1} }, /* CMD27 */ |
| 739 | { {0, 1}, {0, 1}, {0, 1} }, /* CMD28 */ |
| 740 | { {0, 1}, {0, 1}, {0, 1} }, /* CMD29 */ |
| 741 | { {1, 1}, {1, 1}, {1, 1} }, /* CMD30 */ |
| 742 | { {1, 1}, {1, 1}, {1, 1} }, /* CMD31 */ |
| 743 | { {0, 0}, {0, 1}, {0, 0} }, /* CMD32 SD_CMD_ERASE_WR_BLK_START 0,1 */ |
| 744 | { {0, 0}, {0, 1}, {0, 0} }, /* CMD33 SD_CMD_ERASE_WR_BLK_END 0,1 */ |
| 745 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD34 */ |
| 746 | { {0, 1}, {0, 1}, {0, 1} }, /* CMD35 */ |
| 747 | { {0, 1}, {0, 1}, {0, 1} }, /* CMD36 */ |
| 748 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD37 */ |
| 749 | { {0, 1}, {0, 1}, {0, 1} }, /* CMD38 */ |
| 750 | { {0, 4}, {0, 4}, {0, 4} }, /* CMD39 */ |
| 751 | { {0, 5}, {0, 5}, {0, 5} }, /* CMD40 */ |
| 752 | { {0, 0}, {0, 0}, {0, 3} }, /* CMD41 (ACMD) SD_CMD_APP_SEND_OP_COND 0,3 */ |
| 753 | { {2, 1}, {2, 1}, {2, 1} }, /* CMD42 */ |
| 754 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD43 */ |
| 755 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD44 */ |
| 756 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD45 */ |
| 757 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD46 */ |
| 758 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD47 */ |
| 759 | { {0, 0}, {1, 0}, {0, 0} }, /* CMD48 SD_CMD_READ_EXTR_SINGLE */ |
| 760 | { {0, 0}, {2, 0}, {0, 0} }, /* CMD49 SD_CMD_WRITE_EXTR_SINGLE */ |
| 761 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD50 */ |
| 762 | { {0, 0}, {0, 0}, {1, 1} }, /* CMD51 (ACMD) SD_CMD_APP_SEND_SCR 1,1 */ |
| 763 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD52 */ |
| 764 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD53 */ |
| 765 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD54 */ |
| 766 | { {0, 1}, {0, 1}, {0, 1} }, /* CMD55 */ |
| 767 | { {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff} }, /* CMD56 */ |
| 768 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD57 */ |
| 769 | { {0, 0}, {0, 3}, {0, 3} }, /* CMD58 SD_CMD_SPI_READ_OCR 0,3 */ |
| 770 | { {0, 0}, {0, 1}, {0, 0} }, /* CMD59 SD_CMD_SPI_CRC_ON_OFF 0,1 */ |
| 771 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD60 */ |
| 772 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD61 */ |
| 773 | { {0, 0}, {0, 0}, {0, 0} }, /* CMD62 */ |
| 774 | { {0, 0}, {0, 0}, {0, 0} } /* CMD63 */ |
| 775 | }; |
| 776 | |
| 777 | /** |
| 778 | * Returns XOR values needed for SD commands and other quirks |
| 779 | * |
| 780 | * @param mmc mmc device |
| 781 | * @param cmd command information |
| 782 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 783 | * Return: octeontx_mmc_cr_mods data structure with various quirks and flags |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 784 | */ |
| 785 | static struct octeontx_mmc_cr_mods |
| 786 | octeontx_mmc_get_cr_mods(struct mmc *mmc, const struct mmc_cmd *cmd, |
| 787 | const struct mmc_data *data) |
| 788 | { |
| 789 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 790 | struct octeontx_mmc_cr_mods cr = {0, 0}; |
| 791 | const struct octeontx_sd_mods *sdm = |
| 792 | &octeontx_cr_types[cmd->cmdidx & 0x3f]; |
| 793 | u8 c = sdm->mmc.c, r = sdm->mmc.r; |
| 794 | u8 desired_ctype = 0; |
| 795 | |
| 796 | if (IS_MMC(mmc)) { |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 797 | #if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 798 | if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) { |
| 799 | if (cmd->resp_type == MMC_RSP_R1) |
| 800 | cr.rtype_xor = 1; |
| 801 | if (data && data->flags & MMC_DATA_READ) |
| 802 | cr.ctype_xor = 1; |
| 803 | } |
| 804 | #endif |
| 805 | return cr; |
| 806 | } |
| 807 | |
| 808 | if (cmd->cmdidx == 56) |
| 809 | c = (cmd->cmdarg & 1) ? 1 : 2; |
| 810 | |
| 811 | if (data) { |
| 812 | if (data->flags & MMC_DATA_READ) |
| 813 | desired_ctype = 1; |
| 814 | else if (data->flags & MMC_DATA_WRITE) |
| 815 | desired_ctype = 2; |
| 816 | } |
| 817 | |
| 818 | cr.ctype_xor = c ^ desired_ctype; |
| 819 | if (slot->is_acmd) |
| 820 | cr.rtype_xor = r ^ sdm->sdacmd.r; |
| 821 | else |
| 822 | cr.rtype_xor = r ^ sdm->sd.r; |
| 823 | |
| 824 | debug("%s(%s): mmc c: %d, mmc r: %d, desired c: %d, xor c: %d, xor r: %d\n", |
| 825 | __func__, mmc->dev->name, c, r, desired_ctype, |
| 826 | cr.ctype_xor, cr.rtype_xor); |
| 827 | return cr; |
| 828 | } |
| 829 | |
| 830 | /** |
| 831 | * Keep track of switch commands internally |
| 832 | */ |
| 833 | static void octeontx_mmc_track_switch(struct mmc *mmc, u32 cmd_arg) |
| 834 | { |
| 835 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 836 | u8 how = (cmd_arg >> 24) & 3; |
| 837 | u8 where = (u8)(cmd_arg >> 16); |
| 838 | u8 val = (u8)(cmd_arg >> 8); |
| 839 | |
| 840 | slot->want_switch = slot->cached_switch; |
| 841 | |
| 842 | if (slot->is_acmd) |
| 843 | return; |
| 844 | |
| 845 | if (how != 3) |
| 846 | return; |
| 847 | |
| 848 | switch (where) { |
| 849 | case EXT_CSD_BUS_WIDTH: |
| 850 | slot->want_switch.s.bus_width = val; |
| 851 | break; |
| 852 | case EXT_CSD_POWER_CLASS: |
| 853 | slot->want_switch.s.power_class = val; |
| 854 | break; |
| 855 | case EXT_CSD_HS_TIMING: |
| 856 | slot->want_switch.s.hs_timing = 0; |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 857 | #if !defined(CONFIG_ARCH_OCTEON) |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 858 | slot->want_switch.s.hs200_timing = 0; |
| 859 | slot->want_switch.s.hs400_timing = 0; |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 860 | #endif |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 861 | switch (val & 0xf) { |
| 862 | case 0: |
| 863 | break; |
| 864 | case 1: |
| 865 | slot->want_switch.s.hs_timing = 1; |
| 866 | break; |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 867 | #if !defined(CONFIG_ARCH_OCTEON) |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 868 | case 2: |
| 869 | if (!slot->is_asim && !slot->is_emul) |
| 870 | slot->want_switch.s.hs200_timing = 1; |
| 871 | break; |
| 872 | case 3: |
| 873 | if (!slot->is_asim && !slot->is_emul) |
| 874 | slot->want_switch.s.hs400_timing = 1; |
| 875 | break; |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 876 | #endif |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 877 | default: |
| 878 | pr_err("%s(%s): Unsupported timing mode 0x%x\n", |
| 879 | __func__, mmc->dev->name, val & 0xf); |
| 880 | break; |
| 881 | } |
| 882 | break; |
| 883 | default: |
| 884 | break; |
| 885 | } |
| 886 | } |
| 887 | |
| 888 | static int octeontx_mmc_print_rsp_errors(struct mmc *mmc, |
| 889 | union mio_emm_rsp_sts rsp_sts) |
| 890 | { |
| 891 | bool err = false; |
| 892 | const char *name = mmc->dev->name; |
| 893 | |
| 894 | if (rsp_sts.s.acc_timeout) { |
| 895 | pr_warn("%s(%s): acc_timeout\n", __func__, name); |
| 896 | err = true; |
| 897 | } |
| 898 | if (rsp_sts.s.dbuf_err) { |
| 899 | pr_warn("%s(%s): dbuf_err\n", __func__, name); |
| 900 | err = true; |
| 901 | } |
| 902 | if (rsp_sts.s.blk_timeout) { |
| 903 | pr_warn("%s(%s): blk_timeout\n", __func__, name); |
| 904 | err = true; |
| 905 | } |
| 906 | if (rsp_sts.s.blk_crc_err) { |
| 907 | pr_warn("%s(%s): blk_crc_err\n", __func__, name); |
| 908 | err = true; |
| 909 | } |
| 910 | if (rsp_sts.s.stp_timeout) { |
| 911 | pr_warn("%s(%s): stp_timeout\n", __func__, name); |
| 912 | err = true; |
| 913 | } |
| 914 | if (rsp_sts.s.stp_crc_err) { |
| 915 | pr_warn("%s(%s): stp_crc_err\n", __func__, name); |
| 916 | err = true; |
| 917 | } |
| 918 | if (rsp_sts.s.stp_bad_sts) { |
| 919 | pr_warn("%s(%s): stp_bad_sts\n", __func__, name); |
| 920 | err = true; |
| 921 | } |
| 922 | if (err) |
| 923 | pr_warn(" rsp_sts: 0x%llx\n", rsp_sts.u); |
| 924 | |
| 925 | return err ? -1 : 0; |
| 926 | } |
| 927 | |
| 928 | /** |
| 929 | * Starts a DMA operation for block read/write |
| 930 | * |
| 931 | * @param mmc mmc device |
| 932 | * @param write true if write operation |
| 933 | * @param clear true to clear DMA operation |
| 934 | * @param adr source or destination DMA address |
| 935 | * @param size size in blocks |
| 936 | * @param timeout timeout in ms |
| 937 | */ |
| 938 | static void octeontx_mmc_start_dma(struct mmc *mmc, bool write, |
| 939 | bool clear, u32 block, dma_addr_t adr, |
| 940 | u32 size, int timeout) |
| 941 | { |
| 942 | const struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 943 | union mio_emm_dma_cfg emm_dma_cfg; |
| 944 | union mio_emm_dma_adr emm_dma_adr; |
| 945 | union mio_emm_dma emm_dma; |
| 946 | |
| 947 | /* Clear any interrupts */ |
| 948 | write_csr(mmc, MIO_EMM_DMA_INT(), |
| 949 | read_csr(mmc, MIO_EMM_DMA_INT())); |
| 950 | |
| 951 | emm_dma_cfg.u = 0; |
| 952 | emm_dma_cfg.s.en = 1; |
| 953 | emm_dma_cfg.s.rw = !!write; |
| 954 | emm_dma_cfg.s.clr = !!clear; |
| 955 | emm_dma_cfg.s.size = ((u64)(size * mmc->read_bl_len) / 8) - 1; |
| 956 | #if __BYTE_ORDER != __BIG_ENDIAN |
| 957 | emm_dma_cfg.s.endian = 1; |
| 958 | #endif |
| 959 | emm_dma_adr.u = 0; |
| 960 | emm_dma_adr.s.adr = adr; |
| 961 | write_csr(mmc, MIO_EMM_DMA_ADR(), emm_dma_adr.u); |
| 962 | write_csr(mmc, MIO_EMM_DMA_CFG(), emm_dma_cfg.u); |
| 963 | |
| 964 | emm_dma.u = 0; |
| 965 | emm_dma.s.bus_id = slot->bus_id; |
| 966 | emm_dma.s.dma_val = 1; |
| 967 | emm_dma.s.rw = !!write; |
| 968 | emm_dma.s.sector = mmc->high_capacity ? 1 : 0; |
| 969 | |
| 970 | if (size > 1 && ((IS_SD(mmc) && (mmc->scr[0] & 2)) || !IS_SD(mmc))) |
| 971 | emm_dma.s.multi = 1; |
| 972 | else |
| 973 | emm_dma.s.multi = 0; |
| 974 | |
| 975 | emm_dma.s.block_cnt = size; |
| 976 | if (!mmc->high_capacity) |
| 977 | block *= mmc->read_bl_len; |
| 978 | emm_dma.s.card_addr = block; |
| 979 | debug("%s(%s): card address: 0x%x, size: %d, multi: %d\n", |
| 980 | __func__, mmc->dev->name, block, size, emm_dma.s.multi); |
| 981 | |
| 982 | if (timeout > 0) |
| 983 | timeout = (timeout * 1000) - 1000; |
| 984 | set_wdog(mmc, timeout); |
| 985 | |
| 986 | debug(" Writing 0x%llx to mio_emm_dma\n", emm_dma.u); |
| 987 | write_csr(mmc, MIO_EMM_DMA(), emm_dma.u); |
| 988 | } |
| 989 | |
| 990 | /** |
| 991 | * Waits for a DMA operation to complete |
| 992 | * |
| 993 | * @param mmc mmc device |
| 994 | * @param timeout timeout in ms |
| 995 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 996 | * Return: 0 for success (could be DMA errors), -ETIMEDOUT on timeout |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 997 | */ |
| 998 | |
| 999 | /** |
| 1000 | * Cleanup DMA engine after a failure |
| 1001 | * |
| 1002 | * @param mmc mmc device |
| 1003 | * @param rsp_sts rsp status |
| 1004 | */ |
| 1005 | static void octeontx_mmc_cleanup_dma(struct mmc *mmc, |
| 1006 | union mio_emm_rsp_sts rsp_sts) |
| 1007 | { |
| 1008 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 1009 | union mio_emm_dma emm_dma; |
| 1010 | ulong start; |
| 1011 | int retries = 3; |
| 1012 | |
| 1013 | do { |
| 1014 | debug("%s(%s): rsp_sts: 0x%llx, rsp_lo: 0x%llx, dma_int: 0x%llx\n", |
| 1015 | __func__, mmc->dev->name, rsp_sts.u, |
| 1016 | read_csr(mmc, MIO_EMM_RSP_LO()), |
| 1017 | read_csr(mmc, MIO_EMM_DMA_INT())); |
| 1018 | emm_dma.u = read_csr(mmc, MIO_EMM_DMA()); |
| 1019 | emm_dma.s.dma_val = 1; |
| 1020 | emm_dma.s.dat_null = 1; |
| 1021 | emm_dma.s.bus_id = slot->bus_id; |
| 1022 | write_csr(mmc, MIO_EMM_DMA(), emm_dma.u); |
| 1023 | start = get_timer(0); |
| 1024 | do { |
| 1025 | rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS()); |
Stefan Roese | 80877fa | 2022-09-02 14:10:46 +0200 | [diff] [blame] | 1026 | schedule(); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 1027 | } while (get_timer(start) < 100 && |
| 1028 | (rsp_sts.s.dma_val || rsp_sts.s.dma_pend)); |
| 1029 | } while (retries-- >= 0 && rsp_sts.s.dma_pend); |
| 1030 | if (rsp_sts.s.dma_val) |
| 1031 | pr_err("%s(%s): Error: could not clean up DMA. RSP_STS: 0x%llx, RSP_LO: 0x%llx\n", |
| 1032 | __func__, mmc->dev->name, rsp_sts.u, |
| 1033 | read_csr(mmc, MIO_EMM_RSP_LO())); |
| 1034 | debug(" rsp_sts after clearing up DMA: 0x%llx\n", |
| 1035 | read_csr(mmc, MIO_EMM_RSP_STS())); |
| 1036 | } |
| 1037 | |
| 1038 | /** |
| 1039 | * Waits for a DMA operation to complete |
| 1040 | * |
| 1041 | * @param mmc mmc device |
| 1042 | * @param timeout timeout in ms |
| 1043 | * @param verbose true to print out error information |
| 1044 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 1045 | * Return: 0 for success (could be DMA errors), -ETIMEDOUT on timeout |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 1046 | * or -EIO if IO error. |
| 1047 | */ |
| 1048 | static int octeontx_mmc_wait_dma(struct mmc *mmc, bool write, ulong timeout, |
| 1049 | bool verbose) |
| 1050 | { |
| 1051 | struct octeontx_mmc_host *host = mmc_to_host(mmc); |
| 1052 | ulong start_time = get_timer(0); |
| 1053 | union mio_emm_dma_int emm_dma_int; |
| 1054 | union mio_emm_rsp_sts rsp_sts; |
| 1055 | union mio_emm_dma emm_dma; |
| 1056 | bool timed_out = false; |
| 1057 | bool err = false; |
| 1058 | |
| 1059 | debug("%s(%s, %lu, %d), delay: %uus\n", __func__, mmc->dev->name, |
| 1060 | timeout, verbose, host->dma_wait_delay); |
| 1061 | |
| 1062 | udelay(host->dma_wait_delay); |
| 1063 | do { |
| 1064 | emm_dma_int.u = read_csr(mmc, MIO_EMM_DMA_INT()); |
| 1065 | rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS()); |
| 1066 | if (write) { |
| 1067 | if ((rsp_sts.s.dma_pend && !rsp_sts.s.dma_val) || |
| 1068 | rsp_sts.s.blk_timeout || |
| 1069 | rsp_sts.s.stp_timeout || |
| 1070 | rsp_sts.s.rsp_timeout) { |
| 1071 | err = true; |
| 1072 | #ifdef DEBUG |
| 1073 | debug("%s: f1\n", __func__); |
| 1074 | octeontx_mmc_print_rsp_errors(mmc, rsp_sts); |
| 1075 | #endif |
| 1076 | break; |
| 1077 | } |
| 1078 | } else { |
| 1079 | if (rsp_sts.s.blk_crc_err || |
| 1080 | (rsp_sts.s.dma_pend && !rsp_sts.s.dma_val)) { |
| 1081 | err = true; |
| 1082 | #if defined(DEBUG) |
| 1083 | octeontx_mmc_print_rsp_errors(mmc, rsp_sts); |
| 1084 | #endif |
| 1085 | break; |
| 1086 | } |
| 1087 | } |
| 1088 | if (rsp_sts.s.dma_pend) { |
| 1089 | /* |
| 1090 | * If this is set then an error has occurred. |
| 1091 | * Try and restart the DMA operation. |
| 1092 | */ |
| 1093 | emm_dma.u = read_csr(mmc, MIO_EMM_DMA()); |
| 1094 | if (verbose) { |
| 1095 | pr_err("%s(%s): DMA pending error: rsp_sts: 0x%llx, dma_int: 0x%llx, emm_dma: 0x%llx\n", |
| 1096 | __func__, mmc->dev->name, rsp_sts.u, |
| 1097 | emm_dma_int.u, emm_dma.u); |
| 1098 | octeontx_print_rsp_sts(mmc); |
| 1099 | debug(" MIO_EMM_DEBUG: 0x%llx\n", |
| 1100 | read_csr(mmc, MIO_EMM_DEBUG())); |
| 1101 | pr_err("%s: Trying DMA resume...\n", __func__); |
| 1102 | } |
| 1103 | emm_dma.s.dma_val = 1; |
| 1104 | emm_dma.s.dat_null = 1; |
| 1105 | write_csr(mmc, MIO_EMM_DMA(), emm_dma.u); |
| 1106 | udelay(10); |
| 1107 | } else if (!rsp_sts.s.dma_val && emm_dma_int.s.done) { |
| 1108 | break; |
| 1109 | } |
Stefan Roese | 80877fa | 2022-09-02 14:10:46 +0200 | [diff] [blame] | 1110 | schedule(); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 1111 | timed_out = (get_timer(start_time) > timeout); |
| 1112 | } while (!timed_out); |
| 1113 | |
| 1114 | if (timed_out || err) { |
| 1115 | if (verbose) { |
| 1116 | pr_err("%s(%s): MMC DMA %s after %lu ms, rsp_sts: 0x%llx, dma_int: 0x%llx, rsp_sts_lo: 0x%llx, emm_dma: 0x%llx\n", |
| 1117 | __func__, mmc->dev->name, |
| 1118 | timed_out ? "timed out" : "error", |
| 1119 | get_timer(start_time), rsp_sts.u, |
| 1120 | emm_dma_int.u, |
| 1121 | read_csr(mmc, MIO_EMM_RSP_LO()), |
| 1122 | read_csr(mmc, MIO_EMM_DMA())); |
| 1123 | octeontx_print_rsp_sts(mmc); |
| 1124 | } |
| 1125 | if (rsp_sts.s.dma_pend) |
| 1126 | octeontx_mmc_cleanup_dma(mmc, rsp_sts); |
| 1127 | } else { |
| 1128 | write_csr(mmc, MIO_EMM_DMA_INT(), |
| 1129 | read_csr(mmc, MIO_EMM_DMA_INT())); |
| 1130 | } |
| 1131 | |
| 1132 | return timed_out ? -ETIMEDOUT : (err ? -EIO : 0); |
| 1133 | } |
| 1134 | |
| 1135 | /** |
| 1136 | * Read blocks from the MMC/SD device |
| 1137 | * |
| 1138 | * @param mmc mmc device |
| 1139 | * @param cmd command |
| 1140 | * @param data data for read |
| 1141 | * @param verbose true to print out error information |
| 1142 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 1143 | * Return: number of blocks read or 0 if error |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 1144 | */ |
| 1145 | static int octeontx_mmc_read_blocks(struct mmc *mmc, struct mmc_cmd *cmd, |
| 1146 | struct mmc_data *data, bool verbose) |
| 1147 | { |
| 1148 | struct octeontx_mmc_host *host = mmc_to_host(mmc); |
| 1149 | union mio_emm_rsp_sts rsp_sts; |
| 1150 | dma_addr_t dma_addr = (dma_addr_t)dm_pci_virt_to_mem(host->dev, |
| 1151 | data->dest); |
| 1152 | ulong count; |
| 1153 | ulong blkcnt = data->blocks; |
| 1154 | ulong start = cmd->cmdarg; |
| 1155 | int timeout = 1000 + blkcnt * 20; |
| 1156 | bool timed_out = false; |
| 1157 | bool multi_xfer = cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK; |
| 1158 | |
| 1159 | debug("%s(%s): dest: %p, dma address: 0x%llx, blkcnt: %lu, start: %lu\n", |
| 1160 | __func__, mmc->dev->name, data->dest, dma_addr, blkcnt, start); |
| 1161 | debug("%s: rsp_sts: 0x%llx\n", __func__, |
| 1162 | read_csr(mmc, MIO_EMM_RSP_STS())); |
| 1163 | /* use max timeout for multi-block transfers */ |
| 1164 | /* timeout = 0; */ |
| 1165 | |
| 1166 | /* |
| 1167 | * If we have a valid SD card in the slot, we set the response bit |
| 1168 | * mask to check for CRC errors and timeouts only. |
| 1169 | * Otherwise, use the default power on reset value. |
| 1170 | */ |
| 1171 | write_csr(mmc, MIO_EMM_STS_MASK(), |
| 1172 | IS_SD(mmc) ? 0x00b00000ull : 0xe4390080ull); |
| 1173 | invalidate_dcache_range((u64)data->dest, |
| 1174 | (u64)data->dest + blkcnt * data->blocksize); |
| 1175 | |
| 1176 | if (multi_xfer) { |
| 1177 | octeontx_mmc_start_dma(mmc, false, false, start, dma_addr, |
| 1178 | blkcnt, timeout); |
| 1179 | timed_out = !!octeontx_mmc_wait_dma(mmc, false, timeout, |
| 1180 | verbose); |
| 1181 | rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS()); |
| 1182 | if (timed_out || rsp_sts.s.dma_val || rsp_sts.s.dma_pend) { |
| 1183 | if (!verbose) |
| 1184 | return 0; |
| 1185 | |
| 1186 | pr_err("%s(%s): Error: DMA timed out. rsp_sts: 0x%llx, emm_int: 0x%llx, dma_int: 0x%llx, rsp_lo: 0x%llx\n", |
| 1187 | __func__, mmc->dev->name, rsp_sts.u, |
| 1188 | read_csr(mmc, MIO_EMM_INT()), |
| 1189 | read_csr(mmc, MIO_EMM_DMA_INT()), |
| 1190 | read_csr(mmc, MIO_EMM_RSP_LO())); |
| 1191 | pr_err("%s: block count: %lu, start: 0x%lx\n", |
| 1192 | __func__, blkcnt, start); |
| 1193 | octeontx_mmc_print_registers(mmc); |
| 1194 | return 0; |
| 1195 | } |
| 1196 | } else { |
| 1197 | count = blkcnt; |
| 1198 | timeout = 1000; |
| 1199 | do { |
| 1200 | octeontx_mmc_start_dma(mmc, false, false, start, |
| 1201 | dma_addr, 1, timeout); |
| 1202 | dma_addr += mmc->read_bl_len; |
| 1203 | start++; |
| 1204 | |
| 1205 | timed_out = !!octeontx_mmc_wait_dma(mmc, false, |
| 1206 | timeout, verbose); |
| 1207 | rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS()); |
| 1208 | if (timed_out || rsp_sts.s.dma_val || |
| 1209 | rsp_sts.s.dma_pend) { |
| 1210 | if (verbose) { |
| 1211 | pr_err("%s: Error: DMA timed out. rsp_sts: 0x%llx, emm_int: 0x%llx, dma_int: 0x%llx, rsp_lo: 0x%llx\n", |
| 1212 | __func__, rsp_sts.u, |
| 1213 | read_csr(mmc, MIO_EMM_INT()), |
| 1214 | read_csr(mmc, MIO_EMM_DMA_INT()), |
| 1215 | read_csr(mmc, MIO_EMM_RSP_LO())); |
| 1216 | pr_err("%s: block count: 1, start: 0x%lx\n", |
| 1217 | __func__, start); |
| 1218 | octeontx_mmc_print_registers(mmc); |
| 1219 | } |
| 1220 | return blkcnt - count; |
| 1221 | } |
Stefan Roese | 80877fa | 2022-09-02 14:10:46 +0200 | [diff] [blame] | 1222 | schedule(); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 1223 | } while (--count); |
| 1224 | } |
| 1225 | #ifdef DEBUG |
| 1226 | debug("%s(%s): Read %lu (0x%lx) blocks starting at block %u (0x%x) to address %p (dma address 0x%llx)\n", |
| 1227 | __func__, mmc->dev->name, blkcnt, blkcnt, |
| 1228 | cmd->cmdarg, cmd->cmdarg, data->dest, |
| 1229 | dm_pci_virt_to_mem(host->dev, data->dest)); |
| 1230 | print_buffer(0, data->dest, 1, 0x200, 0); |
| 1231 | #endif |
| 1232 | return blkcnt; |
| 1233 | } |
| 1234 | |
| 1235 | static int octeontx_mmc_poll_ready(struct mmc *mmc, ulong timeout) |
| 1236 | { |
| 1237 | ulong start; |
| 1238 | struct mmc_cmd cmd; |
| 1239 | int err; |
| 1240 | bool not_ready = false; |
| 1241 | |
| 1242 | memset(&cmd, 0, sizeof(cmd)); |
| 1243 | cmd.cmdidx = MMC_CMD_SEND_STATUS; |
| 1244 | cmd.cmdarg = mmc->rca << 16; |
| 1245 | cmd.resp_type = MMC_RSP_R1; |
| 1246 | start = get_timer(0); |
| 1247 | do { |
| 1248 | err = octeontx_mmc_send_cmd(mmc, &cmd, NULL); |
| 1249 | if (err) { |
| 1250 | pr_err("%s(%s): MMC command error: %d; Retry...\n", |
| 1251 | __func__, mmc->dev->name, err); |
| 1252 | not_ready = true; |
| 1253 | } else if (cmd.response[0] & R1_READY_FOR_DATA) { |
| 1254 | return 0; |
| 1255 | } |
Stefan Roese | 80877fa | 2022-09-02 14:10:46 +0200 | [diff] [blame] | 1256 | schedule(); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 1257 | } while (get_timer(start) < timeout); |
| 1258 | |
| 1259 | if (not_ready) |
| 1260 | pr_err("%s(%s): MMC command error; Retry timeout\n", |
| 1261 | __func__, mmc->dev->name); |
| 1262 | return -ETIMEDOUT; |
| 1263 | } |
| 1264 | |
| 1265 | static ulong octeontx_mmc_write_blocks(struct mmc *mmc, struct mmc_cmd *cmd, |
| 1266 | struct mmc_data *data) |
| 1267 | { |
| 1268 | struct octeontx_mmc_host *host = mmc_to_host(mmc); |
| 1269 | ulong start = cmd->cmdarg; |
| 1270 | ulong blkcnt = data->blocks; |
| 1271 | dma_addr_t dma_addr; |
| 1272 | union mio_emm_rsp_sts rsp_sts; |
| 1273 | union mio_emm_sts_mask emm_sts_mask; |
| 1274 | ulong timeout; |
| 1275 | int count; |
| 1276 | bool timed_out = false; |
| 1277 | bool multi_xfer = (blkcnt > 1) && |
| 1278 | ((IS_SD(mmc) && mmc->scr[0] & 2) || !IS_SD(mmc)); |
| 1279 | |
| 1280 | octeontx_mmc_switch_to(mmc); |
| 1281 | emm_sts_mask.u = 0; |
| 1282 | emm_sts_mask.s.sts_msk = R1_BLOCK_WRITE_MASK; |
| 1283 | write_csr(mmc, MIO_EMM_STS_MASK(), emm_sts_mask.u); |
| 1284 | |
| 1285 | if (octeontx_mmc_poll_ready(mmc, 10000)) { |
| 1286 | pr_err("%s(%s): Ready timed out\n", __func__, mmc->dev->name); |
| 1287 | return 0; |
| 1288 | } |
| 1289 | flush_dcache_range((u64)data->src, |
| 1290 | (u64)data->src + blkcnt * mmc->write_bl_len); |
| 1291 | dma_addr = (u64)dm_pci_virt_to_mem(host->dev, (void *)data->src); |
| 1292 | if (multi_xfer) { |
| 1293 | timeout = 5000 + 100 * blkcnt; |
| 1294 | octeontx_mmc_start_dma(mmc, true, false, start, dma_addr, |
| 1295 | blkcnt, timeout); |
| 1296 | timed_out = !!octeontx_mmc_wait_dma(mmc, true, timeout, true); |
| 1297 | rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS()); |
| 1298 | if (timed_out || rsp_sts.s.dma_val || rsp_sts.s.dma_pend) { |
| 1299 | pr_err("%s(%s): Error: multi-DMA timed out after %lums. rsp_sts: 0x%llx, emm_int: 0x%llx, emm_dma_int: 0x%llx, rsp_sts_lo: 0x%llx, emm_dma: 0x%llx\n", |
| 1300 | __func__, mmc->dev->name, timeout, |
| 1301 | rsp_sts.u, |
| 1302 | read_csr(mmc, MIO_EMM_INT()), |
| 1303 | read_csr(mmc, MIO_EMM_DMA_INT()), |
| 1304 | read_csr(mmc, MIO_EMM_RSP_LO()), |
| 1305 | read_csr(mmc, MIO_EMM_DMA())); |
| 1306 | return 0; |
| 1307 | } |
| 1308 | } else { |
| 1309 | timeout = 5000; |
| 1310 | count = blkcnt; |
| 1311 | do { |
| 1312 | octeontx_mmc_start_dma(mmc, true, false, start, |
| 1313 | dma_addr, 1, timeout); |
| 1314 | dma_addr += mmc->read_bl_len; |
| 1315 | start++; |
| 1316 | |
| 1317 | timed_out = !!octeontx_mmc_wait_dma(mmc, true, timeout, |
| 1318 | true); |
| 1319 | rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS()); |
| 1320 | if (timed_out || rsp_sts.s.dma_val || |
| 1321 | rsp_sts.s.dma_pend) { |
| 1322 | pr_err("%s(%s): Error: single-DMA timed out after %lums. rsp_sts: 0x%llx, emm_int: 0x%llx, emm_dma_int: 0x%llx, rsp_sts_lo: 0x%llx, emm_dma: 0x%llx\n", |
| 1323 | __func__, mmc->dev->name, timeout, |
| 1324 | rsp_sts.u, |
| 1325 | read_csr(mmc, MIO_EMM_RSP_STS()), |
| 1326 | read_csr(mmc, MIO_EMM_DMA_INT()), |
| 1327 | read_csr(mmc, MIO_EMM_RSP_LO()), |
| 1328 | read_csr(mmc, MIO_EMM_DMA())); |
| 1329 | return blkcnt - count; |
| 1330 | } |
Stefan Roese | 80877fa | 2022-09-02 14:10:46 +0200 | [diff] [blame] | 1331 | schedule(); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 1332 | } while (--count); |
| 1333 | } |
| 1334 | |
| 1335 | return blkcnt; |
| 1336 | } |
| 1337 | |
| 1338 | /** |
| 1339 | * Send a command to the eMMC/SD device |
| 1340 | * |
| 1341 | * @param mmc mmc device |
| 1342 | * @param cmd cmd to send and response |
| 1343 | * @param data additional data |
| 1344 | * @param flags |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 1345 | * Return: 0 for success, otherwise error |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 1346 | */ |
| 1347 | static int octeontx_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
| 1348 | struct mmc_data *data) |
| 1349 | { |
| 1350 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 1351 | const char *name = slot->dev->name; |
| 1352 | struct octeontx_mmc_cr_mods mods = {0, 0}; |
| 1353 | union mio_emm_rsp_sts rsp_sts; |
| 1354 | union mio_emm_cmd emm_cmd; |
| 1355 | union mio_emm_rsp_lo rsp_lo; |
| 1356 | union mio_emm_buf_idx emm_buf_idx; |
| 1357 | union mio_emm_buf_dat emm_buf_dat; |
| 1358 | ulong start; |
| 1359 | int i; |
| 1360 | ulong blkcnt; |
| 1361 | |
| 1362 | /** |
| 1363 | * This constant has a 1 bit for each command which should have a short |
| 1364 | * timeout and a 0 for each bit with a long timeout. Currently the |
| 1365 | * following commands have a long timeout: |
| 1366 | * CMD6, CMD17, CMD18, CMD24, CMD25, CMD32, CMD33, CMD35, CMD36 and |
| 1367 | * CMD38. |
| 1368 | */ |
| 1369 | static const u64 timeout_short = 0xFFFFFFA4FCF9FFDFull; |
| 1370 | uint timeout; |
| 1371 | |
| 1372 | if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD) { |
| 1373 | union mio_emm_rca emm_rca; |
| 1374 | |
| 1375 | emm_rca.u = 0; |
| 1376 | emm_rca.s.card_rca = mmc->rca; |
| 1377 | write_csr(mmc, MIO_EMM_RCA(), emm_rca.u); |
| 1378 | } |
| 1379 | |
| 1380 | if (timeout_short & (1ull << cmd->cmdidx)) |
| 1381 | timeout = MMC_TIMEOUT_SHORT; |
| 1382 | else if (cmd->cmdidx == MMC_CMD_SWITCH && IS_SD(mmc)) |
| 1383 | timeout = 2560; |
| 1384 | else if (cmd->cmdidx == MMC_CMD_ERASE) |
| 1385 | timeout = MMC_TIMEOUT_ERASE; |
| 1386 | else |
| 1387 | timeout = MMC_TIMEOUT_LONG; |
| 1388 | |
| 1389 | debug("%s(%s): cmd idx: %u, arg: 0x%x, resp type: 0x%x, timeout: %u\n", |
| 1390 | __func__, name, cmd->cmdidx, cmd->cmdarg, cmd->resp_type, |
| 1391 | timeout); |
| 1392 | if (data) |
| 1393 | debug(" data: addr: %p, flags: 0x%x, blocks: %u, blocksize: %u\n", |
| 1394 | data->dest, data->flags, data->blocks, data->blocksize); |
| 1395 | |
| 1396 | octeontx_mmc_switch_to(mmc); |
| 1397 | |
| 1398 | /* Clear any interrupts */ |
| 1399 | write_csr(mmc, MIO_EMM_INT(), read_csr(mmc, MIO_EMM_INT())); |
| 1400 | |
| 1401 | /* |
| 1402 | * We need to override the default command types and response types |
| 1403 | * when dealing with SD cards. |
| 1404 | */ |
| 1405 | mods = octeontx_mmc_get_cr_mods(mmc, cmd, data); |
| 1406 | |
| 1407 | /* Handle block read/write/stop operations */ |
| 1408 | switch (cmd->cmdidx) { |
| 1409 | case MMC_CMD_GO_IDLE_STATE: |
| 1410 | slot->tuned = false; |
| 1411 | slot->hs200_tuned = false; |
| 1412 | slot->hs400_tuned = false; |
| 1413 | break; |
| 1414 | case MMC_CMD_STOP_TRANSMISSION: |
| 1415 | return 0; |
| 1416 | case MMC_CMD_READ_MULTIPLE_BLOCK: |
| 1417 | case MMC_CMD_READ_SINGLE_BLOCK: |
| 1418 | pr_debug("%s(%s): Reading blocks\n", __func__, name); |
| 1419 | blkcnt = octeontx_mmc_read_blocks(mmc, cmd, data, true); |
| 1420 | return (blkcnt > 0) ? 0 : -1; |
| 1421 | case MMC_CMD_WRITE_MULTIPLE_BLOCK: |
| 1422 | case MMC_CMD_WRITE_SINGLE_BLOCK: |
| 1423 | blkcnt = octeontx_mmc_write_blocks(mmc, cmd, data); |
| 1424 | return (blkcnt > 0) ? 0 : -1; |
| 1425 | case MMC_CMD_SELECT_CARD: |
| 1426 | /* Set the RCA register (is it set automatically?) */ |
| 1427 | if (IS_SD(mmc)) { |
| 1428 | union mio_emm_rca emm_rca; |
| 1429 | |
| 1430 | emm_rca.u = 0; |
| 1431 | emm_rca.s.card_rca = (cmd->cmdarg >> 16); |
| 1432 | write_csr(mmc, MIO_EMM_RCA(), emm_rca.u); |
| 1433 | debug("%s: Set SD relative address (RCA) to 0x%x\n", |
| 1434 | __func__, emm_rca.s.card_rca); |
| 1435 | } |
| 1436 | break; |
| 1437 | |
| 1438 | case MMC_CMD_SWITCH: |
| 1439 | if (!data && !slot->is_acmd) |
| 1440 | octeontx_mmc_track_switch(mmc, cmd->cmdarg); |
| 1441 | break; |
| 1442 | } |
| 1443 | |
| 1444 | emm_cmd.u = 0; |
| 1445 | emm_cmd.s.cmd_val = 1; |
| 1446 | emm_cmd.s.bus_id = slot->bus_id; |
| 1447 | emm_cmd.s.cmd_idx = cmd->cmdidx; |
| 1448 | emm_cmd.s.arg = cmd->cmdarg; |
| 1449 | emm_cmd.s.ctype_xor = mods.ctype_xor; |
| 1450 | emm_cmd.s.rtype_xor = mods.rtype_xor; |
| 1451 | if (data && data->blocks == 1 && data->blocksize != 512) { |
| 1452 | emm_cmd.s.offset = |
| 1453 | 64 - ((data->blocks * data->blocksize) / 8); |
| 1454 | debug("%s: offset set to %u\n", __func__, emm_cmd.s.offset); |
| 1455 | } |
| 1456 | |
| 1457 | if (data && data->flags & MMC_DATA_WRITE) { |
| 1458 | u8 *src = (u8 *)data->src; |
| 1459 | |
| 1460 | if (!src) { |
| 1461 | pr_err("%s(%s): Error: data source for cmd 0x%x is NULL!\n", |
| 1462 | __func__, name, cmd->cmdidx); |
| 1463 | return -1; |
| 1464 | } |
| 1465 | if (data->blocksize > 512) { |
| 1466 | pr_err("%s(%s): Error: data for cmd 0x%x exceeds 512 bytes\n", |
| 1467 | __func__, name, cmd->cmdidx); |
| 1468 | return -1; |
| 1469 | } |
| 1470 | #ifdef DEBUG |
| 1471 | debug("%s: Sending %d bytes data\n", __func__, data->blocksize); |
| 1472 | print_buffer(0, src, 1, data->blocksize, 0); |
| 1473 | #endif |
| 1474 | emm_buf_idx.u = 0; |
| 1475 | emm_buf_idx.s.inc = 1; |
| 1476 | write_csr(mmc, MIO_EMM_BUF_IDX(), emm_buf_idx.u); |
| 1477 | for (i = 0; i < (data->blocksize + 7) / 8; i++) { |
| 1478 | memcpy(&emm_buf_dat.u, src, sizeof(emm_buf_dat.u)); |
| 1479 | write_csr(mmc, MIO_EMM_BUF_DAT(), |
| 1480 | cpu_to_be64(emm_buf_dat.u)); |
| 1481 | src += sizeof(emm_buf_dat.u); |
| 1482 | } |
| 1483 | write_csr(mmc, MIO_EMM_BUF_IDX(), 0); |
| 1484 | } |
| 1485 | debug("%s(%s): Sending command %u (emm_cmd: 0x%llx)\n", __func__, |
| 1486 | name, cmd->cmdidx, emm_cmd.u); |
| 1487 | set_wdog(mmc, timeout * 1000); |
| 1488 | write_csr(mmc, MIO_EMM_CMD(), emm_cmd.u); |
| 1489 | |
| 1490 | /* Wait for command to finish or time out */ |
| 1491 | start = get_timer(0); |
| 1492 | do { |
| 1493 | rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS()); |
Stefan Roese | 80877fa | 2022-09-02 14:10:46 +0200 | [diff] [blame] | 1494 | schedule(); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 1495 | } while (!rsp_sts.s.cmd_done && !rsp_sts.s.rsp_timeout && |
| 1496 | (get_timer(start) < timeout + 10)); |
| 1497 | octeontx_mmc_print_rsp_errors(mmc, rsp_sts); |
| 1498 | if (rsp_sts.s.rsp_timeout || !rsp_sts.s.cmd_done) { |
| 1499 | debug("%s(%s): Error: command %u(0x%x) timed out. rsp_sts: 0x%llx\n", |
| 1500 | __func__, name, cmd->cmdidx, cmd->cmdarg, rsp_sts.u); |
| 1501 | octeontx_mmc_print_registers(mmc); |
| 1502 | return -ETIMEDOUT; |
| 1503 | } |
| 1504 | if (rsp_sts.s.rsp_crc_err) { |
| 1505 | debug("%s(%s): RSP CRC error, rsp_sts: 0x%llx, cmdidx: %u, arg: 0x%08x\n", |
| 1506 | __func__, name, rsp_sts.u, cmd->cmdidx, cmd->cmdarg); |
| 1507 | octeontx_mmc_print_registers(mmc); |
| 1508 | return -1; |
| 1509 | } |
| 1510 | if (slot->bus_id != rsp_sts.s.bus_id) { |
| 1511 | pr_warn("%s(%s): bus id mismatch, got %d, expected %d for command 0x%x(0x%x)\n", |
| 1512 | __func__, name, |
| 1513 | rsp_sts.s.bus_id, slot->bus_id, |
| 1514 | cmd->cmdidx, cmd->cmdarg); |
| 1515 | goto error; |
| 1516 | } |
| 1517 | if (rsp_sts.s.rsp_bad_sts) { |
| 1518 | rsp_lo.u = read_csr(mmc, MIO_EMM_RSP_LO()); |
| 1519 | debug("%s: Bad response for bus id %d, cmd id %d:\n" |
| 1520 | " rsp_timeout: %d\n" |
| 1521 | " rsp_bad_sts: %d\n" |
| 1522 | " rsp_crc_err: %d\n", |
| 1523 | __func__, slot->bus_id, cmd->cmdidx, |
| 1524 | rsp_sts.s.rsp_timeout, |
| 1525 | rsp_sts.s.rsp_bad_sts, |
| 1526 | rsp_sts.s.rsp_crc_err); |
| 1527 | if (rsp_sts.s.rsp_type == 1 && rsp_sts.s.rsp_bad_sts) { |
| 1528 | debug(" Response status: 0x%llx\n", |
| 1529 | (rsp_lo.u >> 8) & 0xffffffff); |
| 1530 | #ifdef DEBUG |
| 1531 | mmc_print_status((rsp_lo.u >> 8) & 0xffffffff); |
| 1532 | #endif |
| 1533 | } |
| 1534 | goto error; |
| 1535 | } |
| 1536 | if (rsp_sts.s.cmd_idx != cmd->cmdidx) { |
| 1537 | debug("%s(%s): Command response index %d does not match command index %d\n", |
| 1538 | __func__, name, rsp_sts.s.cmd_idx, cmd->cmdidx); |
| 1539 | octeontx_print_rsp_sts(mmc); |
| 1540 | debug("%s: rsp_lo: 0x%llx\n", __func__, |
| 1541 | read_csr(mmc, MIO_EMM_RSP_LO())); |
| 1542 | |
| 1543 | goto error; |
| 1544 | } |
| 1545 | |
| 1546 | slot->is_acmd = (cmd->cmdidx == MMC_CMD_APP_CMD); |
| 1547 | |
| 1548 | if (!cmd->resp_type & MMC_RSP_PRESENT) |
| 1549 | debug(" Response type: 0x%x, no response expected\n", |
| 1550 | cmd->resp_type); |
| 1551 | /* Get the response if present */ |
| 1552 | if (rsp_sts.s.rsp_val && (cmd->resp_type & MMC_RSP_PRESENT)) { |
| 1553 | union mio_emm_rsp_hi rsp_hi; |
| 1554 | |
| 1555 | rsp_lo.u = read_csr(mmc, MIO_EMM_RSP_LO()); |
| 1556 | |
| 1557 | switch (rsp_sts.s.rsp_type) { |
| 1558 | case 1: |
| 1559 | case 3: |
| 1560 | case 4: |
| 1561 | case 5: |
| 1562 | cmd->response[0] = (rsp_lo.u >> 8) & 0xffffffffull; |
| 1563 | debug(" response: 0x%08x\n", |
| 1564 | cmd->response[0]); |
| 1565 | cmd->response[1] = 0; |
| 1566 | cmd->response[2] = 0; |
| 1567 | cmd->response[3] = 0; |
| 1568 | break; |
| 1569 | case 2: |
| 1570 | cmd->response[3] = rsp_lo.u & 0xffffffff; |
| 1571 | cmd->response[2] = (rsp_lo.u >> 32) & 0xffffffff; |
| 1572 | rsp_hi.u = read_csr(mmc, MIO_EMM_RSP_HI()); |
| 1573 | cmd->response[1] = rsp_hi.u & 0xffffffff; |
| 1574 | cmd->response[0] = (rsp_hi.u >> 32) & 0xffffffff; |
| 1575 | debug(" response: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 1576 | cmd->response[0], cmd->response[1], |
| 1577 | cmd->response[2], cmd->response[3]); |
| 1578 | break; |
| 1579 | default: |
| 1580 | pr_err("%s(%s): Unknown response type 0x%x for command %d, arg: 0x%x, rsp_sts: 0x%llx\n", |
| 1581 | __func__, name, rsp_sts.s.rsp_type, cmd->cmdidx, |
| 1582 | cmd->cmdarg, rsp_sts.u); |
| 1583 | return -1; |
| 1584 | } |
| 1585 | } else { |
| 1586 | debug(" Response not expected\n"); |
| 1587 | } |
| 1588 | |
| 1589 | if (data && data->flags & MMC_DATA_READ) { |
| 1590 | u8 *dest = (u8 *)data->dest; |
| 1591 | |
| 1592 | if (!dest) { |
| 1593 | pr_err("%s(%s): Error, destination buffer NULL!\n", |
| 1594 | __func__, mmc->dev->name); |
| 1595 | goto error; |
| 1596 | } |
| 1597 | if (data->blocksize > 512) { |
| 1598 | printf("%s(%s): Error: data size %u exceeds 512\n", |
| 1599 | __func__, mmc->dev->name, |
| 1600 | data->blocksize); |
| 1601 | goto error; |
| 1602 | } |
| 1603 | emm_buf_idx.u = 0; |
| 1604 | emm_buf_idx.s.inc = 1; |
| 1605 | write_csr(mmc, MIO_EMM_BUF_IDX(), emm_buf_idx.u); |
| 1606 | for (i = 0; i < (data->blocksize + 7) / 8; i++) { |
| 1607 | emm_buf_dat.u = read_csr(mmc, MIO_EMM_BUF_DAT()); |
| 1608 | emm_buf_dat.u = be64_to_cpu(emm_buf_dat.u); |
| 1609 | memcpy(dest, &emm_buf_dat.u, sizeof(emm_buf_dat.u)); |
| 1610 | dest += sizeof(emm_buf_dat.u); |
| 1611 | } |
| 1612 | write_csr(mmc, MIO_EMM_BUF_IDX(), 0); |
| 1613 | #ifdef DEBUG |
| 1614 | debug("%s: Received %d bytes data\n", __func__, |
| 1615 | data->blocksize); |
| 1616 | print_buffer(0, data->dest, 1, data->blocksize, 0); |
| 1617 | #endif |
| 1618 | } |
| 1619 | |
| 1620 | return 0; |
| 1621 | error: |
| 1622 | #ifdef DEBUG |
| 1623 | octeontx_mmc_print_registers(mmc); |
| 1624 | #endif |
| 1625 | return -1; |
| 1626 | } |
| 1627 | |
| 1628 | static int octeontx_mmc_dev_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
| 1629 | struct mmc_data *data) |
| 1630 | { |
| 1631 | return octeontx_mmc_send_cmd(dev_to_mmc(dev), cmd, data); |
| 1632 | } |
| 1633 | |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 1634 | #if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 1635 | static int octeontx_mmc_test_cmd(struct mmc *mmc, u32 opcode, int *statp) |
| 1636 | { |
| 1637 | struct mmc_cmd cmd; |
| 1638 | int err; |
| 1639 | |
| 1640 | memset(&cmd, 0, sizeof(cmd)); |
| 1641 | |
| 1642 | debug("%s(%s, %u, %p)\n", __func__, mmc->dev->name, opcode, statp); |
| 1643 | cmd.cmdidx = opcode; |
| 1644 | cmd.resp_type = MMC_RSP_R1; |
| 1645 | cmd.cmdarg = mmc->rca << 16; |
| 1646 | |
| 1647 | err = octeontx_mmc_send_cmd(mmc, &cmd, NULL); |
| 1648 | if (err) |
| 1649 | debug("%s(%s, %u) returned %d\n", __func__, |
| 1650 | mmc->dev->name, opcode, err); |
| 1651 | if (statp) |
| 1652 | *statp = cmd.response[0]; |
| 1653 | return err; |
| 1654 | } |
| 1655 | |
Marek Vasut | dad81fb | 2024-02-20 09:36:23 +0100 | [diff] [blame] | 1656 | static int octeontx_mmc_send_tuning(struct mmc *mmc, u32 opcode, int *error) |
| 1657 | { |
| 1658 | *error = 0; |
| 1659 | return mmc_send_tuning(mmc, opcode); |
| 1660 | } |
| 1661 | |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 1662 | static int octeontx_mmc_test_get_ext_csd(struct mmc *mmc, u32 opcode, |
| 1663 | int *statp) |
| 1664 | { |
| 1665 | struct mmc_cmd cmd; |
| 1666 | struct mmc_data data; |
| 1667 | int err; |
| 1668 | u8 ext_csd[MMC_MAX_BLOCK_LEN]; |
| 1669 | |
| 1670 | debug("%s(%s, %u, %p)\n", __func__, mmc->dev->name, opcode, statp); |
| 1671 | memset(&cmd, 0, sizeof(cmd)); |
| 1672 | |
| 1673 | cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; |
| 1674 | cmd.resp_type = MMC_RSP_R1; |
| 1675 | cmd.cmdarg = 0; |
| 1676 | |
| 1677 | data.dest = (char *)ext_csd; |
| 1678 | data.blocks = 1; |
| 1679 | data.blocksize = MMC_MAX_BLOCK_LEN; |
| 1680 | data.flags = MMC_DATA_READ; |
| 1681 | |
| 1682 | err = octeontx_mmc_send_cmd(mmc, &cmd, &data); |
| 1683 | if (statp) |
| 1684 | *statp = cmd.response[0]; |
| 1685 | |
| 1686 | return err; |
| 1687 | } |
| 1688 | |
| 1689 | /** |
| 1690 | * Wrapper to set the MIO_EMM_TIMING register |
| 1691 | * |
| 1692 | * @param mmc pointer to mmc data structure |
| 1693 | * @param emm_timing New emm_timing register value |
| 1694 | * |
| 1695 | * On some devices it is possible that changing the data out value can |
| 1696 | * cause a glitch on an internal fifo. This works around this problem |
| 1697 | * by performing a soft-reset immediately before setting the timing register. |
| 1698 | * |
| 1699 | * Note: this function should not be called from any function that |
| 1700 | * performs DMA or block operations since not all registers are |
| 1701 | * preserved. |
| 1702 | */ |
| 1703 | static void octeontx_mmc_set_emm_timing(struct mmc *mmc, |
| 1704 | union mio_emm_timing emm_timing) |
| 1705 | { |
| 1706 | union mio_emm_cfg emm_cfg; |
| 1707 | struct octeontx_mmc_slot *slot = mmc->priv; |
| 1708 | union mio_emm_debug emm_debug; |
| 1709 | |
| 1710 | debug("%s(%s, 0x%llx) din: %u\n", __func__, mmc->dev->name, |
| 1711 | emm_timing.u, emm_timing.s.data_in_tap); |
| 1712 | |
| 1713 | udelay(1); |
| 1714 | if (slot->host->tap_requires_noclk) { |
| 1715 | /* Turn off the clock */ |
| 1716 | emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG()); |
| 1717 | emm_debug.s.emmc_clk_disable = 1; |
| 1718 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 1719 | udelay(1); |
| 1720 | emm_debug.s.rdsync_rst = 1; |
| 1721 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 1722 | } |
| 1723 | emm_cfg.u = read_csr(mmc, MIO_EMM_CFG()); |
| 1724 | emm_cfg.s.bus_ena = 1 << 3; |
| 1725 | write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u); |
| 1726 | |
| 1727 | udelay(1); |
| 1728 | write_csr(mmc, MIO_EMM_TIMING(), emm_timing.u); |
| 1729 | udelay(1); |
| 1730 | |
| 1731 | if (slot->host->tap_requires_noclk) { |
| 1732 | /* Turn on the clock */ |
| 1733 | emm_debug.s.rdsync_rst = 0; |
| 1734 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 1735 | udelay(1); |
| 1736 | emm_debug.s.emmc_clk_disable = 0; |
| 1737 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 1738 | udelay(1); |
| 1739 | } |
| 1740 | emm_cfg.s.bus_ena = 1 << mmc_to_slot(mmc)->bus_id; |
| 1741 | write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u); |
| 1742 | } |
| 1743 | |
| 1744 | static const u8 octeontx_hs400_tuning_block[512] = { |
| 1745 | 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00, |
| 1746 | 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc, |
| 1747 | 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff, |
| 1748 | 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff, |
| 1749 | 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd, |
| 1750 | 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb, |
| 1751 | 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff, |
| 1752 | 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff, |
| 1753 | 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, |
| 1754 | 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, |
| 1755 | 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, |
| 1756 | 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, |
| 1757 | 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, |
| 1758 | 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, |
| 1759 | 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, |
| 1760 | 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, |
| 1761 | 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00, |
| 1762 | 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc, |
| 1763 | 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff, |
| 1764 | 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff, |
| 1765 | 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd, |
| 1766 | 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb, |
| 1767 | 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff, |
| 1768 | 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff, |
| 1769 | 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, |
| 1770 | 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, |
| 1771 | 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, |
| 1772 | 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, |
| 1773 | 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, |
| 1774 | 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, |
| 1775 | 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, |
| 1776 | 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, |
| 1777 | 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00, |
| 1778 | 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc, |
| 1779 | 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff, |
| 1780 | 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff, |
| 1781 | 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd, |
| 1782 | 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb, |
| 1783 | 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff, |
| 1784 | 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff, |
| 1785 | 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, |
| 1786 | 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, |
| 1787 | 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, |
| 1788 | 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, |
| 1789 | 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, |
| 1790 | 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, |
| 1791 | 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, |
| 1792 | 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, |
| 1793 | 0xff, 0x00, 0x00, 0xff, 0xff, 0x00, 0xff, 0x00, |
| 1794 | 0x00, 0xff, 0x00, 0xff, 0x55, 0xaa, 0x55, 0xaa, |
| 1795 | 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff, |
| 1796 | 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff, |
| 1797 | 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd, |
| 1798 | 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb, |
| 1799 | 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff, |
| 1800 | 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff, |
| 1801 | 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, |
| 1802 | 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, |
| 1803 | 0x01, 0xfe, 0x01, 0xfe, 0xcc, 0xcc, 0xcc, 0xff, |
| 1804 | 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, |
| 1805 | 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, |
| 1806 | 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, |
| 1807 | 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, |
| 1808 | 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, |
| 1809 | |
| 1810 | }; |
| 1811 | |
| 1812 | /** |
| 1813 | * Perform tuning in HS400 mode |
| 1814 | * |
| 1815 | * @param[in] mmc mmc data structure |
| 1816 | * |
| 1817 | * @ret 0 for success, otherwise error |
| 1818 | */ |
| 1819 | static int octeontx_tune_hs400(struct mmc *mmc) |
| 1820 | { |
| 1821 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 1822 | struct mmc_cmd cmd; |
| 1823 | struct mmc_data data; |
| 1824 | union mio_emm_timing emm_timing; |
| 1825 | u8 buffer[mmc->read_bl_len]; |
| 1826 | int tap_adj; |
| 1827 | int err = -1; |
| 1828 | int tap; |
| 1829 | int run = 0; |
| 1830 | int start_run = -1; |
| 1831 | int best_run = 0; |
| 1832 | int best_start = -1; |
| 1833 | bool prev_ok = false; |
| 1834 | char env_name[64]; |
| 1835 | char how[MAX_NO_OF_TAPS + 1] = ""; |
| 1836 | |
| 1837 | if (slot->hs400_tuning_block == -1) |
| 1838 | return 0; |
| 1839 | |
| 1840 | /* The eMMC standard disables all tuning support when operating in |
| 1841 | * DDR modes like HS400. The problem with this is that there are |
| 1842 | * many cases where the HS200 tuning does not work for HS400 mode. |
| 1843 | * In order to perform this tuning, while in HS200 a block is written |
| 1844 | * to a block specified in the device tree (marvell,hs400-tuning-block) |
| 1845 | * which is used for tuning in this function by repeatedly reading |
| 1846 | * this block and comparing the data and return code. This function |
| 1847 | * chooses the data input tap in the middle of the longest run of |
| 1848 | * successful read operations. |
| 1849 | */ |
| 1850 | |
| 1851 | emm_timing = slot->hs200_taps; |
| 1852 | debug("%s(%s): Start ci: %d, co: %d, di: %d, do: %d\n", |
| 1853 | __func__, mmc->dev->name, emm_timing.s.cmd_in_tap, |
| 1854 | emm_timing.s.cmd_out_tap, emm_timing.s.data_in_tap, |
| 1855 | emm_timing.s.data_out_tap); |
| 1856 | memset(buffer, 0xdb, sizeof(buffer)); |
| 1857 | |
| 1858 | snprintf(env_name, sizeof(env_name), "emmc%d_data_in_tap_hs400", |
| 1859 | slot->bus_id); |
| 1860 | tap = env_get_ulong(env_name, 10, -1L); |
| 1861 | if (tap >= 0 && tap < MAX_NO_OF_TAPS) { |
| 1862 | printf("Overriding data input tap for HS400 mode to %d\n", tap); |
| 1863 | emm_timing.s.data_in_tap = tap; |
| 1864 | octeontx_mmc_set_emm_timing(mmc, emm_timing); |
| 1865 | return 0; |
| 1866 | } |
| 1867 | |
| 1868 | for (tap = 0; tap <= MAX_NO_OF_TAPS; tap++, prev_ok = !err) { |
| 1869 | if (tap < MAX_NO_OF_TAPS) { |
| 1870 | debug("%s: Testing data in tap %d\n", __func__, tap); |
| 1871 | emm_timing.s.data_in_tap = tap; |
| 1872 | octeontx_mmc_set_emm_timing(mmc, emm_timing); |
| 1873 | |
| 1874 | cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; |
| 1875 | cmd.cmdarg = slot->hs400_tuning_block; |
| 1876 | cmd.resp_type = MMC_RSP_R1; |
| 1877 | data.dest = (void *)buffer; |
| 1878 | data.blocks = 1; |
| 1879 | data.blocksize = mmc->read_bl_len; |
| 1880 | data.flags = MMC_DATA_READ; |
| 1881 | err = !octeontx_mmc_read_blocks(mmc, &cmd, &data, |
| 1882 | false); |
| 1883 | if (err || memcmp(buffer, octeontx_hs400_tuning_block, |
| 1884 | sizeof(buffer))) { |
| 1885 | #ifdef DEBUG |
| 1886 | if (!err) { |
| 1887 | debug("%s: data mismatch. Read:\n", |
| 1888 | __func__); |
| 1889 | print_buffer(0, buffer, 1, |
| 1890 | sizeof(buffer), 0); |
| 1891 | debug("\nExpected:\n"); |
| 1892 | print_buffer(0, |
| 1893 | octeontx_hs400_tuning_block, 1, |
| 1894 | sizeof(octeontx_hs400_tuning_block), |
| 1895 | 0); |
| 1896 | } else { |
| 1897 | debug("%s: Error %d reading block\n", |
| 1898 | __func__, err); |
| 1899 | } |
| 1900 | #endif |
| 1901 | err = -EINVAL; |
| 1902 | } else { |
| 1903 | debug("%s: tap %d good\n", __func__, tap); |
| 1904 | } |
| 1905 | how[tap] = "-+"[!err]; |
| 1906 | } else { |
| 1907 | err = -EINVAL; |
| 1908 | } |
| 1909 | |
| 1910 | if (!err) { |
| 1911 | if (!prev_ok) |
| 1912 | start_run = tap; |
| 1913 | } else if (prev_ok) { |
| 1914 | run = tap - 1 - start_run; |
| 1915 | if (start_run >= 0 && run > best_run) { |
| 1916 | best_start = start_run; |
| 1917 | best_run = run; |
| 1918 | } |
| 1919 | } |
| 1920 | } |
| 1921 | |
| 1922 | how[tap - 1] = '\0'; |
| 1923 | if (best_start < 0) { |
| 1924 | printf("%s(%s): %lldMHz tuning failed for HS400\n", |
| 1925 | __func__, mmc->dev->name, slot->clock / 1000000); |
| 1926 | return -EINVAL; |
| 1927 | } |
| 1928 | tap = best_start + best_run / 2; |
| 1929 | |
| 1930 | snprintf(env_name, sizeof(env_name), "emmc%d_data_in_tap_adj_hs400", |
| 1931 | slot->bus_id); |
| 1932 | tap_adj = env_get_ulong(env_name, 10, slot->hs400_tap_adj); |
| 1933 | /* |
| 1934 | * Keep it in range and if out of range force it back in with a small |
| 1935 | * buffer. |
| 1936 | */ |
| 1937 | if (best_run > 3) { |
| 1938 | tap = tap + tap_adj; |
| 1939 | if (tap >= best_start + best_run) |
| 1940 | tap = best_start + best_run - 2; |
| 1941 | if (tap <= best_start) |
| 1942 | tap = best_start + 2; |
| 1943 | } |
| 1944 | how[tap] = '@'; |
| 1945 | debug("Tuning: %s\n", how); |
| 1946 | debug("%s(%s): HS400 tap: best run start: %d, length: %d, tap: %d\n", |
| 1947 | __func__, mmc->dev->name, best_start, best_run, tap); |
| 1948 | slot->hs400_taps = slot->hs200_taps; |
| 1949 | slot->hs400_taps.s.data_in_tap = tap; |
| 1950 | slot->hs400_tuned = true; |
| 1951 | if (env_get_yesno("emmc_export_hs400_taps") > 0) { |
| 1952 | debug("%s(%s): Exporting HS400 taps\n", |
| 1953 | __func__, mmc->dev->name); |
| 1954 | env_set_ulong("emmc_timing_tap", slot->host->timing_taps); |
| 1955 | snprintf(env_name, sizeof(env_name), |
| 1956 | "emmc%d_hs400_data_in_tap_debug", |
| 1957 | slot->bus_id); |
| 1958 | env_set(env_name, how); |
| 1959 | snprintf(env_name, sizeof(env_name), |
| 1960 | "emmc%d_hs400_data_in_tap_val", |
| 1961 | slot->bus_id); |
| 1962 | env_set_ulong(env_name, tap); |
| 1963 | snprintf(env_name, sizeof(env_name), |
| 1964 | "emmc%d_hs400_data_in_tap_start", |
| 1965 | slot->bus_id); |
| 1966 | env_set_ulong(env_name, best_start); |
| 1967 | snprintf(env_name, sizeof(env_name), |
| 1968 | "emmc%d_hs400_data_in_tap_end", |
| 1969 | slot->bus_id); |
| 1970 | env_set_ulong(env_name, best_start + best_run); |
| 1971 | snprintf(env_name, sizeof(env_name), |
| 1972 | "emmc%d_hs400_cmd_in_tap", |
| 1973 | slot->bus_id); |
| 1974 | env_set_ulong(env_name, slot->hs400_taps.s.cmd_in_tap); |
| 1975 | snprintf(env_name, sizeof(env_name), |
| 1976 | "emmc%d_hs400_cmd_out_tap", |
| 1977 | slot->bus_id); |
| 1978 | env_set_ulong(env_name, slot->hs400_taps.s.cmd_out_tap); |
| 1979 | snprintf(env_name, sizeof(env_name), |
| 1980 | "emmc%d_hs400_cmd_out_delay", |
| 1981 | slot->bus_id); |
| 1982 | env_set_ulong(env_name, slot->cmd_out_hs400_delay); |
| 1983 | snprintf(env_name, sizeof(env_name), |
| 1984 | "emmc%d_hs400_data_out_tap", |
| 1985 | slot->bus_id); |
| 1986 | env_set_ulong(env_name, slot->hs400_taps.s.data_out_tap); |
| 1987 | snprintf(env_name, sizeof(env_name), |
| 1988 | "emmc%d_hs400_data_out_delay", |
| 1989 | slot->bus_id); |
| 1990 | env_set_ulong(env_name, slot->data_out_hs400_delay); |
| 1991 | } else { |
| 1992 | debug("%s(%s): HS400 environment export disabled\n", |
| 1993 | __func__, mmc->dev->name); |
| 1994 | } |
| 1995 | octeontx_mmc_set_timing(mmc); |
| 1996 | |
| 1997 | return 0; |
| 1998 | } |
| 1999 | |
| 2000 | struct adj { |
| 2001 | const char *name; |
| 2002 | u8 mask_shift; |
| 2003 | int (*test)(struct mmc *mmc, u32 opcode, int *error); |
| 2004 | u32 opcode; |
| 2005 | bool ddr_only; |
| 2006 | bool hs200_only; |
| 2007 | bool not_hs200_only; |
| 2008 | u8 num_runs; |
| 2009 | }; |
| 2010 | |
| 2011 | struct adj adj[] = { |
| 2012 | { "CMD_IN", 48, octeontx_mmc_test_cmd, MMC_CMD_SEND_STATUS, |
| 2013 | false, false, false, 2, }, |
| 2014 | /* { "CMD_OUT", 32, octeontx_mmc_test_cmd, MMC_CMD_SEND_STATUS, },*/ |
Marek Vasut | dad81fb | 2024-02-20 09:36:23 +0100 | [diff] [blame] | 2015 | { "DATA_IN(HS200)", 16, octeontx_mmc_send_tuning, |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2016 | MMC_CMD_SEND_TUNING_BLOCK_HS200, false, true, false, 2, }, |
| 2017 | { "DATA_IN", 16, octeontx_mmc_test_get_ext_csd, 0, false, false, |
| 2018 | true, 2, }, |
| 2019 | /* { "DATA_OUT", 0, octeontx_mmc_test_cmd, 0, true, false},*/ |
| 2020 | { NULL, }, |
| 2021 | }; |
| 2022 | |
| 2023 | /** |
| 2024 | * Perform tuning tests to find optimal timing |
| 2025 | * |
| 2026 | * @param mmc mmc device |
| 2027 | * @param adj parameter to tune |
| 2028 | * @param opcode command opcode to use |
| 2029 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 2030 | * Return: 0 for success, -1 if tuning failed |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2031 | */ |
| 2032 | static int octeontx_mmc_adjust_tuning(struct mmc *mmc, struct adj *adj, |
| 2033 | u32 opcode) |
| 2034 | { |
| 2035 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 2036 | union mio_emm_timing timing; |
| 2037 | union mio_emm_debug emm_debug; |
| 2038 | int tap; |
| 2039 | int err = -1; |
| 2040 | int run = 0; |
| 2041 | int count; |
| 2042 | int start_run = -1; |
| 2043 | int best_run = 0; |
| 2044 | int best_start = -1; |
| 2045 | bool prev_ok = false; |
| 2046 | u64 tap_status = 0; |
| 2047 | const int tap_adj = slot->hs200_tap_adj; |
| 2048 | char how[MAX_NO_OF_TAPS + 1] = ""; |
| 2049 | bool is_hs200 = mmc->selected_mode == MMC_HS_200; |
| 2050 | |
| 2051 | debug("%s(%s, %s, %d), hs200: %d\n", __func__, mmc->dev->name, |
| 2052 | adj->name, opcode, is_hs200); |
| 2053 | octeontx_mmc_set_emm_timing(mmc, |
| 2054 | is_hs200 ? slot->hs200_taps : slot->taps); |
| 2055 | |
| 2056 | #ifdef DEBUG |
| 2057 | if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) { |
| 2058 | printf("%s(%s): Before tuning %s, opcode: %d\n", |
| 2059 | __func__, mmc->dev->name, adj->name, opcode); |
| 2060 | octeontx_mmc_print_registers2(mmc, NULL); |
| 2061 | } |
| 2062 | #endif |
| 2063 | |
| 2064 | /* |
| 2065 | * The algorithm to find the optimal timing is to start |
| 2066 | * at the end and work backwards and select the second |
| 2067 | * value that passes. Each test is repeated twice. |
| 2068 | */ |
| 2069 | for (tap = 0; tap <= MAX_NO_OF_TAPS; tap++, prev_ok = !err) { |
| 2070 | if (tap < MAX_NO_OF_TAPS) { |
| 2071 | if (slot->host->tap_requires_noclk) { |
| 2072 | /* Turn off the clock */ |
| 2073 | emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG()); |
| 2074 | emm_debug.s.emmc_clk_disable = 1; |
| 2075 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 2076 | udelay(1); |
| 2077 | emm_debug.s.rdsync_rst = 1; |
| 2078 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 2079 | udelay(1); |
| 2080 | } |
| 2081 | |
| 2082 | timing.u = read_csr(mmc, MIO_EMM_TIMING()); |
| 2083 | timing.u &= ~(0x3full << adj->mask_shift); |
| 2084 | timing.u |= (u64)tap << adj->mask_shift; |
| 2085 | write_csr(mmc, MIO_EMM_TIMING(), timing.u); |
| 2086 | debug("%s(%s): Testing ci: %d, co: %d, di: %d, do: %d\n", |
| 2087 | __func__, mmc->dev->name, timing.s.cmd_in_tap, |
| 2088 | timing.s.cmd_out_tap, timing.s.data_in_tap, |
| 2089 | timing.s.data_out_tap); |
| 2090 | |
| 2091 | if (slot->host->tap_requires_noclk) { |
| 2092 | /* Turn off the clock */ |
| 2093 | emm_debug.s.rdsync_rst = 0; |
| 2094 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 2095 | udelay(1); |
| 2096 | emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG()); |
| 2097 | emm_debug.s.emmc_clk_disable = 0; |
| 2098 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 2099 | udelay(1); |
| 2100 | } |
| 2101 | for (count = 0; count < 2; count++) { |
| 2102 | err = adj->test(mmc, opcode, NULL); |
| 2103 | if (err) { |
| 2104 | debug("%s(%s, %s): tap %d failed, count: %d, rsp_sts: 0x%llx, rsp_lo: 0x%llx\n", |
| 2105 | __func__, mmc->dev->name, |
| 2106 | adj->name, tap, count, |
| 2107 | read_csr(mmc, |
| 2108 | MIO_EMM_RSP_STS()), |
| 2109 | read_csr(mmc, |
| 2110 | MIO_EMM_RSP_LO())); |
| 2111 | debug("%s(%s, %s): tap: %d, do: %d, di: %d, co: %d, ci: %d\n", |
| 2112 | __func__, mmc->dev->name, |
| 2113 | adj->name, tap, |
| 2114 | timing.s.data_out_tap, |
| 2115 | timing.s.data_in_tap, |
| 2116 | timing.s.cmd_out_tap, |
| 2117 | timing.s.cmd_in_tap); |
| 2118 | break; |
| 2119 | } |
| 2120 | debug("%s(%s, %s): tap %d passed, count: %d, rsp_sts: 0x%llx, rsp_lo: 0x%llx\n", |
| 2121 | __func__, mmc->dev->name, adj->name, tap, |
| 2122 | count, |
| 2123 | read_csr(mmc, MIO_EMM_RSP_STS()), |
| 2124 | read_csr(mmc, MIO_EMM_RSP_LO())); |
| 2125 | } |
| 2126 | tap_status |= (u64)(!err) << tap; |
| 2127 | how[tap] = "-+"[!err]; |
| 2128 | } else { |
| 2129 | /* |
| 2130 | * Putting the end+1 case in the loop simplifies |
| 2131 | * logic, allowing 'prev_ok' to process a sweet |
| 2132 | * spot in tuning which extends to the wall. |
| 2133 | */ |
| 2134 | err = -EINVAL; |
| 2135 | } |
| 2136 | if (!err) { |
| 2137 | /* |
| 2138 | * If no CRC/etc errors in the response, but previous |
| 2139 | * failed, note the start of a new run. |
| 2140 | */ |
| 2141 | debug(" prev_ok: %d\n", prev_ok); |
| 2142 | if (!prev_ok) |
| 2143 | start_run = tap; |
| 2144 | } else if (prev_ok) { |
| 2145 | run = tap - 1 - start_run; |
| 2146 | /* did we just exit a wider sweet spot? */ |
| 2147 | if (start_run >= 0 && run > best_run) { |
| 2148 | best_start = start_run; |
| 2149 | best_run = run; |
| 2150 | } |
| 2151 | } |
| 2152 | } |
| 2153 | how[tap - 1] = '\0'; |
| 2154 | if (best_start < 0) { |
| 2155 | printf("%s(%s, %s): %lldMHz tuning %s failed\n", __func__, |
| 2156 | mmc->dev->name, adj->name, slot->clock / 1000000, |
| 2157 | adj->name); |
| 2158 | return -EINVAL; |
| 2159 | } |
| 2160 | |
| 2161 | tap = best_start + best_run / 2; |
| 2162 | debug(" tap %d is center, start: %d, run: %d\n", tap, |
| 2163 | best_start, best_run); |
| 2164 | if (is_hs200) { |
| 2165 | slot->hs200_taps.u &= ~(0x3full << adj->mask_shift); |
| 2166 | slot->hs200_taps.u |= (u64)tap << adj->mask_shift; |
| 2167 | } else { |
| 2168 | slot->taps.u &= ~(0x3full << adj->mask_shift); |
| 2169 | slot->taps.u |= (u64)tap << adj->mask_shift; |
| 2170 | } |
| 2171 | if (best_start < 0) { |
| 2172 | printf("%s(%s, %s): %lldMHz tuning %s failed\n", __func__, |
| 2173 | mmc->dev->name, adj->name, slot->clock / 1000000, |
| 2174 | adj->name); |
| 2175 | return -EINVAL; |
| 2176 | } |
| 2177 | |
| 2178 | tap = best_start + best_run / 2; |
| 2179 | if (is_hs200 && (tap + tap_adj >= 0) && (tap + tap_adj < 64) && |
| 2180 | tap_status & (1ULL << (tap + tap_adj))) { |
| 2181 | debug("Adjusting tap from %d by %d to %d\n", |
| 2182 | tap, tap_adj, tap + tap_adj); |
| 2183 | tap += tap_adj; |
| 2184 | } |
| 2185 | how[tap] = '@'; |
| 2186 | debug("%s/%s %d/%d/%d %s\n", mmc->dev->name, |
| 2187 | adj->name, best_start, tap, best_start + best_run, how); |
| 2188 | |
| 2189 | if (is_hs200) { |
| 2190 | slot->hs200_taps.u &= ~(0x3full << adj->mask_shift); |
| 2191 | slot->hs200_taps.u |= (u64)tap << adj->mask_shift; |
| 2192 | } else { |
| 2193 | slot->taps.u &= ~(0x3full << adj->mask_shift); |
| 2194 | slot->taps.u |= (u64)tap << adj->mask_shift; |
| 2195 | } |
| 2196 | |
| 2197 | #ifdef DEBUG |
| 2198 | if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) { |
| 2199 | debug("%s(%s, %s): After successful tuning\n", |
| 2200 | __func__, mmc->dev->name, adj->name); |
| 2201 | debug("%s(%s, %s): tap: %d, new do: %d, di: %d, co: %d, ci: %d\n", |
| 2202 | __func__, mmc->dev->name, adj->name, tap, |
| 2203 | slot->taps.s.data_out_tap, |
| 2204 | slot->taps.s.data_in_tap, |
| 2205 | slot->taps.s.cmd_out_tap, |
| 2206 | slot->taps.s.cmd_in_tap); |
| 2207 | debug("%s(%s, %s): tap: %d, new do HS200: %d, di: %d, co: %d, ci: %d\n", |
| 2208 | __func__, mmc->dev->name, adj->name, tap, |
| 2209 | slot->hs200_taps.s.data_out_tap, |
| 2210 | slot->hs200_taps.s.data_in_tap, |
| 2211 | slot->hs200_taps.s.cmd_out_tap, |
| 2212 | slot->hs200_taps.s.cmd_in_tap); |
| 2213 | } |
| 2214 | #endif |
| 2215 | octeontx_mmc_set_timing(mmc); |
| 2216 | |
| 2217 | if (is_hs200 && env_get_yesno("emmc_export_hs200_taps")) { |
| 2218 | char env_name[64]; |
| 2219 | |
| 2220 | env_set_ulong("emmc_timing_tap", slot->host->timing_taps); |
| 2221 | switch (opcode) { |
| 2222 | case MMC_CMD_SEND_TUNING_BLOCK: |
| 2223 | snprintf(env_name, sizeof(env_name), |
| 2224 | "emmc%d_hs200_data_in_tap_debug", |
| 2225 | slot->bus_id); |
| 2226 | env_set(env_name, how); |
| 2227 | snprintf(env_name, sizeof(env_name), |
| 2228 | "emmc%d_hs200_data_in_tap_val", slot->bus_id); |
| 2229 | env_set_ulong(env_name, tap); |
| 2230 | snprintf(env_name, sizeof(env_name), |
| 2231 | "emmc%d_hs200_data_in_tap_start", |
| 2232 | slot->bus_id); |
| 2233 | env_set_ulong(env_name, best_start); |
| 2234 | snprintf(env_name, sizeof(env_name), |
| 2235 | "emmc%d_hs200_data_in_tap_end", |
| 2236 | slot->bus_id); |
| 2237 | env_set_ulong(env_name, best_start + best_run); |
| 2238 | break; |
| 2239 | case MMC_CMD_SEND_STATUS: |
| 2240 | snprintf(env_name, sizeof(env_name), |
| 2241 | "emmc%d_hs200_cmd_in_tap_debug", |
| 2242 | slot->bus_id); |
| 2243 | env_set(env_name, how); |
| 2244 | snprintf(env_name, sizeof(env_name), |
| 2245 | "emmc%d_hs200_cmd_in_tap_val", slot->bus_id); |
| 2246 | env_set_ulong(env_name, tap); |
| 2247 | snprintf(env_name, sizeof(env_name), |
| 2248 | "emmc%d_hs200_cmd_in_tap_start", |
| 2249 | slot->bus_id); |
| 2250 | env_set_ulong(env_name, best_start); |
| 2251 | snprintf(env_name, sizeof(env_name), |
| 2252 | "emmc%d_hs200_cmd_in_tap_end", |
| 2253 | slot->bus_id); |
| 2254 | env_set_ulong(env_name, best_start + best_run); |
| 2255 | break; |
| 2256 | default: |
| 2257 | snprintf(env_name, sizeof(env_name), |
| 2258 | "emmc%d_hs200_data_out_tap", slot->bus_id); |
| 2259 | env_set_ulong(env_name, slot->data_out_hs200_delay); |
| 2260 | snprintf(env_name, sizeof(env_name), |
| 2261 | "emmc%d_hs200_cmd_out_tap", slot->bus_id); |
| 2262 | env_set_ulong(env_name, slot->cmd_out_hs200_delay); |
| 2263 | break; |
| 2264 | } |
| 2265 | } |
| 2266 | |
| 2267 | return 0; |
| 2268 | } |
| 2269 | |
| 2270 | static int octeontx_mmc_execute_tuning(struct udevice *dev, u32 opcode) |
| 2271 | { |
| 2272 | struct mmc *mmc = dev_to_mmc(dev); |
| 2273 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 2274 | union mio_emm_timing emm_timing; |
| 2275 | int err; |
| 2276 | struct adj *a; |
| 2277 | bool is_hs200; |
| 2278 | char env_name[64]; |
| 2279 | |
| 2280 | pr_info("%s re-tuning, opcode 0x%x\n", dev->name, opcode); |
| 2281 | |
| 2282 | if (slot->is_asim || slot->is_emul) |
| 2283 | return 0; |
| 2284 | |
| 2285 | is_hs200 = (mmc->selected_mode == MMC_HS_200); |
| 2286 | if (is_hs200) { |
| 2287 | slot->hs200_tuned = false; |
| 2288 | slot->hs400_tuned = false; |
| 2289 | } else { |
| 2290 | slot->tuned = false; |
| 2291 | } |
| 2292 | octeontx_mmc_set_output_bus_timing(mmc); |
| 2293 | octeontx_mmc_set_input_bus_timing(mmc); |
| 2294 | emm_timing.u = read_csr(mmc, MIO_EMM_TIMING()); |
| 2295 | if (mmc->selected_mode == MMC_HS_200) { |
| 2296 | slot->hs200_taps.s.cmd_out_tap = emm_timing.s.cmd_out_tap; |
| 2297 | slot->hs200_taps.s.data_out_tap = emm_timing.s.data_out_tap; |
| 2298 | } else { |
| 2299 | slot->taps.s.cmd_out_tap = emm_timing.s.cmd_out_tap; |
| 2300 | slot->taps.s.data_out_tap = emm_timing.s.data_out_tap; |
| 2301 | } |
| 2302 | octeontx_mmc_set_input_bus_timing(mmc); |
| 2303 | octeontx_mmc_set_output_bus_timing(mmc); |
| 2304 | |
| 2305 | for (a = adj; a->name; a++) { |
| 2306 | ulong in_tap; |
| 2307 | |
| 2308 | if (!strcmp(a->name, "CMD_IN")) { |
| 2309 | snprintf(env_name, sizeof(env_name), |
| 2310 | "emmc%d_cmd_in_tap", slot->bus_id); |
| 2311 | in_tap = env_get_ulong(env_name, 10, (ulong)-1); |
| 2312 | if (in_tap != (ulong)-1) { |
| 2313 | if (mmc->selected_mode == MMC_HS_200 || |
| 2314 | a->hs200_only) { |
| 2315 | slot->hs200_taps.s.cmd_in_tap = in_tap; |
| 2316 | slot->hs400_taps.s.cmd_in_tap = in_tap; |
| 2317 | } else { |
| 2318 | slot->taps.s.cmd_in_tap = in_tap; |
| 2319 | } |
| 2320 | continue; |
| 2321 | } |
| 2322 | } else if (a->hs200_only && |
| 2323 | !strcmp(a->name, "DATA_IN(HS200)")) { |
| 2324 | snprintf(env_name, sizeof(env_name), |
| 2325 | "emmc%d_data_in_tap_hs200", slot->bus_id); |
| 2326 | in_tap = env_get_ulong(env_name, 10, (ulong)-1); |
| 2327 | if (in_tap != (ulong)-1) { |
| 2328 | debug("%s(%s): Overriding HS200 data in tap to %d\n", |
| 2329 | __func__, dev->name, (int)in_tap); |
| 2330 | slot->hs200_taps.s.data_in_tap = in_tap; |
| 2331 | continue; |
| 2332 | } |
| 2333 | } else if (!a->hs200_only && !strcmp(a->name, "DATA_IN")) { |
| 2334 | snprintf(env_name, sizeof(env_name), |
| 2335 | "emmc%d_data_in_tap", slot->bus_id); |
| 2336 | in_tap = env_get_ulong(env_name, 10, (ulong)-1); |
| 2337 | if (in_tap != (ulong)-1) { |
| 2338 | debug("%s(%s): Overriding non-HS200 data in tap to %d\n", |
| 2339 | __func__, dev->name, (int)in_tap); |
| 2340 | slot->taps.s.data_in_tap = in_tap; |
| 2341 | continue; |
| 2342 | } |
| 2343 | } |
| 2344 | |
| 2345 | debug("%s(%s): Testing: %s, mode: %s, opcode: %u\n", __func__, |
| 2346 | dev->name, a->name, mmc_mode_name(mmc->selected_mode), |
| 2347 | opcode); |
| 2348 | |
| 2349 | /* Skip DDR only test when not in DDR mode */ |
| 2350 | if (a->ddr_only && !mmc->ddr_mode) { |
| 2351 | debug("%s(%s): Skipping %s due to non-DDR mode\n", |
| 2352 | __func__, dev->name, a->name); |
| 2353 | continue; |
| 2354 | } |
| 2355 | /* Skip hs200 tests in non-hs200 mode and |
| 2356 | * non-hs200 tests in hs200 mode |
| 2357 | */ |
| 2358 | if (is_hs200) { |
| 2359 | if (a->not_hs200_only) { |
| 2360 | debug("%s(%s): Skipping %s\n", __func__, |
| 2361 | dev->name, a->name); |
| 2362 | continue; |
| 2363 | } |
| 2364 | } else { |
| 2365 | if (a->hs200_only) { |
| 2366 | debug("%s(%s): Skipping %s\n", __func__, |
| 2367 | dev->name, a->name); |
| 2368 | continue; |
| 2369 | } |
| 2370 | } |
| 2371 | |
| 2372 | err = octeontx_mmc_adjust_tuning(mmc, a, a->opcode ? |
| 2373 | a->opcode : opcode); |
| 2374 | if (err) { |
| 2375 | pr_err("%s(%s, %u): tuning %s failed\n", __func__, |
| 2376 | dev->name, opcode, a->name); |
| 2377 | return err; |
| 2378 | } |
| 2379 | } |
| 2380 | |
| 2381 | octeontx_mmc_set_timing(mmc); |
| 2382 | if (is_hs200) |
| 2383 | slot->hs200_tuned = true; |
| 2384 | else |
| 2385 | slot->tuned = true; |
| 2386 | |
| 2387 | if (slot->hs400_tuning_block != -1) { |
| 2388 | struct mmc_cmd cmd; |
| 2389 | struct mmc_data data; |
| 2390 | u8 buffer[mmc->read_bl_len]; |
| 2391 | |
| 2392 | cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; |
| 2393 | cmd.cmdarg = slot->hs400_tuning_block; |
| 2394 | cmd.resp_type = MMC_RSP_R1; |
| 2395 | data.dest = (void *)buffer; |
| 2396 | data.blocks = 1; |
| 2397 | data.blocksize = mmc->read_bl_len; |
| 2398 | data.flags = MMC_DATA_READ; |
| 2399 | err = octeontx_mmc_read_blocks(mmc, &cmd, &data, true) != 1; |
| 2400 | |
| 2401 | if (err) { |
| 2402 | printf("%s: Cannot read HS400 tuning block %u\n", |
| 2403 | dev->name, slot->hs400_tuning_block); |
| 2404 | return err; |
| 2405 | } |
| 2406 | if (memcmp(buffer, octeontx_hs400_tuning_block, |
| 2407 | sizeof(buffer))) { |
| 2408 | debug("%s(%s): Writing new HS400 tuning block to block %d\n", |
| 2409 | __func__, dev->name, slot->hs400_tuning_block); |
| 2410 | cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK; |
| 2411 | data.src = (void *)octeontx_hs400_tuning_block; |
| 2412 | data.flags = MMC_DATA_WRITE; |
| 2413 | err = !octeontx_mmc_write_blocks(mmc, &cmd, &data); |
| 2414 | if (err) { |
| 2415 | printf("%s: Cannot write HS400 tuning block %u\n", |
| 2416 | dev->name, slot->hs400_tuning_block); |
| 2417 | return -EINVAL; |
| 2418 | } |
| 2419 | } |
| 2420 | } |
| 2421 | |
| 2422 | return 0; |
| 2423 | } |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 2424 | #else /* CONFIG_MMC_SUPPORTS_TUNING */ |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2425 | static void octeontx_mmc_set_emm_timing(struct mmc *mmc, |
| 2426 | union mio_emm_timing emm_timing) |
| 2427 | { |
| 2428 | } |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 2429 | #endif /* CONFIG_MMC_SUPPORTS_TUNING */ |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2430 | |
| 2431 | /** |
| 2432 | * Calculate the clock period with rounding up |
| 2433 | * |
| 2434 | * @param mmc mmc device |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 2435 | * Return: clock period in system clocks for clk_lo + clk_hi |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2436 | */ |
| 2437 | static u32 octeontx_mmc_calc_clk_period(struct mmc *mmc) |
| 2438 | { |
| 2439 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 2440 | struct octeontx_mmc_host *host = slot->host; |
| 2441 | |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2442 | if (mmc->clock) |
| 2443 | return DIV_ROUND_UP(host->sys_freq, mmc->clock); |
| 2444 | |
| 2445 | return 0; |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2446 | } |
| 2447 | |
| 2448 | static int octeontx_mmc_set_ios(struct udevice *dev) |
| 2449 | { |
| 2450 | struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev); |
| 2451 | struct mmc *mmc = &slot->mmc; |
| 2452 | struct octeontx_mmc_host *host = slot->host; |
| 2453 | union mio_emm_switch emm_switch; |
| 2454 | union mio_emm_modex mode; |
| 2455 | uint clock; |
| 2456 | int bus_width = 0; |
| 2457 | int clk_period = 0; |
| 2458 | int power_class = 10; |
| 2459 | int err = 0; |
| 2460 | bool is_hs200 = false; |
| 2461 | bool is_hs400 = false; |
| 2462 | |
| 2463 | debug("%s(%s): Entry\n", __func__, dev->name); |
| 2464 | debug(" clock: %u, bus width: %u, mode: %u\n", mmc->clock, |
| 2465 | mmc->bus_width, mmc->selected_mode); |
| 2466 | debug(" host caps: 0x%x, card caps: 0x%x\n", mmc->host_caps, |
| 2467 | mmc->card_caps); |
| 2468 | octeontx_mmc_switch_to(mmc); |
| 2469 | |
| 2470 | clock = mmc->clock; |
| 2471 | if (!clock) |
| 2472 | clock = mmc->cfg->f_min; |
| 2473 | |
| 2474 | switch (mmc->bus_width) { |
| 2475 | case 8: |
| 2476 | bus_width = 2; |
| 2477 | break; |
| 2478 | case 4: |
| 2479 | bus_width = 1; |
| 2480 | break; |
| 2481 | case 1: |
| 2482 | bus_width = 0; |
| 2483 | break; |
| 2484 | default: |
| 2485 | pr_warn("%s(%s): Invalid bus width %d, defaulting to 1\n", |
| 2486 | __func__, dev->name, mmc->bus_width); |
| 2487 | bus_width = 0; |
| 2488 | } |
| 2489 | |
| 2490 | /* DDR is available for 4/8 bit bus width */ |
| 2491 | if (mmc->ddr_mode && bus_width) |
| 2492 | bus_width |= 4; |
| 2493 | |
| 2494 | debug("%s: sys_freq: %llu\n", __func__, host->sys_freq); |
| 2495 | clk_period = octeontx_mmc_calc_clk_period(mmc); |
| 2496 | |
| 2497 | emm_switch.u = 0; |
| 2498 | emm_switch.s.bus_width = bus_width; |
| 2499 | emm_switch.s.power_class = power_class; |
| 2500 | emm_switch.s.clk_hi = clk_period / 2; |
| 2501 | emm_switch.s.clk_lo = clk_period / 2; |
| 2502 | |
| 2503 | debug("%s: last mode: %d, mode: %d, last clock: %u, clock: %u, ddr: %d\n", |
| 2504 | __func__, slot->last_mode, mmc->selected_mode, |
| 2505 | slot->last_clock, mmc->clock, mmc->ddr_mode); |
| 2506 | switch (mmc->selected_mode) { |
| 2507 | case MMC_LEGACY: |
| 2508 | break; |
| 2509 | case MMC_HS: |
| 2510 | case SD_HS: |
| 2511 | case MMC_HS_52: |
| 2512 | emm_switch.s.hs_timing = 1; |
| 2513 | break; |
| 2514 | case MMC_HS_200: |
| 2515 | is_hs200 = true; |
| 2516 | fallthrough; |
| 2517 | case UHS_SDR12: |
| 2518 | case UHS_SDR25: |
| 2519 | case UHS_SDR50: |
| 2520 | case UHS_SDR104: |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2521 | #if !defined(CONFIG_ARCH_OCTEON) |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2522 | emm_switch.s.hs200_timing = 1; |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2523 | #endif |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2524 | break; |
| 2525 | case MMC_HS_400: |
| 2526 | is_hs400 = true; |
| 2527 | fallthrough; |
| 2528 | case UHS_DDR50: |
| 2529 | case MMC_DDR_52: |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2530 | #if !defined(CONFIG_ARCH_OCTEON) |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2531 | emm_switch.s.hs400_timing = 1; |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2532 | #endif |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2533 | break; |
| 2534 | default: |
| 2535 | pr_err("%s(%s): Unsupported mode 0x%x\n", __func__, dev->name, |
| 2536 | mmc->selected_mode); |
| 2537 | return -1; |
| 2538 | } |
| 2539 | emm_switch.s.bus_id = slot->bus_id; |
| 2540 | |
| 2541 | if (!is_hs200 && !is_hs400 && |
| 2542 | (mmc->selected_mode != slot->last_mode || |
| 2543 | mmc->clock != slot->last_clock) && |
| 2544 | !mmc->ddr_mode) { |
| 2545 | slot->tuned = false; |
| 2546 | slot->last_mode = mmc->selected_mode; |
| 2547 | slot->last_clock = mmc->clock; |
| 2548 | } |
| 2549 | |
| 2550 | if (CONFIG_IS_ENABLED(MMC_VERBOSE)) { |
| 2551 | debug("%s(%s): Setting bus mode to %s\n", __func__, dev->name, |
| 2552 | mmc_mode_name(mmc->selected_mode)); |
| 2553 | } else { |
| 2554 | debug("%s(%s): Setting bus mode to 0x%x\n", __func__, dev->name, |
| 2555 | mmc->selected_mode); |
| 2556 | } |
| 2557 | |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2558 | #if !defined(CONFIG_ARCH_OCTEON) |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2559 | debug(" Trying switch 0x%llx w%d hs:%d hs200:%d hs400:%d\n", |
| 2560 | emm_switch.u, emm_switch.s.bus_width, emm_switch.s.hs_timing, |
| 2561 | emm_switch.s.hs200_timing, emm_switch.s.hs400_timing); |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2562 | #endif |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2563 | |
| 2564 | set_wdog(mmc, 1000); |
| 2565 | do_switch(mmc, emm_switch); |
| 2566 | mdelay(100); |
| 2567 | mode.u = read_csr(mmc, MIO_EMM_MODEX(slot->bus_id)); |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2568 | #if !defined(CONFIG_ARCH_OCTEON) |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2569 | debug("%s(%s): mode: 0x%llx w:%d, hs:%d, hs200:%d, hs400:%d\n", |
| 2570 | __func__, dev->name, mode.u, mode.s.bus_width, |
| 2571 | mode.s.hs_timing, mode.s.hs200_timing, mode.s.hs400_timing); |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2572 | #endif |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2573 | |
| 2574 | err = octeontx_mmc_configure_delay(mmc); |
| 2575 | |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 2576 | #if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2577 | if (!err && mmc->selected_mode == MMC_HS_400 && !slot->hs400_tuned) { |
| 2578 | debug("%s: Tuning HS400 mode\n", __func__); |
| 2579 | err = octeontx_tune_hs400(mmc); |
| 2580 | } |
| 2581 | #endif |
| 2582 | |
| 2583 | return err; |
| 2584 | } |
| 2585 | |
| 2586 | /** |
| 2587 | * Gets the status of the card detect pin |
| 2588 | */ |
| 2589 | static int octeontx_mmc_get_cd(struct udevice *dev) |
| 2590 | { |
| 2591 | struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev); |
| 2592 | int val = 1; |
| 2593 | |
| 2594 | if (dm_gpio_is_valid(&slot->cd_gpio)) { |
| 2595 | val = dm_gpio_get_value(&slot->cd_gpio); |
| 2596 | val ^= slot->cd_inverted; |
| 2597 | } |
| 2598 | debug("%s(%s): cd: %d\n", __func__, dev->name, val); |
| 2599 | return val; |
| 2600 | } |
| 2601 | |
| 2602 | /** |
| 2603 | * Gets the status of the write protect pin |
| 2604 | */ |
| 2605 | static int octeontx_mmc_get_wp(struct udevice *dev) |
| 2606 | { |
| 2607 | struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev); |
| 2608 | int val = 0; |
| 2609 | |
| 2610 | if (dm_gpio_is_valid(&slot->wp_gpio)) { |
| 2611 | val = dm_gpio_get_value(&slot->wp_gpio); |
| 2612 | val ^= slot->wp_inverted; |
| 2613 | } |
| 2614 | debug("%s(%s): wp: %d\n", __func__, dev->name, val); |
| 2615 | return val; |
| 2616 | } |
| 2617 | |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2618 | #if defined(CONFIG_ARCH_OCTEON) |
| 2619 | static int octeontx_mmc_configure_delay(struct mmc *mmc) |
| 2620 | { |
| 2621 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 2622 | union mio_emm_sample emm_sample; |
| 2623 | |
| 2624 | debug("%s(%s)\n", __func__, mmc->dev->name); |
| 2625 | |
| 2626 | emm_sample.u = 0; |
| 2627 | emm_sample.s.cmd_cnt = slot->cmd_cnt; |
| 2628 | emm_sample.s.dat_cnt = slot->dat_cnt; |
| 2629 | write_csr(mmc, MIO_EMM_SAMPLE(), emm_sample.u); |
| 2630 | |
| 2631 | return 0; |
| 2632 | } |
| 2633 | |
| 2634 | static void octeontx_mmc_io_drive_setup(struct mmc *mmc) |
| 2635 | { |
| 2636 | } |
| 2637 | #else |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2638 | static void octeontx_mmc_set_timing(struct mmc *mmc) |
| 2639 | { |
| 2640 | union mio_emm_timing timing; |
| 2641 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 2642 | |
| 2643 | switch (mmc->selected_mode) { |
| 2644 | case MMC_HS_200: |
| 2645 | timing = slot->hs200_taps; |
| 2646 | break; |
| 2647 | case MMC_HS_400: |
| 2648 | timing = slot->hs400_tuned ? |
| 2649 | slot->hs400_taps : slot->hs200_taps; |
| 2650 | break; |
| 2651 | default: |
| 2652 | timing = slot->taps; |
| 2653 | break; |
| 2654 | } |
| 2655 | |
| 2656 | debug("%s(%s):\n cmd_in_tap: %u\n cmd_out_tap: %u\n data_in_tap: %u\n data_out_tap: %u\n", |
| 2657 | __func__, mmc->dev->name, timing.s.cmd_in_tap, |
| 2658 | timing.s.cmd_out_tap, timing.s.data_in_tap, |
| 2659 | timing.s.data_out_tap); |
| 2660 | |
| 2661 | octeontx_mmc_set_emm_timing(mmc, timing); |
| 2662 | } |
| 2663 | |
| 2664 | static int octeontx_mmc_configure_delay(struct mmc *mmc) |
| 2665 | { |
| 2666 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 2667 | struct octeontx_mmc_host *host __maybe_unused = slot->host; |
| 2668 | bool __maybe_unused is_hs200; |
| 2669 | bool __maybe_unused is_hs400; |
| 2670 | |
| 2671 | debug("%s(%s)\n", __func__, mmc->dev->name); |
| 2672 | |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2673 | if (IS_ENABLED(CONFIG_ARCH_OCTEON) || |
| 2674 | IS_ENABLED(CONFIG_ARCH_OCTEONTX)) { |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2675 | union mio_emm_sample emm_sample; |
| 2676 | |
| 2677 | emm_sample.u = 0; |
| 2678 | emm_sample.s.cmd_cnt = slot->cmd_cnt; |
| 2679 | emm_sample.s.dat_cnt = slot->dat_cnt; |
| 2680 | write_csr(mmc, MIO_EMM_SAMPLE(), emm_sample.u); |
| 2681 | } else { |
| 2682 | is_hs200 = (mmc->selected_mode == MMC_HS_200); |
| 2683 | is_hs400 = (mmc->selected_mode == MMC_HS_400); |
| 2684 | |
| 2685 | if ((is_hs200 && slot->hs200_tuned) || |
| 2686 | (is_hs400 && slot->hs400_tuned) || |
| 2687 | (!is_hs200 && !is_hs400 && slot->tuned)) { |
| 2688 | octeontx_mmc_set_output_bus_timing(mmc); |
| 2689 | } else { |
| 2690 | int half = MAX_NO_OF_TAPS / 2; |
| 2691 | int dout, cout; |
| 2692 | |
| 2693 | switch (mmc->selected_mode) { |
| 2694 | case MMC_LEGACY: |
| 2695 | if (IS_SD(mmc)) { |
| 2696 | cout = MMC_SD_LEGACY_DEFAULT_CMD_OUT_TAP; |
| 2697 | dout = MMC_SD_LEGACY_DEFAULT_DATA_OUT_TAP; |
| 2698 | } else { |
| 2699 | cout = MMC_LEGACY_DEFAULT_CMD_OUT_TAP; |
| 2700 | dout = MMC_LEGACY_DEFAULT_DATA_OUT_TAP; |
| 2701 | } |
| 2702 | break; |
| 2703 | case MMC_HS: |
| 2704 | cout = MMC_HS_CMD_OUT_TAP; |
| 2705 | dout = MMC_HS_DATA_OUT_TAP; |
| 2706 | break; |
| 2707 | case SD_HS: |
| 2708 | case UHS_SDR12: |
| 2709 | case UHS_SDR25: |
| 2710 | case UHS_SDR50: |
| 2711 | cout = MMC_SD_HS_CMD_OUT_TAP; |
| 2712 | dout = MMC_SD_HS_DATA_OUT_TAP; |
| 2713 | break; |
| 2714 | case UHS_SDR104: |
| 2715 | case UHS_DDR50: |
| 2716 | case MMC_HS_52: |
| 2717 | case MMC_DDR_52: |
| 2718 | cout = MMC_DEFAULT_CMD_OUT_TAP; |
| 2719 | dout = MMC_DEFAULT_DATA_OUT_TAP; |
| 2720 | break; |
| 2721 | case MMC_HS_200: |
| 2722 | cout = -1; |
| 2723 | dout = -1; |
| 2724 | if (host->timing_calibrated) { |
| 2725 | cout = octeontx2_mmc_calc_delay( |
| 2726 | mmc, slot->cmd_out_hs200_delay); |
| 2727 | dout = octeontx2_mmc_calc_delay( |
| 2728 | mmc, |
| 2729 | slot->data_out_hs200_delay); |
| 2730 | debug("%s(%s): Calibrated HS200/HS400 cmd out delay: %dps tap: %d, data out delay: %d, tap: %d\n", |
| 2731 | __func__, mmc->dev->name, |
| 2732 | slot->cmd_out_hs200_delay, cout, |
| 2733 | slot->data_out_hs200_delay, dout); |
| 2734 | } else { |
| 2735 | cout = MMC_DEFAULT_HS200_CMD_OUT_TAP; |
| 2736 | dout = MMC_DEFAULT_HS200_DATA_OUT_TAP; |
| 2737 | } |
| 2738 | is_hs200 = true; |
| 2739 | break; |
| 2740 | case MMC_HS_400: |
| 2741 | cout = -1; |
| 2742 | dout = -1; |
| 2743 | if (host->timing_calibrated) { |
| 2744 | if (slot->cmd_out_hs400_delay) |
| 2745 | cout = octeontx2_mmc_calc_delay( |
| 2746 | mmc, |
| 2747 | slot->cmd_out_hs400_delay); |
| 2748 | if (slot->data_out_hs400_delay) |
| 2749 | dout = octeontx2_mmc_calc_delay( |
| 2750 | mmc, |
| 2751 | slot->data_out_hs400_delay); |
| 2752 | debug("%s(%s): Calibrated HS200/HS400 cmd out delay: %dps tap: %d, data out delay: %d, tap: %d\n", |
| 2753 | __func__, mmc->dev->name, |
| 2754 | slot->cmd_out_hs400_delay, cout, |
| 2755 | slot->data_out_hs400_delay, dout); |
| 2756 | } else { |
| 2757 | cout = MMC_DEFAULT_HS400_CMD_OUT_TAP; |
| 2758 | dout = MMC_DEFAULT_HS400_DATA_OUT_TAP; |
| 2759 | } |
| 2760 | is_hs400 = true; |
| 2761 | break; |
| 2762 | default: |
| 2763 | pr_err("%s(%s): Invalid mode %d\n", __func__, |
| 2764 | mmc->dev->name, mmc->selected_mode); |
| 2765 | return -1; |
| 2766 | } |
| 2767 | debug("%s(%s): Not tuned, hs200: %d, hs200 tuned: %d, hs400: %d, hs400 tuned: %d, tuned: %d\n", |
| 2768 | __func__, mmc->dev->name, is_hs200, |
| 2769 | slot->hs200_tuned, |
| 2770 | is_hs400, slot->hs400_tuned, slot->tuned); |
| 2771 | /* Set some defaults */ |
| 2772 | if (is_hs200) { |
| 2773 | slot->hs200_taps.u = 0; |
| 2774 | slot->hs200_taps.s.cmd_out_tap = cout; |
| 2775 | slot->hs200_taps.s.data_out_tap = dout; |
| 2776 | slot->hs200_taps.s.cmd_in_tap = half; |
| 2777 | slot->hs200_taps.s.data_in_tap = half; |
| 2778 | } else if (is_hs400) { |
| 2779 | slot->hs400_taps.u = 0; |
| 2780 | slot->hs400_taps.s.cmd_out_tap = cout; |
| 2781 | slot->hs400_taps.s.data_out_tap = dout; |
| 2782 | slot->hs400_taps.s.cmd_in_tap = half; |
| 2783 | slot->hs400_taps.s.data_in_tap = half; |
| 2784 | } else { |
| 2785 | slot->taps.u = 0; |
| 2786 | slot->taps.s.cmd_out_tap = cout; |
| 2787 | slot->taps.s.data_out_tap = dout; |
| 2788 | slot->taps.s.cmd_in_tap = half; |
| 2789 | slot->taps.s.data_in_tap = half; |
| 2790 | } |
| 2791 | } |
| 2792 | |
| 2793 | if (is_hs200) |
| 2794 | debug("%s(%s): hs200 taps: ci: %u, co: %u, di: %u, do: %u\n", |
| 2795 | __func__, mmc->dev->name, |
| 2796 | slot->hs200_taps.s.cmd_in_tap, |
| 2797 | slot->hs200_taps.s.cmd_out_tap, |
| 2798 | slot->hs200_taps.s.data_in_tap, |
| 2799 | slot->hs200_taps.s.data_out_tap); |
| 2800 | else if (is_hs400) |
| 2801 | debug("%s(%s): hs400 taps: ci: %u, co: %u, di: %u, do: %u\n", |
| 2802 | __func__, mmc->dev->name, |
| 2803 | slot->hs400_taps.s.cmd_in_tap, |
| 2804 | slot->hs400_taps.s.cmd_out_tap, |
| 2805 | slot->hs400_taps.s.data_in_tap, |
| 2806 | slot->hs400_taps.s.data_out_tap); |
| 2807 | else |
| 2808 | debug("%s(%s): taps: ci: %u, co: %u, di: %u, do: %u\n", |
| 2809 | __func__, mmc->dev->name, slot->taps.s.cmd_in_tap, |
| 2810 | slot->taps.s.cmd_out_tap, |
| 2811 | slot->taps.s.data_in_tap, |
| 2812 | slot->taps.s.data_out_tap); |
| 2813 | octeontx_mmc_set_timing(mmc); |
| 2814 | debug("%s: Done\n", __func__); |
| 2815 | } |
| 2816 | |
| 2817 | return 0; |
| 2818 | } |
| 2819 | |
| 2820 | /** |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2821 | * Set the IO drive strength and slew |
| 2822 | * |
| 2823 | * @param mmc mmc device |
| 2824 | */ |
| 2825 | static void octeontx_mmc_io_drive_setup(struct mmc *mmc) |
| 2826 | { |
| 2827 | if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) { |
| 2828 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 2829 | union mio_emm_io_ctl io_ctl; |
| 2830 | |
| 2831 | if (slot->drive < 0 || slot->slew < 0) |
| 2832 | return; |
| 2833 | |
| 2834 | io_ctl.u = 0; |
| 2835 | io_ctl.s.drive = slot->drive; |
| 2836 | io_ctl.s.slew = slot->slew; |
| 2837 | write_csr(mmc, MIO_EMM_IO_CTL(), io_ctl.u); |
| 2838 | } |
| 2839 | } |
| 2840 | #endif |
| 2841 | |
| 2842 | /** |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2843 | * Sets the MMC watchdog timer in microseconds |
| 2844 | * |
| 2845 | * @param mmc mmc device |
| 2846 | * @param us timeout in microseconds, 0 for maximum timeout |
| 2847 | */ |
| 2848 | static void set_wdog(struct mmc *mmc, u64 us) |
| 2849 | { |
| 2850 | union mio_emm_wdog wdog; |
| 2851 | u64 val; |
| 2852 | |
| 2853 | val = (us * mmc->clock) / 1000000; |
| 2854 | if (val >= (1 << 26) || !us) { |
| 2855 | if (us) |
| 2856 | pr_debug("%s: warning: timeout %llu exceeds max value %llu, truncating\n", |
| 2857 | __func__, us, |
| 2858 | (u64)(((1ULL << 26) - 1) * 1000000ULL) / |
| 2859 | mmc->clock); |
| 2860 | val = (1 << 26) - 1; |
| 2861 | } |
| 2862 | wdog.u = 0; |
| 2863 | wdog.s.clk_cnt = val; |
| 2864 | write_csr(mmc, MIO_EMM_WDOG(), wdog.u); |
| 2865 | } |
| 2866 | |
| 2867 | /** |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2868 | * Print switch errors |
| 2869 | * |
| 2870 | * @param mmc mmc device |
| 2871 | */ |
| 2872 | static void check_switch_errors(struct mmc *mmc) |
| 2873 | { |
| 2874 | union mio_emm_switch emm_switch; |
| 2875 | |
| 2876 | emm_switch.u = read_csr(mmc, MIO_EMM_SWITCH()); |
| 2877 | if (emm_switch.s.switch_err0) |
| 2878 | pr_err("%s: Switch power class error\n", mmc->cfg->name); |
| 2879 | if (emm_switch.s.switch_err1) |
| 2880 | pr_err("%s: Switch HS timing error\n", mmc->cfg->name); |
| 2881 | if (emm_switch.s.switch_err2) |
| 2882 | pr_err("%s: Switch bus width error\n", mmc->cfg->name); |
| 2883 | } |
| 2884 | |
| 2885 | static void do_switch(struct mmc *mmc, union mio_emm_switch emm_switch) |
| 2886 | { |
| 2887 | union mio_emm_rsp_sts rsp_sts; |
| 2888 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 2889 | int bus_id = emm_switch.s.bus_id; |
| 2890 | ulong start; |
| 2891 | |
| 2892 | if (emm_switch.s.bus_id != 0) { |
| 2893 | emm_switch.s.bus_id = 0; |
| 2894 | write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u); |
| 2895 | udelay(100); |
| 2896 | emm_switch.s.bus_id = bus_id; |
| 2897 | } |
| 2898 | debug("%s(%s, 0x%llx)\n", __func__, mmc->dev->name, emm_switch.u); |
| 2899 | write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u); |
| 2900 | |
| 2901 | start = get_timer(0); |
| 2902 | do { |
| 2903 | rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS()); |
| 2904 | if (!rsp_sts.s.switch_val) |
| 2905 | break; |
| 2906 | udelay(100); |
| 2907 | } while (get_timer(start) < 10); |
| 2908 | if (rsp_sts.s.switch_val) { |
| 2909 | pr_warn("%s(%s): Warning: writing 0x%llx to emm_switch timed out, status: 0x%llx\n", |
| 2910 | __func__, mmc->dev->name, emm_switch.u, rsp_sts.u); |
| 2911 | } |
| 2912 | slot->cached_switch = emm_switch; |
| 2913 | check_switch_errors(mmc); |
| 2914 | slot->cached_switch.u = emm_switch.u; |
| 2915 | debug("%s: emm_switch: 0x%llx, rsp_lo: 0x%llx\n", |
| 2916 | __func__, read_csr(mmc, MIO_EMM_SWITCH()), |
| 2917 | read_csr(mmc, MIO_EMM_RSP_LO())); |
| 2918 | } |
| 2919 | |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2920 | /** |
| 2921 | * Calibrates the delay based on the internal clock |
| 2922 | * |
| 2923 | * @param mmc Pointer to mmc data structure |
| 2924 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 2925 | * Return: 0 for success or -ETIMEDOUT on error |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 2926 | * |
| 2927 | * NOTE: On error a default value will be calculated. |
| 2928 | */ |
| 2929 | #if defined(CONFIG_ARCH_OCTEON) |
| 2930 | static int octeontx_mmc_set_input_bus_timing(struct mmc *mmc) |
| 2931 | { |
| 2932 | return 0; |
| 2933 | } |
| 2934 | |
| 2935 | static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc) |
| 2936 | { |
| 2937 | return 0; |
| 2938 | } |
| 2939 | |
| 2940 | static int octeontx_mmc_calibrate_delay(struct mmc *mmc) |
| 2941 | { |
| 2942 | return 0; |
| 2943 | } |
| 2944 | #else |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2945 | /** |
| 2946 | * Given a delay in ps, return the tap delay count |
| 2947 | * |
| 2948 | * @param mmc mmc data structure |
| 2949 | * @param delay delay in picoseconds |
| 2950 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 2951 | * Return: Number of tap cycles or error if -1 |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2952 | */ |
| 2953 | static int octeontx2_mmc_calc_delay(struct mmc *mmc, int delay) |
| 2954 | { |
| 2955 | struct octeontx_mmc_host *host = mmc_to_host(mmc); |
| 2956 | |
| 2957 | if (host->is_asim || host->is_emul) |
| 2958 | return 63; |
| 2959 | |
| 2960 | if (!host->timing_taps) { |
| 2961 | pr_err("%s(%s): Error: host timing not calibrated\n", |
| 2962 | __func__, mmc->dev->name); |
| 2963 | return -1; |
| 2964 | } |
| 2965 | debug("%s(%s, %d) timing taps: %llu\n", __func__, mmc->dev->name, |
| 2966 | delay, host->timing_taps); |
| 2967 | return min_t(int, DIV_ROUND_UP(delay, host->timing_taps), 63); |
| 2968 | } |
| 2969 | |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 2970 | static int octeontx_mmc_calibrate_delay(struct mmc *mmc) |
| 2971 | { |
| 2972 | union mio_emm_calb emm_calb; |
| 2973 | union mio_emm_tap emm_tap; |
| 2974 | union mio_emm_cfg emm_cfg; |
| 2975 | union mio_emm_io_ctl emm_io_ctl; |
| 2976 | union mio_emm_switch emm_switch; |
| 2977 | union mio_emm_wdog emm_wdog; |
| 2978 | union mio_emm_sts_mask emm_sts_mask; |
| 2979 | union mio_emm_debug emm_debug; |
| 2980 | union mio_emm_timing emm_timing; |
| 2981 | struct octeontx_mmc_host *host = mmc_to_host(mmc); |
| 2982 | ulong start; |
| 2983 | u8 bus_id, bus_ena; |
| 2984 | |
| 2985 | debug("%s: Calibrating delay\n", __func__); |
| 2986 | if (host->is_asim || host->is_emul) { |
| 2987 | debug(" No calibration for ASIM\n"); |
| 2988 | return 0; |
| 2989 | } |
| 2990 | emm_tap.u = 0; |
| 2991 | if (host->calibrate_glitch) { |
| 2992 | emm_tap.s.delay = MMC_DEFAULT_TAP_DELAY; |
| 2993 | } else { |
| 2994 | /* Save registers */ |
| 2995 | emm_cfg.u = read_csr(mmc, MIO_EMM_CFG()); |
| 2996 | emm_io_ctl.u = read_csr(mmc, MIO_EMM_IO_CTL()); |
| 2997 | emm_switch.u = read_csr(mmc, MIO_EMM_SWITCH()); |
| 2998 | emm_wdog.u = read_csr(mmc, MIO_EMM_WDOG()); |
| 2999 | emm_sts_mask.u = read_csr(mmc, MIO_EMM_STS_MASK()); |
| 3000 | emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG()); |
| 3001 | emm_timing.u = read_csr(mmc, MIO_EMM_TIMING()); |
| 3002 | bus_ena = emm_cfg.s.bus_ena; |
| 3003 | bus_id = emm_switch.s.bus_id; |
| 3004 | emm_cfg.s.bus_ena = 0; |
| 3005 | write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u); |
| 3006 | udelay(1); |
| 3007 | emm_cfg.s.bus_ena = 1ULL << 3; |
| 3008 | write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u); |
| 3009 | mdelay(1); |
| 3010 | emm_calb.u = 0; |
| 3011 | write_csr(mmc, MIO_EMM_CALB(), emm_calb.u); |
| 3012 | emm_calb.s.start = 1; |
| 3013 | write_csr(mmc, MIO_EMM_CALB(), emm_calb.u); |
| 3014 | start = get_timer(0); |
| 3015 | /* This should only take 3 microseconds */ |
| 3016 | do { |
| 3017 | udelay(5); |
| 3018 | emm_tap.u = read_csr(mmc, MIO_EMM_TAP()); |
| 3019 | } while (!emm_tap.s.delay && get_timer(start) < 10); |
| 3020 | |
| 3021 | emm_calb.s.start = 0; |
| 3022 | write_csr(mmc, MIO_EMM_CALB(), emm_calb.u); |
| 3023 | |
| 3024 | emm_cfg.s.bus_ena = 0; |
| 3025 | write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u); |
| 3026 | udelay(1); |
| 3027 | /* Restore registers */ |
| 3028 | emm_cfg.s.bus_ena = bus_ena; |
| 3029 | write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u); |
| 3030 | if (host->tap_requires_noclk) { |
| 3031 | /* Turn off the clock */ |
| 3032 | emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG()); |
| 3033 | emm_debug.s.emmc_clk_disable = 1; |
| 3034 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 3035 | udelay(1); |
| 3036 | emm_debug.s.rdsync_rst = 1; |
| 3037 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 3038 | udelay(1); |
| 3039 | } |
| 3040 | |
| 3041 | write_csr(mmc, MIO_EMM_TIMING(), emm_timing.u); |
| 3042 | if (host->tap_requires_noclk) { |
| 3043 | /* Turn the clock back on */ |
| 3044 | udelay(1); |
| 3045 | emm_debug.s.rdsync_rst = 0; |
| 3046 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 3047 | udelay(1); |
| 3048 | emm_debug.s.emmc_clk_disable = 0; |
| 3049 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 3050 | } |
| 3051 | udelay(1); |
| 3052 | write_csr(mmc, MIO_EMM_IO_CTL(), emm_io_ctl.u); |
| 3053 | bus_id = emm_switch.s.bus_id; |
| 3054 | emm_switch.s.bus_id = 0; |
| 3055 | write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u); |
| 3056 | emm_switch.s.bus_id = bus_id; |
| 3057 | write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u); |
| 3058 | write_csr(mmc, MIO_EMM_WDOG(), emm_wdog.u); |
| 3059 | write_csr(mmc, MIO_EMM_STS_MASK(), emm_sts_mask.u); |
| 3060 | write_csr(mmc, MIO_EMM_RCA(), mmc->rca); |
| 3061 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 3062 | |
| 3063 | if (!emm_tap.s.delay) { |
| 3064 | pr_err("%s: Error: delay calibration failed, timed out.\n", |
| 3065 | __func__); |
| 3066 | /* Set to default value if timed out */ |
| 3067 | emm_tap.s.delay = MMC_DEFAULT_TAP_DELAY; |
| 3068 | return -ETIMEDOUT; |
| 3069 | } |
| 3070 | } |
| 3071 | /* Round up */ |
| 3072 | host->timing_taps = (10 * 1000 * emm_tap.s.delay) / TOTAL_NO_OF_TAPS; |
| 3073 | debug("%s(%s): timing taps: %llu, delay: %u\n", |
| 3074 | __func__, mmc->dev->name, host->timing_taps, emm_tap.s.delay); |
| 3075 | host->timing_calibrated = true; |
| 3076 | return 0; |
| 3077 | } |
| 3078 | |
| 3079 | static int octeontx_mmc_set_input_bus_timing(struct mmc *mmc) |
| 3080 | { |
| 3081 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 3082 | |
| 3083 | if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) { |
| 3084 | union mio_emm_sample sample; |
| 3085 | |
| 3086 | sample.u = 0; |
| 3087 | sample.s.cmd_cnt = slot->cmd_clk_skew; |
| 3088 | sample.s.dat_cnt = slot->dat_clk_skew; |
| 3089 | write_csr(mmc, MIO_EMM_SAMPLE(), sample.u); |
| 3090 | } else { |
| 3091 | union mio_emm_timing timing; |
| 3092 | |
| 3093 | timing.u = read_csr(mmc, MIO_EMM_TIMING()); |
| 3094 | if (mmc->selected_mode == MMC_HS_200) { |
| 3095 | if (slot->hs200_tuned) { |
| 3096 | timing.s.cmd_in_tap = |
| 3097 | slot->hs200_taps.s.cmd_in_tap; |
| 3098 | timing.s.data_in_tap = |
| 3099 | slot->hs200_taps.s.data_in_tap; |
| 3100 | } else { |
| 3101 | pr_warn("%s(%s): Warning: hs200 timing not tuned\n", |
| 3102 | __func__, mmc->dev->name); |
| 3103 | timing.s.cmd_in_tap = |
| 3104 | MMC_DEFAULT_HS200_CMD_IN_TAP; |
| 3105 | timing.s.data_in_tap = |
| 3106 | MMC_DEFAULT_HS200_DATA_IN_TAP; |
| 3107 | } |
| 3108 | } else if (mmc->selected_mode == MMC_HS_400) { |
| 3109 | if (slot->hs400_tuned) { |
| 3110 | timing.s.cmd_in_tap = |
| 3111 | slot->hs400_taps.s.cmd_in_tap; |
| 3112 | timing.s.data_in_tap = |
| 3113 | slot->hs400_taps.s.data_in_tap; |
| 3114 | } else if (slot->hs200_tuned) { |
| 3115 | timing.s.cmd_in_tap = |
| 3116 | slot->hs200_taps.s.cmd_in_tap; |
| 3117 | timing.s.data_in_tap = |
| 3118 | slot->hs200_taps.s.data_in_tap; |
| 3119 | } else { |
| 3120 | pr_warn("%s(%s): Warning: hs400 timing not tuned\n", |
| 3121 | __func__, mmc->dev->name); |
| 3122 | timing.s.cmd_in_tap = |
| 3123 | MMC_DEFAULT_HS200_CMD_IN_TAP; |
| 3124 | timing.s.data_in_tap = |
| 3125 | MMC_DEFAULT_HS200_DATA_IN_TAP; |
| 3126 | } |
| 3127 | } else if (slot->tuned) { |
| 3128 | timing.s.cmd_in_tap = slot->taps.s.cmd_in_tap; |
| 3129 | timing.s.data_in_tap = slot->taps.s.data_in_tap; |
| 3130 | } else { |
| 3131 | timing.s.cmd_in_tap = MMC_DEFAULT_CMD_IN_TAP; |
| 3132 | timing.s.data_in_tap = MMC_DEFAULT_DATA_IN_TAP; |
| 3133 | } |
| 3134 | octeontx_mmc_set_emm_timing(mmc, timing); |
| 3135 | } |
| 3136 | |
| 3137 | return 0; |
| 3138 | } |
| 3139 | |
| 3140 | /** |
| 3141 | * Sets the default bus timing for the current mode. |
| 3142 | * |
| 3143 | * @param mmc mmc data structure |
| 3144 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 3145 | * Return: 0 for success, error otherwise |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3146 | */ |
| 3147 | static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc) |
| 3148 | { |
| 3149 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 3150 | union mio_emm_timing timing; |
| 3151 | int cout_bdelay, dout_bdelay; |
| 3152 | unsigned int cout_delay, dout_delay; |
| 3153 | char env_name[32]; |
| 3154 | |
| 3155 | if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) |
| 3156 | return 0; |
| 3157 | |
| 3158 | debug("%s(%s)\n", __func__, mmc->dev->name); |
| 3159 | if (slot->is_asim || slot->is_emul) |
| 3160 | return 0; |
| 3161 | |
| 3162 | octeontx_mmc_calibrate_delay(mmc); |
| 3163 | |
| 3164 | if (mmc->clock < 26000000) { |
| 3165 | cout_delay = 5000; |
| 3166 | dout_delay = 5000; |
| 3167 | } else if (mmc->clock <= 52000000) { |
| 3168 | cout_delay = 2500; |
| 3169 | dout_delay = 2500; |
| 3170 | } else if (!mmc_is_mode_ddr(mmc->selected_mode)) { |
| 3171 | cout_delay = slot->cmd_out_hs200_delay; |
| 3172 | dout_delay = slot->data_out_hs200_delay; |
| 3173 | } else { |
| 3174 | cout_delay = slot->cmd_out_hs400_delay; |
| 3175 | dout_delay = slot->data_out_hs400_delay; |
| 3176 | } |
| 3177 | |
| 3178 | snprintf(env_name, sizeof(env_name), "mmc%d_hs200_dout_delay_ps", |
| 3179 | slot->bus_id); |
| 3180 | dout_delay = env_get_ulong(env_name, 10, dout_delay); |
| 3181 | debug("%s: dout_delay: %u\n", __func__, dout_delay); |
| 3182 | |
| 3183 | cout_bdelay = octeontx2_mmc_calc_delay(mmc, cout_delay); |
| 3184 | dout_bdelay = octeontx2_mmc_calc_delay(mmc, dout_delay); |
| 3185 | |
| 3186 | debug("%s: cmd output delay: %u, data output delay: %u, cmd bdelay: %d, data bdelay: %d, clock: %d\n", |
| 3187 | __func__, cout_delay, dout_delay, cout_bdelay, dout_bdelay, |
| 3188 | mmc->clock); |
| 3189 | if (cout_bdelay < 0 || dout_bdelay < 0) { |
| 3190 | pr_err("%s: Error: could not calculate command and/or data clock skew\n", |
| 3191 | __func__); |
| 3192 | return -1; |
| 3193 | } |
| 3194 | timing.u = read_csr(mmc, MIO_EMM_TIMING()); |
| 3195 | timing.s.cmd_out_tap = cout_bdelay; |
| 3196 | timing.s.data_out_tap = dout_bdelay; |
| 3197 | if (mmc->selected_mode == MMC_HS_200) { |
| 3198 | slot->hs200_taps.s.cmd_out_tap = cout_bdelay; |
| 3199 | slot->hs200_taps.s.data_out_tap = dout_bdelay; |
| 3200 | } else if (mmc->selected_mode == MMC_HS_400) { |
| 3201 | slot->hs400_taps.s.cmd_out_tap = cout_bdelay; |
| 3202 | slot->hs400_taps.s.data_out_tap = dout_bdelay; |
| 3203 | } else { |
| 3204 | slot->taps.s.cmd_out_tap = cout_bdelay; |
| 3205 | slot->taps.s.data_out_tap = dout_bdelay; |
| 3206 | } |
| 3207 | octeontx_mmc_set_emm_timing(mmc, timing); |
| 3208 | debug("%s(%s): bdelay: %d/%d, clock: %d, ddr: %s, timing taps: %llu, do: %d, di: %d, co: %d, ci: %d\n", |
| 3209 | __func__, mmc->dev->name, cout_bdelay, dout_bdelay, mmc->clock, |
| 3210 | mmc->ddr_mode ? "yes" : "no", |
| 3211 | mmc_to_host(mmc)->timing_taps, |
| 3212 | timing.s.data_out_tap, |
| 3213 | timing.s.data_in_tap, |
| 3214 | timing.s.cmd_out_tap, |
| 3215 | timing.s.cmd_in_tap); |
| 3216 | |
| 3217 | return 0; |
| 3218 | } |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 3219 | #endif |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3220 | |
| 3221 | static void octeontx_mmc_set_clock(struct mmc *mmc) |
| 3222 | { |
| 3223 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 3224 | uint clock; |
| 3225 | |
| 3226 | clock = min(mmc->cfg->f_max, (uint)slot->clock); |
| 3227 | clock = max(mmc->cfg->f_min, clock); |
| 3228 | debug("%s(%s): f_min: %u, f_max: %u, clock: %u\n", __func__, |
| 3229 | mmc->dev->name, mmc->cfg->f_min, mmc->cfg->f_max, clock); |
| 3230 | slot->clock = clock; |
| 3231 | mmc->clock = clock; |
| 3232 | } |
| 3233 | |
| 3234 | /** |
| 3235 | * This switches I/O power as needed when switching between slots. |
| 3236 | * |
| 3237 | * @param mmc mmc data structure |
| 3238 | */ |
| 3239 | static void octeontx_mmc_switch_io(struct mmc *mmc) |
| 3240 | { |
| 3241 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 3242 | struct octeontx_mmc_host *host = slot->host; |
| 3243 | struct mmc *last_mmc = host->last_mmc; |
| 3244 | static struct udevice *last_reg; |
| 3245 | union mio_emm_cfg emm_cfg; |
| 3246 | int bus; |
| 3247 | static bool initialized; |
| 3248 | |
| 3249 | /* First time? */ |
| 3250 | if (!initialized || mmc != host->last_mmc) { |
| 3251 | struct mmc *ommc; |
| 3252 | |
| 3253 | /* Switch to bus 3 which is unused */ |
| 3254 | emm_cfg.u = read_csr(mmc, MIO_EMM_CFG()); |
| 3255 | emm_cfg.s.bus_ena = 1 << 3; |
| 3256 | write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u); |
| 3257 | |
| 3258 | /* Turn off all other I/O interfaces with first initialization |
| 3259 | * if at least one supply was found. |
| 3260 | */ |
| 3261 | for (bus = 0; bus <= OCTEONTX_MAX_MMC_SLOT; bus++) { |
| 3262 | ommc = &host->slots[bus].mmc; |
| 3263 | |
| 3264 | /* Handle self case later */ |
| 3265 | if (ommc == mmc || !ommc->vqmmc_supply) |
| 3266 | continue; |
| 3267 | |
| 3268 | /* Skip if we're not switching regulators */ |
| 3269 | if (last_reg == mmc->vqmmc_supply) |
| 3270 | continue; |
| 3271 | |
| 3272 | /* Turn off other regulators */ |
| 3273 | if (ommc->vqmmc_supply != mmc->vqmmc_supply) |
| 3274 | regulator_set_enable(ommc->vqmmc_supply, false); |
| 3275 | } |
| 3276 | /* Turn ourself on */ |
| 3277 | if (mmc->vqmmc_supply && last_reg != mmc->vqmmc_supply) |
| 3278 | regulator_set_enable(mmc->vqmmc_supply, true); |
| 3279 | mdelay(1); /* Settle time */ |
| 3280 | /* Switch to new bus */ |
| 3281 | emm_cfg.s.bus_ena = 1 << slot->bus_id; |
| 3282 | write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u); |
| 3283 | last_reg = mmc->vqmmc_supply; |
| 3284 | initialized = true; |
| 3285 | return; |
| 3286 | } |
| 3287 | |
| 3288 | /* No change in device */ |
| 3289 | if (last_mmc == mmc) |
| 3290 | return; |
| 3291 | |
| 3292 | if (!last_mmc) { |
| 3293 | pr_warn("%s(%s): No previous slot detected in IO slot switch!\n", |
| 3294 | __func__, mmc->dev->name); |
| 3295 | return; |
| 3296 | } |
| 3297 | |
| 3298 | debug("%s(%s): last: %s, supply: %p\n", __func__, mmc->dev->name, |
| 3299 | last_mmc->dev->name, mmc->vqmmc_supply); |
| 3300 | |
| 3301 | /* The supply is the same so we do nothing */ |
| 3302 | if (last_mmc->vqmmc_supply == mmc->vqmmc_supply) |
| 3303 | return; |
| 3304 | |
| 3305 | /* Turn off the old slot I/O supply */ |
| 3306 | if (last_mmc->vqmmc_supply) { |
| 3307 | debug("%s(%s): Turning off IO to %s, supply: %s\n", |
| 3308 | __func__, mmc->dev->name, last_mmc->dev->name, |
| 3309 | last_mmc->vqmmc_supply->name); |
| 3310 | regulator_set_enable(last_mmc->vqmmc_supply, false); |
| 3311 | } |
| 3312 | /* Turn on the new slot I/O supply */ |
| 3313 | if (mmc->vqmmc_supply) { |
| 3314 | debug("%s(%s): Turning on IO to slot %d, supply: %s\n", |
| 3315 | __func__, mmc->dev->name, slot->bus_id, |
| 3316 | mmc->vqmmc_supply->name); |
| 3317 | regulator_set_enable(mmc->vqmmc_supply, true); |
| 3318 | } |
| 3319 | /* Allow power to settle */ |
| 3320 | mdelay(1); |
| 3321 | } |
| 3322 | |
| 3323 | /** |
| 3324 | * Called to switch between mmc devices |
| 3325 | * |
| 3326 | * @param mmc new mmc device |
| 3327 | */ |
| 3328 | static void octeontx_mmc_switch_to(struct mmc *mmc) |
| 3329 | { |
| 3330 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 3331 | struct octeontx_mmc_slot *old_slot; |
| 3332 | struct octeontx_mmc_host *host = slot->host; |
| 3333 | union mio_emm_switch emm_switch; |
| 3334 | union mio_emm_sts_mask emm_sts_mask; |
| 3335 | union mio_emm_rca emm_rca; |
| 3336 | |
| 3337 | if (slot->bus_id == host->last_slotid) |
| 3338 | return; |
| 3339 | |
| 3340 | debug("%s(%s) switching from slot %d to slot %d\n", __func__, |
| 3341 | mmc->dev->name, host->last_slotid, slot->bus_id); |
| 3342 | octeontx_mmc_switch_io(mmc); |
| 3343 | |
| 3344 | if (host->last_slotid >= 0 && slot->valid) { |
| 3345 | old_slot = &host->slots[host->last_slotid]; |
| 3346 | old_slot->cached_switch.u = read_csr(mmc, MIO_EMM_SWITCH()); |
| 3347 | old_slot->cached_rca.u = read_csr(mmc, MIO_EMM_RCA()); |
| 3348 | } |
| 3349 | if (mmc->rca) |
| 3350 | write_csr(mmc, MIO_EMM_RCA(), mmc->rca); |
| 3351 | emm_switch = slot->cached_switch; |
| 3352 | do_switch(mmc, emm_switch); |
| 3353 | emm_rca.u = 0; |
| 3354 | emm_rca.s.card_rca = mmc->rca; |
| 3355 | write_csr(mmc, MIO_EMM_RCA(), emm_rca.u); |
| 3356 | mdelay(100); |
| 3357 | |
| 3358 | set_wdog(mmc, 100000); |
| 3359 | if (octeontx_mmc_set_output_bus_timing(mmc) || |
| 3360 | octeontx_mmc_set_input_bus_timing(mmc)) |
| 3361 | pr_err("%s(%s): Error setting bus timing\n", __func__, |
| 3362 | mmc->dev->name); |
| 3363 | octeontx_mmc_io_drive_setup(mmc); |
| 3364 | |
| 3365 | emm_sts_mask.u = 0; |
| 3366 | emm_sts_mask.s.sts_msk = 1 << 7 | 1 << 22 | 1 << 23 | 1 << 19; |
| 3367 | write_csr(mmc, MIO_EMM_STS_MASK(), emm_sts_mask.u); |
| 3368 | host->last_slotid = slot->bus_id; |
| 3369 | host->last_mmc = mmc; |
| 3370 | mdelay(10); |
| 3371 | } |
| 3372 | |
| 3373 | /** |
| 3374 | * Perform initial timing configuration |
| 3375 | * |
| 3376 | * @param mmc mmc device |
| 3377 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 3378 | * Return: 0 for success |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3379 | * |
| 3380 | * NOTE: This will need to be updated when new silicon comes out |
| 3381 | */ |
| 3382 | static int octeontx_mmc_init_timing(struct mmc *mmc) |
| 3383 | { |
| 3384 | union mio_emm_timing timing; |
| 3385 | |
| 3386 | if (mmc_to_slot(mmc)->is_asim || mmc_to_slot(mmc)->is_emul) |
| 3387 | return 0; |
| 3388 | |
| 3389 | debug("%s(%s)\n", __func__, mmc->dev->name); |
| 3390 | timing.u = 0; |
| 3391 | timing.s.cmd_out_tap = MMC_DEFAULT_CMD_OUT_TAP; |
| 3392 | timing.s.data_out_tap = MMC_DEFAULT_DATA_OUT_TAP; |
| 3393 | timing.s.cmd_in_tap = MMC_DEFAULT_CMD_IN_TAP; |
| 3394 | timing.s.data_in_tap = MMC_DEFAULT_DATA_IN_TAP; |
| 3395 | octeontx_mmc_set_emm_timing(mmc, timing); |
| 3396 | return 0; |
| 3397 | } |
| 3398 | |
| 3399 | /** |
| 3400 | * Perform low-level initialization |
| 3401 | * |
| 3402 | * @param mmc mmc device |
| 3403 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 3404 | * Return: 0 for success, error otherwise |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3405 | */ |
| 3406 | static int octeontx_mmc_init_lowlevel(struct mmc *mmc) |
| 3407 | { |
| 3408 | struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); |
| 3409 | struct octeontx_mmc_host *host = slot->host; |
| 3410 | union mio_emm_switch emm_switch; |
| 3411 | u32 clk_period; |
| 3412 | |
| 3413 | debug("%s(%s): lowlevel init for slot %d\n", __func__, |
| 3414 | mmc->dev->name, slot->bus_id); |
| 3415 | host->emm_cfg.s.bus_ena &= ~(1 << slot->bus_id); |
| 3416 | write_csr(mmc, MIO_EMM_CFG(), host->emm_cfg.u); |
| 3417 | udelay(100); |
| 3418 | host->emm_cfg.s.bus_ena |= 1 << slot->bus_id; |
| 3419 | write_csr(mmc, MIO_EMM_CFG(), host->emm_cfg.u); |
| 3420 | udelay(10); |
| 3421 | slot->clock = mmc->cfg->f_min; |
| 3422 | octeontx_mmc_set_clock(&slot->mmc); |
| 3423 | |
| 3424 | if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) { |
| 3425 | if (host->cond_clock_glitch) { |
| 3426 | union mio_emm_debug emm_debug; |
| 3427 | |
| 3428 | emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG()); |
| 3429 | emm_debug.s.clk_on = 1; |
| 3430 | write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u); |
| 3431 | } |
| 3432 | octeontx_mmc_calibrate_delay(&slot->mmc); |
| 3433 | } |
| 3434 | |
| 3435 | clk_period = octeontx_mmc_calc_clk_period(mmc); |
| 3436 | emm_switch.u = 0; |
| 3437 | emm_switch.s.power_class = 10; |
| 3438 | emm_switch.s.clk_lo = clk_period / 2; |
| 3439 | emm_switch.s.clk_hi = clk_period / 2; |
| 3440 | |
| 3441 | emm_switch.s.bus_id = slot->bus_id; |
| 3442 | debug("%s: Performing switch\n", __func__); |
| 3443 | do_switch(mmc, emm_switch); |
| 3444 | slot->cached_switch.u = emm_switch.u; |
| 3445 | |
| 3446 | if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) |
| 3447 | octeontx_mmc_init_timing(mmc); |
| 3448 | |
| 3449 | set_wdog(mmc, 1000000); /* Set to 1 second */ |
| 3450 | write_csr(mmc, MIO_EMM_STS_MASK(), 0xe4390080ull); |
| 3451 | write_csr(mmc, MIO_EMM_RCA(), 1); |
| 3452 | mdelay(10); |
| 3453 | debug("%s: done\n", __func__); |
| 3454 | return 0; |
| 3455 | } |
| 3456 | |
| 3457 | /** |
| 3458 | * Translates a voltage number to bits in MMC register |
| 3459 | * |
| 3460 | * @param voltage voltage in microvolts |
| 3461 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 3462 | * Return: MMC register value for voltage |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3463 | */ |
| 3464 | static u32 xlate_voltage(u32 voltage) |
| 3465 | { |
| 3466 | u32 volt = 0; |
| 3467 | |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 3468 | /* Convert to millivolts. Only necessary on ARM Octeon TX/TX2 */ |
| 3469 | if (!IS_ENABLED(CONFIG_ARCH_OCTEON)) |
| 3470 | voltage /= 1000; |
| 3471 | |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3472 | if (voltage >= 1650 && voltage <= 1950) |
| 3473 | volt |= MMC_VDD_165_195; |
| 3474 | if (voltage >= 2000 && voltage <= 2100) |
| 3475 | volt |= MMC_VDD_20_21; |
| 3476 | if (voltage >= 2100 && voltage <= 2200) |
| 3477 | volt |= MMC_VDD_21_22; |
| 3478 | if (voltage >= 2200 && voltage <= 2300) |
| 3479 | volt |= MMC_VDD_22_23; |
| 3480 | if (voltage >= 2300 && voltage <= 2400) |
| 3481 | volt |= MMC_VDD_23_24; |
| 3482 | if (voltage >= 2400 && voltage <= 2500) |
| 3483 | volt |= MMC_VDD_24_25; |
| 3484 | if (voltage >= 2500 && voltage <= 2600) |
| 3485 | volt |= MMC_VDD_25_26; |
| 3486 | if (voltage >= 2600 && voltage <= 2700) |
| 3487 | volt |= MMC_VDD_26_27; |
| 3488 | if (voltage >= 2700 && voltage <= 2800) |
| 3489 | volt |= MMC_VDD_27_28; |
| 3490 | if (voltage >= 2800 && voltage <= 2900) |
| 3491 | volt |= MMC_VDD_28_29; |
| 3492 | if (voltage >= 2900 && voltage <= 3000) |
| 3493 | volt |= MMC_VDD_29_30; |
| 3494 | if (voltage >= 3000 && voltage <= 3100) |
| 3495 | volt |= MMC_VDD_30_31; |
| 3496 | if (voltage >= 3100 && voltage <= 3200) |
| 3497 | volt |= MMC_VDD_31_32; |
| 3498 | if (voltage >= 3200 && voltage <= 3300) |
| 3499 | volt |= MMC_VDD_32_33; |
| 3500 | if (voltage >= 3300 && voltage <= 3400) |
| 3501 | volt |= MMC_VDD_33_34; |
| 3502 | if (voltage >= 3400 && voltage <= 3500) |
| 3503 | volt |= MMC_VDD_34_35; |
| 3504 | if (voltage >= 3500 && voltage <= 3600) |
| 3505 | volt |= MMC_VDD_35_36; |
| 3506 | |
| 3507 | return volt; |
| 3508 | } |
| 3509 | |
| 3510 | /** |
| 3511 | * Check if a slot is valid in the device tree |
| 3512 | * |
| 3513 | * @param dev slot device to check |
| 3514 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 3515 | * Return: true if status reports "ok" or "okay" or if no status, |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3516 | * false otherwise. |
| 3517 | */ |
| 3518 | static bool octeontx_mmc_get_valid(struct udevice *dev) |
| 3519 | { |
Simon Glass | a7ece58 | 2020-12-19 10:40:14 -0700 | [diff] [blame] | 3520 | const char *stat = ofnode_read_string(dev_ofnode(dev), "status"); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3521 | |
| 3522 | if (!stat || !strncmp(stat, "ok", 2)) |
| 3523 | return true; |
| 3524 | else |
| 3525 | return false; |
| 3526 | } |
| 3527 | |
| 3528 | /** |
| 3529 | * Reads slot configuration from the device tree |
| 3530 | * |
| 3531 | * @param dev slot device |
| 3532 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 3533 | * Return: 0 on success, otherwise error |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3534 | */ |
| 3535 | static int octeontx_mmc_get_config(struct udevice *dev) |
| 3536 | { |
| 3537 | struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev); |
| 3538 | uint voltages[2]; |
| 3539 | uint low, high; |
| 3540 | char env_name[32]; |
| 3541 | int err; |
Simon Glass | a7ece58 | 2020-12-19 10:40:14 -0700 | [diff] [blame] | 3542 | ofnode node = dev_ofnode(dev); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3543 | int bus_width = 1; |
| 3544 | ulong new_max_freq; |
| 3545 | |
| 3546 | debug("%s(%s)", __func__, dev->name); |
| 3547 | slot->cfg.name = dev->name; |
| 3548 | |
Simon Glass | a7ece58 | 2020-12-19 10:40:14 -0700 | [diff] [blame] | 3549 | slot->cfg.f_max = ofnode_read_s32_default(dev_ofnode(dev), |
| 3550 | "max-frequency", |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3551 | 26000000); |
| 3552 | snprintf(env_name, sizeof(env_name), "mmc_max_frequency%d", |
| 3553 | slot->bus_id); |
| 3554 | |
| 3555 | new_max_freq = env_get_ulong(env_name, 10, slot->cfg.f_max); |
| 3556 | debug("Reading %s, got %lu\n", env_name, new_max_freq); |
| 3557 | |
| 3558 | if (new_max_freq != slot->cfg.f_max) { |
| 3559 | printf("Overriding device tree MMC maximum frequency %u to %lu\n", |
| 3560 | slot->cfg.f_max, new_max_freq); |
| 3561 | slot->cfg.f_max = new_max_freq; |
| 3562 | } |
| 3563 | slot->cfg.f_min = 400000; |
| 3564 | slot->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
| 3565 | |
| 3566 | if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) { |
| 3567 | slot->hs400_tuning_block = |
Simon Glass | a7ece58 | 2020-12-19 10:40:14 -0700 | [diff] [blame] | 3568 | ofnode_read_s32_default(dev_ofnode(dev), |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3569 | "marvell,hs400-tuning-block", |
| 3570 | -1); |
| 3571 | debug("%s(%s): mmc HS400 tuning block: %d\n", __func__, |
| 3572 | dev->name, slot->hs400_tuning_block); |
| 3573 | |
| 3574 | slot->hs200_tap_adj = |
Simon Glass | a7ece58 | 2020-12-19 10:40:14 -0700 | [diff] [blame] | 3575 | ofnode_read_s32_default(dev_ofnode(dev), |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3576 | "marvell,hs200-tap-adjust", 0); |
| 3577 | debug("%s(%s): hs200-tap-adjust: %d\n", __func__, dev->name, |
| 3578 | slot->hs200_tap_adj); |
| 3579 | slot->hs400_tap_adj = |
Simon Glass | a7ece58 | 2020-12-19 10:40:14 -0700 | [diff] [blame] | 3580 | ofnode_read_s32_default(dev_ofnode(dev), |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3581 | "marvell,hs400-tap-adjust", 0); |
| 3582 | debug("%s(%s): hs400-tap-adjust: %d\n", __func__, dev->name, |
| 3583 | slot->hs400_tap_adj); |
| 3584 | } |
| 3585 | |
Simon Glass | a7ece58 | 2020-12-19 10:40:14 -0700 | [diff] [blame] | 3586 | err = ofnode_read_u32_array(dev_ofnode(dev), "voltage-ranges", |
| 3587 | voltages, 2); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3588 | if (err) { |
| 3589 | slot->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
| 3590 | } else { |
| 3591 | low = xlate_voltage(voltages[0]); |
| 3592 | high = xlate_voltage(voltages[1]); |
| 3593 | debug(" low voltage: 0x%x (%u), high: 0x%x (%u)\n", |
| 3594 | low, voltages[0], high, voltages[1]); |
| 3595 | if (low > high || !low || !high) { |
| 3596 | pr_err("Invalid MMC voltage range [%u-%u] specified for %s\n", |
| 3597 | low, high, dev->name); |
| 3598 | return -1; |
| 3599 | } |
| 3600 | slot->cfg.voltages = 0; |
| 3601 | do { |
| 3602 | slot->cfg.voltages |= low; |
| 3603 | low <<= 1; |
| 3604 | } while (low <= high); |
| 3605 | } |
| 3606 | debug("%s: config voltages: 0x%x\n", __func__, slot->cfg.voltages); |
| 3607 | slot->slew = ofnode_read_s32_default(node, "cavium,clk-slew", -1); |
| 3608 | slot->drive = ofnode_read_s32_default(node, "cavium,drv-strength", -1); |
| 3609 | gpio_request_by_name(dev, "cd-gpios", 0, &slot->cd_gpio, GPIOD_IS_IN); |
| 3610 | slot->cd_inverted = ofnode_read_bool(node, "cd-inverted"); |
| 3611 | gpio_request_by_name(dev, "wp-gpios", 0, &slot->wp_gpio, GPIOD_IS_IN); |
| 3612 | slot->wp_inverted = ofnode_read_bool(node, "wp-inverted"); |
| 3613 | if (slot->cfg.voltages & MMC_VDD_165_195) { |
| 3614 | slot->is_1_8v = true; |
| 3615 | slot->is_3_3v = false; |
| 3616 | } else if (slot->cfg.voltages & (MMC_VDD_30_31 | MMC_VDD_31_32 | |
| 3617 | MMC_VDD_33_34 | MMC_VDD_34_35 | |
| 3618 | MMC_VDD_35_36)) { |
| 3619 | slot->is_1_8v = false; |
| 3620 | slot->is_3_3v = true; |
| 3621 | } |
| 3622 | |
| 3623 | bus_width = ofnode_read_u32_default(node, "bus-width", 1); |
| 3624 | /* Note fall-through */ |
| 3625 | switch (bus_width) { |
| 3626 | case 8: |
| 3627 | slot->cfg.host_caps |= MMC_MODE_8BIT; |
| 3628 | case 4: |
| 3629 | slot->cfg.host_caps |= MMC_MODE_4BIT; |
| 3630 | case 1: |
| 3631 | slot->cfg.host_caps |= MMC_MODE_1BIT; |
| 3632 | break; |
| 3633 | } |
| 3634 | if (ofnode_read_bool(node, "no-1-8-v")) { |
| 3635 | slot->is_3_3v = true; |
| 3636 | slot->is_1_8v = false; |
| 3637 | if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34))) |
| 3638 | pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n", |
| 3639 | __func__, dev->name); |
| 3640 | } |
| 3641 | if (ofnode_read_bool(node, "mmc-ddr-3-3v")) { |
| 3642 | slot->is_3_3v = true; |
| 3643 | slot->is_1_8v = false; |
| 3644 | if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34))) |
| 3645 | pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n", |
| 3646 | __func__, dev->name); |
| 3647 | } |
| 3648 | if (ofnode_read_bool(node, "cap-sd-highspeed") || |
| 3649 | ofnode_read_bool(node, "cap-mmc-highspeed") || |
| 3650 | ofnode_read_bool(node, "sd-uhs-sdr25")) |
| 3651 | slot->cfg.host_caps |= MMC_MODE_HS; |
| 3652 | if (slot->cfg.f_max >= 50000000 && |
| 3653 | slot->cfg.host_caps & MMC_MODE_HS) |
| 3654 | slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
| 3655 | if (ofnode_read_bool(node, "sd-uhs-sdr50")) |
| 3656 | slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
| 3657 | if (ofnode_read_bool(node, "sd-uhs-ddr50")) |
| 3658 | slot->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | |
| 3659 | MMC_MODE_DDR_52MHz; |
| 3660 | |
| 3661 | if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) { |
| 3662 | if (!slot->is_asim && !slot->is_emul) { |
| 3663 | if (ofnode_read_bool(node, "mmc-hs200-1_8v")) |
| 3664 | slot->cfg.host_caps |= MMC_MODE_HS200 | |
| 3665 | MMC_MODE_HS_52MHz; |
| 3666 | if (ofnode_read_bool(node, "mmc-hs400-1_8v")) |
| 3667 | slot->cfg.host_caps |= MMC_MODE_HS400 | |
| 3668 | MMC_MODE_HS_52MHz | |
| 3669 | MMC_MODE_HS200 | |
| 3670 | MMC_MODE_DDR_52MHz; |
| 3671 | slot->cmd_out_hs200_delay = |
| 3672 | ofnode_read_u32_default(node, |
| 3673 | "marvell,cmd-out-hs200-dly", |
| 3674 | MMC_DEFAULT_HS200_CMD_OUT_DLY); |
| 3675 | debug("%s(%s): HS200 cmd out delay: %d\n", |
| 3676 | __func__, dev->name, slot->cmd_out_hs200_delay); |
| 3677 | slot->data_out_hs200_delay = |
| 3678 | ofnode_read_u32_default(node, |
| 3679 | "marvell,data-out-hs200-dly", |
| 3680 | MMC_DEFAULT_HS200_DATA_OUT_DLY); |
| 3681 | debug("%s(%s): HS200 data out delay: %d\n", |
| 3682 | __func__, dev->name, slot->data_out_hs200_delay); |
| 3683 | slot->cmd_out_hs400_delay = |
| 3684 | ofnode_read_u32_default(node, |
| 3685 | "marvell,cmd-out-hs400-dly", |
| 3686 | MMC_DEFAULT_HS400_CMD_OUT_DLY); |
| 3687 | debug("%s(%s): HS400 cmd out delay: %d\n", |
| 3688 | __func__, dev->name, slot->cmd_out_hs400_delay); |
| 3689 | slot->data_out_hs400_delay = |
| 3690 | ofnode_read_u32_default(node, |
| 3691 | "marvell,data-out-hs400-dly", |
| 3692 | MMC_DEFAULT_HS400_DATA_OUT_DLY); |
| 3693 | debug("%s(%s): HS400 data out delay: %d\n", |
| 3694 | __func__, dev->name, slot->data_out_hs400_delay); |
| 3695 | } |
| 3696 | } |
| 3697 | |
| 3698 | slot->disable_ddr = ofnode_read_bool(node, "marvell,disable-ddr"); |
| 3699 | slot->non_removable = ofnode_read_bool(node, "non-removable"); |
| 3700 | slot->cmd_clk_skew = ofnode_read_u32_default(node, |
| 3701 | "cavium,cmd-clk-skew", 0); |
| 3702 | slot->dat_clk_skew = ofnode_read_u32_default(node, |
| 3703 | "cavium,dat-clk-skew", 0); |
| 3704 | debug("%s(%s): host caps: 0x%x\n", __func__, |
| 3705 | dev->name, slot->cfg.host_caps); |
| 3706 | return 0; |
| 3707 | } |
| 3708 | |
| 3709 | /** |
| 3710 | * Probes a MMC slot |
| 3711 | * |
| 3712 | * @param dev mmc device |
| 3713 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 3714 | * Return: 0 for success, error otherwise |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3715 | */ |
| 3716 | static int octeontx_mmc_slot_probe(struct udevice *dev) |
| 3717 | { |
| 3718 | struct octeontx_mmc_slot *slot; |
| 3719 | struct mmc *mmc; |
| 3720 | int err; |
| 3721 | |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3722 | debug("%s(%s)\n", __func__, dev->name); |
| 3723 | if (!host_probed) { |
| 3724 | pr_err("%s(%s): Error: host not probed yet\n", |
| 3725 | __func__, dev->name); |
| 3726 | } |
| 3727 | slot = dev_to_mmc_slot(dev); |
| 3728 | mmc = &slot->mmc; |
| 3729 | mmc->dev = dev; |
| 3730 | |
| 3731 | slot->valid = false; |
| 3732 | if (!octeontx_mmc_get_valid(dev)) { |
| 3733 | debug("%s(%s): slot is invalid\n", __func__, dev->name); |
| 3734 | return -ENODEV; |
| 3735 | } |
| 3736 | |
| 3737 | debug("%s(%s): Getting config\n", __func__, dev->name); |
| 3738 | err = octeontx_mmc_get_config(dev); |
| 3739 | if (err) { |
| 3740 | pr_err("probe(%s): Error getting config\n", dev->name); |
| 3741 | return err; |
| 3742 | } |
| 3743 | |
| 3744 | debug("%s(%s): mmc bind, mmc: %p\n", __func__, dev->name, &slot->mmc); |
| 3745 | err = mmc_bind(dev, &slot->mmc, &slot->cfg); |
| 3746 | if (err) { |
| 3747 | pr_err("%s(%s): Error binding mmc\n", __func__, dev->name); |
| 3748 | return -1; |
| 3749 | } |
| 3750 | |
| 3751 | /* For some reason, mmc_bind always assigns priv to the device */ |
| 3752 | slot->mmc.priv = slot; |
| 3753 | |
| 3754 | debug("%s(%s): lowlevel init\n", __func__, dev->name); |
| 3755 | err = octeontx_mmc_init_lowlevel(mmc); |
| 3756 | if (err) { |
| 3757 | pr_err("probe(%s): Low-level init failed\n", dev->name); |
| 3758 | return err; |
| 3759 | } |
| 3760 | |
| 3761 | slot->valid = true; |
| 3762 | |
| 3763 | debug("%s(%s):\n" |
| 3764 | " base address : %p\n" |
| 3765 | " bus id : %d\n", __func__, dev->name, |
| 3766 | slot->base_addr, slot->bus_id); |
| 3767 | |
| 3768 | return err; |
| 3769 | } |
| 3770 | |
| 3771 | /** |
| 3772 | * MMC slot driver operations |
| 3773 | */ |
| 3774 | static const struct dm_mmc_ops octeontx_hsmmc_ops = { |
| 3775 | .send_cmd = octeontx_mmc_dev_send_cmd, |
| 3776 | .set_ios = octeontx_mmc_set_ios, |
| 3777 | .get_cd = octeontx_mmc_get_cd, |
| 3778 | .get_wp = octeontx_mmc_get_wp, |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 3779 | #if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3780 | .execute_tuning = octeontx_mmc_execute_tuning, |
| 3781 | #endif |
| 3782 | }; |
| 3783 | |
| 3784 | static const struct udevice_id octeontx_hsmmc_ids[] = { |
| 3785 | { .compatible = "mmc-slot" }, |
| 3786 | { } |
| 3787 | }; |
| 3788 | |
| 3789 | U_BOOT_DRIVER(octeontx_hsmmc_slot) = { |
| 3790 | .name = "octeontx_hsmmc_slot", |
| 3791 | .id = UCLASS_MMC, |
| 3792 | .of_match = of_match_ptr(octeontx_hsmmc_ids), |
| 3793 | .probe = octeontx_mmc_slot_probe, |
| 3794 | .ops = &octeontx_hsmmc_ops, |
| 3795 | }; |
| 3796 | |
| 3797 | /***************************************************************** |
| 3798 | * PCI host driver |
| 3799 | * |
| 3800 | * The PCI host driver contains the resources used by all of the |
| 3801 | * slot drivers. |
| 3802 | * |
| 3803 | * The slot drivers are pseudo drivers. |
| 3804 | */ |
| 3805 | |
| 3806 | /** |
| 3807 | * Probe the MMC host controller |
| 3808 | * |
| 3809 | * @param dev mmc host controller device |
| 3810 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 3811 | * Return: 0 for success, -1 on error |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3812 | */ |
| 3813 | static int octeontx_mmc_host_probe(struct udevice *dev) |
| 3814 | { |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3815 | struct octeontx_mmc_host *host = dev_get_priv(dev); |
| 3816 | union mio_emm_int emm_int; |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 3817 | struct clk clk; |
| 3818 | int ret; |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3819 | u8 rev; |
| 3820 | |
| 3821 | debug("%s(%s): Entry host: %p\n", __func__, dev->name, host); |
| 3822 | |
| 3823 | if (!octeontx_mmc_get_valid(dev)) { |
| 3824 | debug("%s(%s): mmc host not valid\n", __func__, dev->name); |
| 3825 | return -ENODEV; |
| 3826 | } |
| 3827 | memset(host, 0, sizeof(*host)); |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 3828 | |
| 3829 | /* Octeon TX & TX2 use PCI based probing */ |
| 3830 | if (device_is_compatible(dev, "cavium,thunder-8890-mmc")) { |
Andrew Scull | 6520c82 | 2022-04-21 16:11:13 +0000 | [diff] [blame] | 3831 | host->base_addr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 3832 | PCI_REGION_MEM); |
| 3833 | if (!host->base_addr) { |
| 3834 | pr_err("%s: Error: MMC base address not found\n", |
| 3835 | __func__); |
| 3836 | return -1; |
| 3837 | } |
| 3838 | } else { |
| 3839 | host->base_addr = dev_remap_addr(dev); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3840 | } |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 3841 | |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3842 | host->dev = dev; |
| 3843 | debug("%s(%s): Base address: %p\n", __func__, dev->name, |
| 3844 | host->base_addr); |
Simon Glass | 07c1777 | 2020-12-19 10:40:12 -0700 | [diff] [blame] | 3845 | if (!dev_has_ofnode(dev)) { |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3846 | pr_err("%s: No device tree information found\n", __func__); |
| 3847 | return -1; |
| 3848 | } |
Simon Glass | a7ece58 | 2020-12-19 10:40:14 -0700 | [diff] [blame] | 3849 | host->node = dev_ofnode(dev); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3850 | host->last_slotid = -1; |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 3851 | #if !defined(CONFIG_ARCH_OCTEON) |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3852 | if (otx_is_platform(PLATFORM_ASIM)) |
| 3853 | host->is_asim = true; |
| 3854 | if (otx_is_platform(PLATFORM_EMULATOR)) |
| 3855 | host->is_emul = true; |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 3856 | #endif |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3857 | host->dma_wait_delay = |
Simon Glass | a7ece58 | 2020-12-19 10:40:14 -0700 | [diff] [blame] | 3858 | ofnode_read_u32_default(dev_ofnode(dev), |
| 3859 | "marvell,dma-wait-delay", 1); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3860 | /* Force reset of eMMC */ |
| 3861 | writeq(0, host->base_addr + MIO_EMM_CFG()); |
| 3862 | debug("%s: Clearing MIO_EMM_CFG\n", __func__); |
| 3863 | udelay(100); |
| 3864 | emm_int.u = readq(host->base_addr + MIO_EMM_INT()); |
| 3865 | debug("%s: Writing 0x%llx to MIO_EMM_INT\n", __func__, emm_int.u); |
| 3866 | writeq(emm_int.u, host->base_addr + MIO_EMM_INT()); |
| 3867 | |
| 3868 | debug("%s(%s): Getting I/O clock\n", __func__, dev->name); |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 3869 | ret = clk_get_by_index(dev, 0, &clk); |
| 3870 | if (ret < 0) |
| 3871 | return ret; |
| 3872 | |
| 3873 | ret = clk_enable(&clk); |
| 3874 | if (ret) |
| 3875 | return ret; |
| 3876 | |
| 3877 | host->sys_freq = clk_get_rate(&clk); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3878 | debug("%s(%s): I/O clock %llu\n", __func__, dev->name, host->sys_freq); |
| 3879 | |
| 3880 | if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) { |
| 3881 | /* Flags for issues to work around */ |
| 3882 | dm_pci_read_config8(dev, PCI_REVISION_ID, &rev); |
| 3883 | if (otx_is_soc(CN96XX)) { |
| 3884 | debug("%s: CN96XX revision %d\n", __func__, rev); |
| 3885 | switch (rev) { |
| 3886 | case 0: |
| 3887 | host->calibrate_glitch = true; |
| 3888 | host->cond_clock_glitch = true; |
| 3889 | break; |
| 3890 | case 1: |
| 3891 | break; |
| 3892 | case 2: |
| 3893 | break; |
| 3894 | case 0x10: /* C0 */ |
| 3895 | host->hs400_skew_needed = true; |
| 3896 | debug("HS400 skew support enabled\n"); |
| 3897 | fallthrough; |
| 3898 | default: |
| 3899 | debug("CN96XX rev C0+ detected\n"); |
| 3900 | host->tap_requires_noclk = true; |
| 3901 | break; |
| 3902 | } |
| 3903 | } else if (otx_is_soc(CN95XX)) { |
| 3904 | if (!rev) |
| 3905 | host->cond_clock_glitch = true; |
| 3906 | } |
| 3907 | } |
| 3908 | |
| 3909 | host_probed = true; |
| 3910 | |
| 3911 | return 0; |
| 3912 | } |
| 3913 | |
| 3914 | /** |
| 3915 | * This performs some initial setup before a probe occurs. |
| 3916 | * |
| 3917 | * @param dev: MMC slot device |
| 3918 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 3919 | * Return: 0 for success, -1 on failure |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3920 | * |
| 3921 | * Do some pre-initialization before probing a slot. |
| 3922 | */ |
| 3923 | static int octeontx_mmc_host_child_pre_probe(struct udevice *dev) |
| 3924 | { |
| 3925 | struct octeontx_mmc_host *host = dev_get_priv(dev_get_parent(dev)); |
| 3926 | struct octeontx_mmc_slot *slot; |
| 3927 | struct mmc_uclass_priv *upriv; |
Simon Glass | a7ece58 | 2020-12-19 10:40:14 -0700 | [diff] [blame] | 3928 | ofnode node = dev_ofnode(dev); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3929 | u32 bus_id; |
| 3930 | char name[16]; |
| 3931 | int err; |
| 3932 | |
| 3933 | debug("%s(%s) Pre-Probe\n", __func__, dev->name); |
| 3934 | if (ofnode_read_u32(node, "reg", &bus_id)) { |
| 3935 | pr_err("%s(%s): Error: \"reg\" not found in device tree\n", |
| 3936 | __func__, dev->name); |
| 3937 | return -1; |
| 3938 | } |
| 3939 | if (bus_id > OCTEONTX_MAX_MMC_SLOT) { |
| 3940 | pr_err("%s(%s): Error: \"reg\" out of range of 0..%d\n", |
| 3941 | __func__, dev->name, OCTEONTX_MAX_MMC_SLOT); |
| 3942 | return -1; |
| 3943 | } |
| 3944 | |
| 3945 | slot = &host->slots[bus_id]; |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 3946 | dev_set_priv(dev, slot); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3947 | slot->host = host; |
| 3948 | slot->bus_id = bus_id; |
| 3949 | slot->dev = dev; |
| 3950 | slot->base_addr = host->base_addr; |
| 3951 | slot->is_asim = host->is_asim; |
| 3952 | slot->is_emul = host->is_emul; |
| 3953 | |
| 3954 | snprintf(name, sizeof(name), "octeontx-mmc%d", bus_id); |
| 3955 | err = device_set_name(dev, name); |
| 3956 | |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 3957 | /* FIXME: This code should not be needed */ |
| 3958 | if (!dev_get_uclass_priv(dev)) { |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3959 | debug("%s(%s): Allocating uclass priv\n", __func__, |
| 3960 | dev->name); |
| 3961 | upriv = calloc(1, sizeof(struct mmc_uclass_priv)); |
| 3962 | if (!upriv) |
| 3963 | return -ENOMEM; |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 3964 | |
| 3965 | /* |
| 3966 | * FIXME: This is not allowed |
| 3967 | * dev_set_uclass_priv(dev, upriv); |
| 3968 | * uclass_set_priv(dev->uclass, upriv); |
| 3969 | */ |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3970 | } else { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 3971 | upriv = dev_get_uclass_priv(dev); |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3972 | } |
| 3973 | |
| 3974 | upriv->mmc = &slot->mmc; |
| 3975 | debug("%s: uclass priv: %p, mmc: %p\n", dev->name, upriv, upriv->mmc); |
| 3976 | |
| 3977 | debug("%s: ret: %d\n", __func__, err); |
| 3978 | return err; |
| 3979 | } |
| 3980 | |
| 3981 | static const struct udevice_id octeontx_hsmmc_host_ids[] = { |
| 3982 | { .compatible = "cavium,thunder-8890-mmc" }, |
Stefan Roese | e06f552 | 2021-03-12 09:48:25 +0100 | [diff] [blame] | 3983 | { .compatible = "cavium,octeon-7360-mmc" }, |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3984 | { } |
| 3985 | }; |
| 3986 | |
| 3987 | U_BOOT_DRIVER(octeontx_hsmmc_host) = { |
| 3988 | .name = "octeontx_hsmmc_host", |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 3989 | /* FIXME: Why is this not UCLASS_MMC? */ |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3990 | .id = UCLASS_MISC, |
| 3991 | .of_match = of_match_ptr(octeontx_hsmmc_host_ids), |
| 3992 | .probe = octeontx_mmc_host_probe, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 3993 | .priv_auto = sizeof(struct octeontx_mmc_host), |
Suneel Garapati | 40e6133 | 2019-10-19 18:03:01 -0700 | [diff] [blame] | 3994 | .child_pre_probe = octeontx_mmc_host_child_pre_probe, |
| 3995 | .flags = DM_FLAG_PRE_RELOC, |
| 3996 | }; |
| 3997 | |
| 3998 | static struct pci_device_id octeontx_mmc_supported[] = { |
| 3999 | { PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_EMMC) }, |
| 4000 | { }, |
| 4001 | }; |
| 4002 | |
| 4003 | U_BOOT_PCI_DEVICE(octeontx_hsmmc_host, octeontx_mmc_supported); |