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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Hao Zhang8e697a02014-07-09 23:44:46 +03002/*
3 * K2HK EVM : Board initialization
4 *
5 * (C) Copyright 2012-2014
6 * Texas Instruments Incorporated, <www.ti.com>
Hao Zhang8e697a02014-07-09 23:44:46 +03007 */
8
Simon Glass2dc9c342020-05-10 11:40:01 -06009#include <image.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Vitaly Andrianov047e7802014-07-25 22:23:19 +030011#include <asm/arch/clock.h>
Hao Zhang8e697a02014-07-09 23:44:46 +030012#include <asm/arch/hardware.h>
Khoronzhuk, Ivanf2c13ba2014-09-29 22:17:22 +030013#include <asm/ti-common/keystone_net.h>
Hao Zhang8e697a02014-07-09 23:44:46 +030014
Hao Zhang8e697a02014-07-09 23:44:46 +030015unsigned int external_clk[ext_clk_count] = {
16 [sys_clk] = 122880000,
17 [alt_core_clk] = 125000000,
18 [pa_clk] = 122880000,
19 [tetris_clk] = 125000000,
20 [ddr3a_clk] = 100000000,
21 [ddr3b_clk] = 100000000,
Hao Zhang8e697a02014-07-09 23:44:46 +030022};
23
Lokesh Vutlaa9a0e122017-05-03 16:58:26 +053024unsigned int get_external_clk(u32 clk)
25{
26 unsigned int clk_freq;
27
28 switch (clk) {
29 case sys_clk:
30 clk_freq = 122880000;
31 break;
32 case alt_core_clk:
33 clk_freq = 125000000;
34 break;
35 case pa_clk:
36 clk_freq = 122880000;
37 break;
38 case tetris_clk:
39 clk_freq = 125000000;
40 break;
41 case ddr3a_clk:
42 clk_freq = 100000000;
43 break;
44 case ddr3b_clk:
45 clk_freq = 100000000;
46 break;
47 default:
48 clk_freq = 0;
49 break;
50 }
51
52 return clk_freq;
53}
54
Lokesh Vutla9da9afa2015-07-28 14:16:44 +053055static struct pll_init_data core_pll_config[NUM_SPDS] = {
56 [SPD800] = CORE_PLL_799,
57 [SPD1000] = CORE_PLL_999,
58 [SPD1200] = CORE_PLL_1200,
Vitaly Andrianov047e7802014-07-25 22:23:19 +030059};
60
Lokesh Vutla70438fc2015-07-28 14:16:43 +053061s16 divn_val[16] = {
62 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
63};
64
Vitaly Andrianov047e7802014-07-25 22:23:19 +030065static struct pll_init_data tetris_pll_config[] = {
Lokesh Vutla9da9afa2015-07-28 14:16:44 +053066 [SPD800] = TETRIS_PLL_800,
67 [SPD1000] = TETRIS_PLL_1000,
68 [SPD1200] = TETRIS_PLL_1200,
69 [SPD1350] = TETRIS_PLL_1350,
70 [SPD1400] = TETRIS_PLL_1400,
Hao Zhang8e697a02014-07-09 23:44:46 +030071};
72
Vitaly Andrianov047e7802014-07-25 22:23:19 +030073static struct pll_init_data pa_pll_config =
74 PASS_PLL_983;
75
Lokesh Vutla79a94a22015-07-28 14:16:46 +053076struct pll_init_data *get_pll_init_data(int pll)
77{
78 int speed;
79 struct pll_init_data *data;
80
81 switch (pll) {
82 case MAIN_PLL:
Lokesh Vutlab35410e2016-03-04 10:36:40 -060083 speed = get_max_dev_speed(speeds);
Lokesh Vutla79a94a22015-07-28 14:16:46 +053084 data = &core_pll_config[speed];
85 break;
86 case TETRIS_PLL:
Lokesh Vutlab35410e2016-03-04 10:36:40 -060087 speed = get_max_arm_speed(speeds);
Lokesh Vutla79a94a22015-07-28 14:16:46 +053088 data = &tetris_pll_config[speed];
89 break;
90 case PASS_PLL:
91 data = &pa_pll_config;
92 break;
93 default:
94 data = NULL;
95 }
96
97 return data;
98}
99
Hao Zhang8e697a02014-07-09 23:44:46 +0300100#ifdef CONFIG_BOARD_EARLY_INIT_F
101int board_early_init_f(void)
102{
Lokesh Vutla79a94a22015-07-28 14:16:46 +0530103 init_plls();
Vitaly Andrianov047e7802014-07-25 22:23:19 +0300104
Hao Zhang8e697a02014-07-09 23:44:46 +0300105 return 0;
106}
107#endif
Hao Zhang95948202014-10-22 16:32:31 +0300108
Jean-Jacques Hiblot2037fa42017-09-15 12:57:24 +0200109#if defined(CONFIG_MULTI_DTB_FIT)
Cooper Jr., Franklin43ff2242017-06-16 17:25:16 -0500110int board_fit_config_name_match(const char *name)
111{
112 if (!strcmp(name, "keystone-k2hk-evm"))
113 return 0;
114
115 return -1;
116}
117#endif
118
Hao Zhang95948202014-10-22 16:32:31 +0300119#ifdef CONFIG_SPL_BUILD
Hao Zhang95948202014-10-22 16:32:31 +0300120void spl_init_keystone_plls(void)
121{
Lokesh Vutla79a94a22015-07-28 14:16:46 +0530122 init_plls();
Hao Zhang95948202014-10-22 16:32:31 +0300123}
124#endif