blob: db59ebb838e76e836b842df334a1c98721eef839 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotardac871ab2018-01-18 13:39:32 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrice Chotard5d9950d2020-12-02 18:47:30 +01004 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
Patrice Chotardac871ab2018-01-18 13:39:32 +01005 */
6
Patrice Chotardac871ab2018-01-18 13:39:32 +01007#include <dm.h>
Simon Glassed38aef2020-05-10 11:40:03 -06008#include <env.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060011#include <asm/global_data.h>
Patrice Chotardac871ab2018-01-18 13:39:32 +010012
13#include <asm/io.h>
14#include <asm/arch/stm32.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18int dram_init(void)
19{
20 int rv;
21 struct udevice *dev;
22
23 rv = uclass_get_device(UCLASS_RAM, 0, &dev);
24 if (rv) {
25 debug("DRAM init failed: %d\n", rv);
26 return rv;
27 }
28
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +053029 if (fdtdec_setup_mem_size_base() != 0)
Patrice Chotardac871ab2018-01-18 13:39:32 +010030 rv = -EINVAL;
31
32 return rv;
33}
34
35int dram_init_banksize(void)
36{
37 fdtdec_setup_memory_banksize();
38
39 return 0;
40}
41
Patrice Chotardac871ab2018-01-18 13:39:32 +010042int board_init(void)
43{
Patrice Chotardac871ab2018-01-18 13:39:32 +010044 return 0;
45}
46
47#ifdef CONFIG_MISC_INIT_R
48int misc_init_r(void)
49{
50 char serialno[25];
51 u32 u_id_low, u_id_mid, u_id_high;
52
53 if (!env_get("serial#")) {
54 u_id_low = readl(&STM32_U_ID->u_id_low);
55 u_id_mid = readl(&STM32_U_ID->u_id_mid);
56 u_id_high = readl(&STM32_U_ID->u_id_high);
57 sprintf(serialno, "%08x%08x%08x",
58 u_id_high, u_id_mid, u_id_low);
59 env_set("serial#", serialno);
60 }
61
62 return 0;
63}
64#endif