Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Board functions for TI AM335X based pxm2 board |
| 4 | * (C) Copyright 2013 Siemens Schweiz AG |
| 5 | * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 6 | * |
| 7 | * Based on: |
| 8 | * u-boot:/board/ti/am335x/board.c |
| 9 | * |
| 10 | * Board functions for TI AM335X based boards |
| 11 | * |
Nishanth Menon | eaa39c6 | 2023-11-01 15:56:03 -0500 | [diff] [blame] | 12 | * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 13 | */ |
| 14 | |
Enrico Leto | fce9179 | 2024-01-24 15:43:54 +0100 | [diff] [blame] | 15 | #include <cpsw.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 16 | #include <env.h> |
Enrico Leto | fce9179 | 2024-01-24 15:43:54 +0100 | [diff] [blame] | 17 | #include <i2c.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 18 | #include <init.h> |
Enrico Leto | fce9179 | 2024-01-24 15:43:54 +0100 | [diff] [blame] | 19 | #include <nand.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 20 | #include <net.h> |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 21 | #include <asm/arch/clock.h> |
Enrico Leto | fce9179 | 2024-01-24 15:43:54 +0100 | [diff] [blame] | 22 | #include <asm/arch/ddr_defs.h> |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 23 | #include <asm/arch/sys_proto.h> |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 24 | #include <asm/gpio.h> |
Enrico Leto | fce9179 | 2024-01-24 15:43:54 +0100 | [diff] [blame] | 25 | #include <asm/io.h> |
| 26 | #include "pmic.h" |
Enrico Leto | 2e74050 | 2024-01-24 15:43:53 +0100 | [diff] [blame] | 27 | #include "../common/board_am335x.h" |
Enrico Leto | 096bfdc | 2024-01-24 15:43:49 +0100 | [diff] [blame] | 28 | #include "../common/eeprom.h" |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 29 | #include "../common/factoryset.h" |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 30 | |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 31 | #ifdef CONFIG_SPL_BUILD |
Enrico Leto | 2e74050 | 2024-01-24 15:43:53 +0100 | [diff] [blame] | 32 | void draco_init_ddr(void) |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 33 | { |
| 34 | struct emif_regs pxm2_ddr3_emif_reg_data = { |
| 35 | .sdram_config = 0x41805332, |
| 36 | .sdram_tim1 = 0x666b3c9, |
| 37 | .sdram_tim2 = 0x243631ca, |
| 38 | .sdram_tim3 = 0x33f, |
| 39 | .emif_ddr_phy_ctlr_1 = 0x100005, |
| 40 | .zq_config = 0, |
| 41 | .ref_ctrl = 0x81a, |
| 42 | }; |
| 43 | |
| 44 | struct ddr_data pxm2_ddr3_data = { |
| 45 | .datardsratio0 = 0x81204812, |
| 46 | .datawdsratio0 = 0, |
| 47 | .datafwsratio0 = 0x8020080, |
| 48 | .datawrsratio0 = 0x4010040, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 49 | }; |
| 50 | |
| 51 | struct cmd_control pxm2_ddr3_cmd_ctrl_data = { |
| 52 | .cmd0csratio = 0x80, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 53 | .cmd0iclkout = 0, |
| 54 | .cmd1csratio = 0x80, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 55 | .cmd1iclkout = 0, |
| 56 | .cmd2csratio = 0x80, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 57 | .cmd2iclkout = 0, |
| 58 | }; |
| 59 | |
Lokesh Vutla | 303b267 | 2013-12-10 15:02:21 +0530 | [diff] [blame] | 60 | const struct ctrl_ioregs ioregs = { |
Egli, Samuel | 121636f | 2014-04-24 17:57:52 +0200 | [diff] [blame] | 61 | .cm0ioctl = DDR_IOCTRL_VAL, |
| 62 | .cm1ioctl = DDR_IOCTRL_VAL, |
| 63 | .cm2ioctl = DDR_IOCTRL_VAL, |
| 64 | .dt0ioctl = DDR_IOCTRL_VAL, |
| 65 | .dt1ioctl = DDR_IOCTRL_VAL, |
Lokesh Vutla | 303b267 | 2013-12-10 15:02:21 +0530 | [diff] [blame] | 66 | }; |
| 67 | |
| 68 | config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 69 | &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0); |
| 70 | } |
| 71 | |
| 72 | /* |
| 73 | * voltage switching for MPU frequency switching. |
| 74 | * @module = mpu - 0, core - 1 |
| 75 | * @vddx_op_vol_sel = vdd voltage to set |
| 76 | */ |
| 77 | |
| 78 | #define MPU 0 |
| 79 | #define CORE 1 |
| 80 | |
| 81 | int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel) |
| 82 | { |
| 83 | uchar buf[4]; |
| 84 | unsigned int reg_offset; |
| 85 | |
| 86 | if (module == MPU) |
| 87 | reg_offset = PMIC_VDD1_OP_REG; |
| 88 | else |
| 89 | reg_offset = PMIC_VDD2_OP_REG; |
| 90 | |
| 91 | /* Select VDDx OP */ |
| 92 | if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) |
| 93 | return 1; |
| 94 | |
| 95 | buf[0] &= ~PMIC_OP_REG_CMD_MASK; |
| 96 | |
| 97 | if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) |
| 98 | return 1; |
| 99 | |
| 100 | /* Configure VDDx OP Voltage */ |
| 101 | if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) |
| 102 | return 1; |
| 103 | |
| 104 | buf[0] &= ~PMIC_OP_REG_SEL_MASK; |
| 105 | buf[0] |= vddx_op_vol_sel; |
| 106 | |
| 107 | if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) |
| 108 | return 1; |
| 109 | |
| 110 | if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) |
| 111 | return 1; |
| 112 | |
| 113 | if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel) |
| 114 | return 1; |
| 115 | |
| 116 | return 0; |
| 117 | } |
| 118 | |
| 119 | #define OSC (V_OSCK/1000000) |
| 120 | |
| 121 | const struct dpll_params dpll_mpu_pxm2 = { |
| 122 | 720, OSC-1, 1, -1, -1, -1, -1}; |
| 123 | |
Enrico Leto | 2e74050 | 2024-01-24 15:43:53 +0100 | [diff] [blame] | 124 | void spl_draco_board_init(void) |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 125 | { |
| 126 | uchar buf[4]; |
| 127 | /* |
| 128 | * pxm2 PMIC code. All boards currently want an MPU voltage |
| 129 | * of 1.2625V and CORE voltage of 1.1375V to operate at |
| 130 | * 720MHz. |
| 131 | */ |
| 132 | if (i2c_probe(PMIC_CTRL_I2C_ADDR)) |
| 133 | return; |
| 134 | |
| 135 | /* VDD1/2 voltage selection register access by control i/f */ |
| 136 | if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) |
| 137 | return; |
| 138 | |
| 139 | buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C; |
| 140 | |
| 141 | if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) |
| 142 | return; |
| 143 | |
| 144 | /* Frequency switching for OPP 120 */ |
| 145 | if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) || |
| 146 | voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) { |
| 147 | printf("voltage update failed\n"); |
| 148 | } |
| 149 | } |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 150 | |
Enrico Leto | 2e74050 | 2024-01-24 15:43:53 +0100 | [diff] [blame] | 151 | int draco_read_eeprom(void) |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 152 | { |
| 153 | /* nothing ToDo here for this board */ |
| 154 | |
| 155 | return 0; |
| 156 | } |
Enrico Leto | 32f433f | 2024-01-24 15:43:50 +0100 | [diff] [blame] | 157 | #endif /* if def CONFIG_SPL_BUILD */ |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 158 | |
| 159 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
Simon Glass | e5cd9a4 | 2021-07-10 21:14:26 -0600 | [diff] [blame] | 160 | (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 161 | static void cpsw_control(int enabled) |
| 162 | { |
| 163 | /* VTP can be added here */ |
| 164 | |
| 165 | return; |
| 166 | } |
| 167 | |
| 168 | static struct cpsw_slave_data cpsw_slaves[] = { |
| 169 | { |
| 170 | .slave_reg_ofs = 0x208, |
| 171 | .sliver_reg_ofs = 0xd80, |
Mugunthan V N | 4944f37 | 2014-02-18 07:31:52 -0500 | [diff] [blame] | 172 | .phy_addr = 0, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 173 | .phy_if = PHY_INTERFACE_MODE_RMII, |
| 174 | }, |
| 175 | { |
| 176 | .slave_reg_ofs = 0x308, |
| 177 | .sliver_reg_ofs = 0xdc0, |
Mugunthan V N | 4944f37 | 2014-02-18 07:31:52 -0500 | [diff] [blame] | 178 | .phy_addr = 1, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 179 | .phy_if = PHY_INTERFACE_MODE_RMII, |
| 180 | }, |
| 181 | }; |
| 182 | |
| 183 | static struct cpsw_platform_data cpsw_data = { |
| 184 | .mdio_base = CPSW_MDIO_BASE, |
| 185 | .cpsw_base = CPSW_BASE, |
| 186 | .mdio_div = 0xff, |
| 187 | .channels = 4, |
| 188 | .cpdma_reg_ofs = 0x800, |
| 189 | .slaves = 1, |
| 190 | .slave_data = cpsw_slaves, |
| 191 | .ale_reg_ofs = 0xd00, |
| 192 | .ale_entries = 1024, |
| 193 | .host_port_reg_ofs = 0x108, |
| 194 | .hw_stats_reg_ofs = 0x900, |
| 195 | .bd_ram_ofs = 0x2000, |
| 196 | .mac_control = (1 << 5), |
| 197 | .control = cpsw_control, |
| 198 | .host_port_num = 0, |
| 199 | .version = CPSW_CTRL_VERSION_2, |
| 200 | }; |
| 201 | #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ |
| 202 | |
| 203 | #if defined(CONFIG_DRIVER_TI_CPSW) || \ |
Paul Kocialkowski | f34dfcb | 2015-08-04 17:04:06 +0200 | [diff] [blame] | 204 | (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 205 | int board_eth_init(struct bd_info *bis) |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 206 | { |
| 207 | int n = 0; |
| 208 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
Simon Glass | e5cd9a4 | 2021-07-10 21:14:26 -0600 | [diff] [blame] | 209 | (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 210 | struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
| 211 | #ifdef CONFIG_FACTORYSET |
| 212 | int rv; |
Joe Hershberger | 8ecdbed | 2015-04-08 01:41:04 -0500 | [diff] [blame] | 213 | if (!is_valid_ethaddr(factory_dat.mac)) |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 214 | printf("Error: no valid mac address\n"); |
| 215 | else |
Simon Glass | 8551d55 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 216 | eth_env_set_enetaddr("ethaddr", factory_dat.mac); |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 217 | #endif /* #ifdef CONFIG_FACTORYSET */ |
| 218 | |
| 219 | /* Set rgmii mode and enable rmii clock to be sourced from chip */ |
Heiko Schocher | 9603afb | 2014-11-05 10:23:21 +0100 | [diff] [blame] | 220 | writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 221 | |
| 222 | rv = cpsw_register(&cpsw_data); |
| 223 | if (rv < 0) |
| 224 | printf("Error %d registering CPSW switch\n", rv); |
| 225 | else |
| 226 | n += rv; |
| 227 | #endif |
| 228 | return n; |
| 229 | } |
| 230 | #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ |
| 231 | |
Heiko Schocher | faf2dc6 | 2014-11-18 11:51:06 +0100 | [diff] [blame] | 232 | #ifdef CONFIG_BOARD_LATE_INIT |
| 233 | int board_late_init(void) |
| 234 | { |
| 235 | int ret; |
| 236 | |
| 237 | omap_nand_switch_ecc(1, 8); |
| 238 | |
| 239 | #ifdef CONFIG_FACTORYSET |
| 240 | if (factory_dat.asn[0] != 0) { |
| 241 | char tmp[2 * MAX_STRING_LENGTH + 2]; |
| 242 | |
| 243 | if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0) |
| 244 | factory_dat.pxm50 = 1; |
| 245 | else |
| 246 | factory_dat.pxm50 = 0; |
| 247 | sprintf(tmp, "%s_%s", factory_dat.asn, |
| 248 | factory_dat.comp_version); |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 249 | ret = env_set("boardid", tmp); |
Heiko Schocher | faf2dc6 | 2014-11-18 11:51:06 +0100 | [diff] [blame] | 250 | if (ret) |
| 251 | printf("error setting board id\n"); |
| 252 | } else { |
| 253 | factory_dat.pxm50 = 1; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 254 | ret = env_set("boardid", "PXM50_1.0"); |
Heiko Schocher | faf2dc6 | 2014-11-18 11:51:06 +0100 | [diff] [blame] | 255 | if (ret) |
| 256 | printf("error setting board id\n"); |
| 257 | } |
| 258 | debug("PXM50: %d\n", factory_dat.pxm50); |
| 259 | #endif |
| 260 | |
| 261 | return 0; |
| 262 | } |
| 263 | #endif |