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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Heiko Schocher499c4982013-08-19 16:39:01 +02002/*
3 * Board functions for TI AM335X based pxm2 board
4 * (C) Copyright 2013 Siemens Schweiz AG
5 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 *
7 * Based on:
8 * u-boot:/board/ti/am335x/board.c
9 *
10 * Board functions for TI AM335X based boards
11 *
Nishanth Menoneaa39c62023-11-01 15:56:03 -050012 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
Heiko Schocher499c4982013-08-19 16:39:01 +020013 */
14
15#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060016#include <env.h>
Heiko Schocher499c4982013-08-19 16:39:01 +020017#include <errno.h>
Simon Glassa7b51302019-11-14 12:57:46 -070018#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060019#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -070020#include <malloc.h>
Simon Glass274e0b02020-05-10 11:39:56 -060021#include <net.h>
Heiko Schocher499c4982013-08-19 16:39:01 +020022#include <spl.h>
23#include <asm/arch/cpu.h>
24#include <asm/arch/hardware.h>
25#include <asm/arch/omap.h>
26#include <asm/arch/ddr_defs.h>
27#include <asm/arch/clock.h>
28#include <asm/arch/gpio.h>
29#include <asm/arch/mmc_host_def.h>
30#include <asm/arch/sys_proto.h>
Heiko Schocher499c4982013-08-19 16:39:01 +020031#include <asm/io.h>
32#include <asm/emif.h>
33#include <asm/gpio.h>
34#include <i2c.h>
35#include <miiphy.h>
36#include <cpsw.h>
37#include <watchdog.h>
38#include "board.h"
Enrico Leto096bfdc2024-01-24 15:43:49 +010039#include "../common/eeprom.h"
Heiko Schocher499c4982013-08-19 16:39:01 +020040#include "../common/factoryset.h"
41#include "pmic.h"
42#include <nand.h>
43#include <bmp_layout.h>
44
Heiko Schocher499c4982013-08-19 16:39:01 +020045#ifdef CONFIG_SPL_BUILD
46static void board_init_ddr(void)
47{
48struct emif_regs pxm2_ddr3_emif_reg_data = {
49 .sdram_config = 0x41805332,
50 .sdram_tim1 = 0x666b3c9,
51 .sdram_tim2 = 0x243631ca,
52 .sdram_tim3 = 0x33f,
53 .emif_ddr_phy_ctlr_1 = 0x100005,
54 .zq_config = 0,
55 .ref_ctrl = 0x81a,
56};
57
58struct ddr_data pxm2_ddr3_data = {
59 .datardsratio0 = 0x81204812,
60 .datawdsratio0 = 0,
61 .datafwsratio0 = 0x8020080,
62 .datawrsratio0 = 0x4010040,
Heiko Schocher499c4982013-08-19 16:39:01 +020063};
64
65struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
66 .cmd0csratio = 0x80,
Heiko Schocher499c4982013-08-19 16:39:01 +020067 .cmd0iclkout = 0,
68 .cmd1csratio = 0x80,
Heiko Schocher499c4982013-08-19 16:39:01 +020069 .cmd1iclkout = 0,
70 .cmd2csratio = 0x80,
Heiko Schocher499c4982013-08-19 16:39:01 +020071 .cmd2iclkout = 0,
72};
73
Lokesh Vutla303b2672013-12-10 15:02:21 +053074const struct ctrl_ioregs ioregs = {
Egli, Samuel121636f2014-04-24 17:57:52 +020075 .cm0ioctl = DDR_IOCTRL_VAL,
76 .cm1ioctl = DDR_IOCTRL_VAL,
77 .cm2ioctl = DDR_IOCTRL_VAL,
78 .dt0ioctl = DDR_IOCTRL_VAL,
79 .dt1ioctl = DDR_IOCTRL_VAL,
Lokesh Vutla303b2672013-12-10 15:02:21 +053080};
81
82 config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
Heiko Schocher499c4982013-08-19 16:39:01 +020083 &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
84}
85
86/*
87 * voltage switching for MPU frequency switching.
88 * @module = mpu - 0, core - 1
89 * @vddx_op_vol_sel = vdd voltage to set
90 */
91
92#define MPU 0
93#define CORE 1
94
95int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
96{
97 uchar buf[4];
98 unsigned int reg_offset;
99
100 if (module == MPU)
101 reg_offset = PMIC_VDD1_OP_REG;
102 else
103 reg_offset = PMIC_VDD2_OP_REG;
104
105 /* Select VDDx OP */
106 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
107 return 1;
108
109 buf[0] &= ~PMIC_OP_REG_CMD_MASK;
110
111 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
112 return 1;
113
114 /* Configure VDDx OP Voltage */
115 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
116 return 1;
117
118 buf[0] &= ~PMIC_OP_REG_SEL_MASK;
119 buf[0] |= vddx_op_vol_sel;
120
121 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
122 return 1;
123
124 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
125 return 1;
126
127 if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
128 return 1;
129
130 return 0;
131}
132
133#define OSC (V_OSCK/1000000)
134
135const struct dpll_params dpll_mpu_pxm2 = {
136 720, OSC-1, 1, -1, -1, -1, -1};
137
138void spl_siemens_board_init(void)
139{
140 uchar buf[4];
141 /*
142 * pxm2 PMIC code. All boards currently want an MPU voltage
143 * of 1.2625V and CORE voltage of 1.1375V to operate at
144 * 720MHz.
145 */
146 if (i2c_probe(PMIC_CTRL_I2C_ADDR))
147 return;
148
149 /* VDD1/2 voltage selection register access by control i/f */
150 if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
151 return;
152
153 buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
154
155 if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
156 return;
157
158 /* Frequency switching for OPP 120 */
159 if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
160 voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
161 printf("voltage update failed\n");
162 }
163}
164#endif /* if def CONFIG_SPL_BUILD */
165
166int read_eeprom(void)
167{
168 /* nothing ToDo here for this board */
169
170 return 0;
171}
172
173#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
Simon Glasse5cd9a42021-07-10 21:14:26 -0600174 (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
Heiko Schocher499c4982013-08-19 16:39:01 +0200175static void cpsw_control(int enabled)
176{
177 /* VTP can be added here */
178
179 return;
180}
181
182static struct cpsw_slave_data cpsw_slaves[] = {
183 {
184 .slave_reg_ofs = 0x208,
185 .sliver_reg_ofs = 0xd80,
Mugunthan V N4944f372014-02-18 07:31:52 -0500186 .phy_addr = 0,
Heiko Schocher499c4982013-08-19 16:39:01 +0200187 .phy_if = PHY_INTERFACE_MODE_RMII,
188 },
189 {
190 .slave_reg_ofs = 0x308,
191 .sliver_reg_ofs = 0xdc0,
Mugunthan V N4944f372014-02-18 07:31:52 -0500192 .phy_addr = 1,
Heiko Schocher499c4982013-08-19 16:39:01 +0200193 .phy_if = PHY_INTERFACE_MODE_RMII,
194 },
195};
196
197static struct cpsw_platform_data cpsw_data = {
198 .mdio_base = CPSW_MDIO_BASE,
199 .cpsw_base = CPSW_BASE,
200 .mdio_div = 0xff,
201 .channels = 4,
202 .cpdma_reg_ofs = 0x800,
203 .slaves = 1,
204 .slave_data = cpsw_slaves,
205 .ale_reg_ofs = 0xd00,
206 .ale_entries = 1024,
207 .host_port_reg_ofs = 0x108,
208 .hw_stats_reg_ofs = 0x900,
209 .bd_ram_ofs = 0x2000,
210 .mac_control = (1 << 5),
211 .control = cpsw_control,
212 .host_port_num = 0,
213 .version = CPSW_CTRL_VERSION_2,
214};
215#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
216
217#if defined(CONFIG_DRIVER_TI_CPSW) || \
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +0200218 (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900219int board_eth_init(struct bd_info *bis)
Heiko Schocher499c4982013-08-19 16:39:01 +0200220{
221 int n = 0;
222#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
Simon Glasse5cd9a42021-07-10 21:14:26 -0600223 (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
Heiko Schocher499c4982013-08-19 16:39:01 +0200224 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
225#ifdef CONFIG_FACTORYSET
226 int rv;
Joe Hershberger8ecdbed2015-04-08 01:41:04 -0500227 if (!is_valid_ethaddr(factory_dat.mac))
Heiko Schocher499c4982013-08-19 16:39:01 +0200228 printf("Error: no valid mac address\n");
229 else
Simon Glass8551d552017-08-03 12:22:11 -0600230 eth_env_set_enetaddr("ethaddr", factory_dat.mac);
Heiko Schocher499c4982013-08-19 16:39:01 +0200231#endif /* #ifdef CONFIG_FACTORYSET */
232
233 /* Set rgmii mode and enable rmii clock to be sourced from chip */
Heiko Schocher9603afb2014-11-05 10:23:21 +0100234 writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
Heiko Schocher499c4982013-08-19 16:39:01 +0200235
236 rv = cpsw_register(&cpsw_data);
237 if (rv < 0)
238 printf("Error %d registering CPSW switch\n", rv);
239 else
240 n += rv;
241#endif
242 return n;
243}
244#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
245
Heiko Schocherfaf2dc62014-11-18 11:51:06 +0100246#ifdef CONFIG_BOARD_LATE_INIT
247int board_late_init(void)
248{
249 int ret;
250
251 omap_nand_switch_ecc(1, 8);
252
253#ifdef CONFIG_FACTORYSET
254 if (factory_dat.asn[0] != 0) {
255 char tmp[2 * MAX_STRING_LENGTH + 2];
256
257 if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
258 factory_dat.pxm50 = 1;
259 else
260 factory_dat.pxm50 = 0;
261 sprintf(tmp, "%s_%s", factory_dat.asn,
262 factory_dat.comp_version);
Simon Glass6a38e412017-08-03 12:22:09 -0600263 ret = env_set("boardid", tmp);
Heiko Schocherfaf2dc62014-11-18 11:51:06 +0100264 if (ret)
265 printf("error setting board id\n");
266 } else {
267 factory_dat.pxm50 = 1;
Simon Glass6a38e412017-08-03 12:22:09 -0600268 ret = env_set("boardid", "PXM50_1.0");
Heiko Schocherfaf2dc62014-11-18 11:51:06 +0100269 if (ret)
270 printf("error setting board id\n");
271 }
272 debug("PXM50: %d\n", factory_dat.pxm50);
273#endif
274
275 return 0;
276}
277#endif
278
Heiko Schocher499c4982013-08-19 16:39:01 +0200279#include "../common/board.c"