blob: b59d64f93ef3d36724e66d6066718d61cbad77ef [file] [log] [blame]
Hannes Schmelzer82088482019-08-01 07:04:46 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * mux.c
4 *
5 * Pinmux Setting for B&R BRSMARC1 Board (HW-Rev. 1)
6 *
7 * Copyright (C) 2017 Hannes Schmelzer <hannes.schmelzer@br-automation.com>
8 * B&R Industrial Automation GmbH - http://www.br-automation.com
9 *
10 */
11
Hannes Schmelzer82088482019-08-01 07:04:46 +020012#include <asm/arch/sys_proto.h>
13#include <asm/arch/hardware.h>
14#include <asm/arch/mux.h>
15#include <asm/io.h>
16#include <i2c.h>
17
18static struct module_pin_mux spi0_pin_mux[] = {
19 /* SPI0_SCLK */
20 {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
21 /* SPI0_D0 */
22 {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
23 /* SPI0_D1 */
24 {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
25 /* SPI0_CS0 */
26 {OFFSET(spi0_cs0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
27 /* SPI0_CS1 */
28 {OFFSET(spi0_cs1), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
29 {-1},
30};
31
32static struct module_pin_mux spi1_pin_mux[] = {
33 /* SPI1_SCLK */
34 {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
35 /* SPI1_D0 */
36 {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
37 /* SPI1_D1 */
38 {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
39 /* SPI1_CS0 */
40 {OFFSET(mcasp0_ahclkr), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
41 /* SPI1_CS1 */
42 {OFFSET(xdma_event_intr0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
43 {-1},
44};
45
46static struct module_pin_mux dcan0_pin_mux[] = {
47 /* DCAN0 TX */
48 {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
49 /* DCAN0 RX */
50 {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
51 {-1},
52};
53
54static struct module_pin_mux dcan1_pin_mux[] = {
55 /* DCAN1 TX */
56 {OFFSET(uart0_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
57 /* DCAN1 RX */
58 {OFFSET(uart0_rtsn), MODE(2) | RXACTIVE},
59 {-1},
60};
61
62static struct module_pin_mux gpios[] = {
63 /* GPIO0_7 - LVDS_EN */
64 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
65 /* GPIO0_20 - BKLT_PWM (timer7) */
66 {OFFSET(xdma_event_intr1), (MODE(4) | PULLUDDIS | PULLDOWN_EN)},
67 /* GPIO2_4 - DISON */
68 {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
69 /* GPIO1_24 - RGB_EN */
70 {OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
71 /* GPIO1_28 - nPD */
72 {OFFSET(gpmc_be1n), (MODE(7) | PULLUDEN | PULLUP_EN)},
73 /* GPIO2_5 - Watchdog */
74 {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
75 /* GPIO2_0 - ResetOut */
76 {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)},
77 /* GPIO2_2 - BKLT_EN */
78 {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
79 /* GPIO1_17 - GPIO0 */
80 {OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS | RXACTIVE)},
81 /* GPIO1_18 - GPIO1 */
82 {OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS | RXACTIVE)},
83 /* GPIO1_19 - GPIO2 */
84 {OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS | RXACTIVE)},
85 /* GPIO1_22 - GPIO3 */
86 {OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS | RXACTIVE)},
87 /* GPIO1_23 - GPIO4 */
88 {OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS | RXACTIVE)},
89 /* GPIO1_25 - GPIO5 */
90 {OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS | RXACTIVE)},
91 /* GPIO3_7 - GPIO6 */
92 {OFFSET(emu0), (MODE(7) | PULLUDDIS | RXACTIVE)},
93 /* GPIO3_8 - GPIO7 */
94 {OFFSET(emu1), (MODE(7) | PULLUDDIS | RXACTIVE)},
95 /* GPIO3_18 - GPIO8 */
96 {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
97 /* GPIO3_19 - GPIO9 */
98 {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDDIS | RXACTIVE)},
99 /* GPIO3_20 - GPIO10 */
100 {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
101 /* GPIO3_21 - GPIO11 */
102 {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDDIS | RXACTIVE)},
103 /* GPIO2_28 - DRAM-strapping */
104 {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN)},
105 /* GPIO2_4 - not routed (Pin U6) */
106 {OFFSET(gpmc_wen), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
107 /* GPIO2_5 - not routed (Pin T6) */
108 {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
109 /* GPIO2_28 - not routed (Pin G15) */
110 {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
111 /* GPIO3_18 - not routed (Pin B12) */
112 {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
113 {-1},
114};
115
116static struct module_pin_mux uart0_pin_mux[] = {
117 /* UART0_RXD */
118 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
119 /* UART0_TXD */
120 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
121 {-1},
122};
123
124static struct module_pin_mux uart234_pin_mux[] = {
125 /* UART2_RXD */
126 {OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
127 /* UART2_TXD */
128 {OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)},
129
130 /* UART3_RXD */
131 {OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
132 /* UART3_TXD */
133 {OFFSET(mmc0_dat0), (MODE(3) | PULLUDEN)},
134 /* UART3_RTS */
135 {OFFSET(mmc0_cmd), (MODE(2) | PULLUDEN)},
136 /* UART3_CTS */
137 {OFFSET(mmc0_clk), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},
138
139 /* UART4_RXD */
140 {OFFSET(mii1_txd3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
141 /* UART4_TXD */
142 {OFFSET(mii1_txd2), (MODE(3) | PULLUDEN)},
143 /* UART4_RTS */
144 {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN)},
145 /* UART4_CTS */
146 {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
147
148 {-1},
149};
150
151static struct module_pin_mux i2c_pin_mux[] = {
152 /* I2C0_DATA */
153 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
154 /* I2C0_SCLK */
155 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
156 /* I2C1_DATA */
157 {OFFSET(uart1_rxd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
158 /* I2C1_SCLK */
159 {OFFSET(uart1_txd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
160 {-1},
161};
162
163static struct module_pin_mux eth_pin_mux[] = {
164 /* ETH1 */
165 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* ETH1_REFCLK */
166 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRSDV */
167 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXER */
168 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
169 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
170 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
171 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
172 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
173
174 /* ETH2 */
175 {OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* ETH2_REFCLK */
176 {OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRSDV */
177 {OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXER */
178 {OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */
179 {OFFSET(gpmc_a11), MODE(3) | RXACTIVE}, /* RMII2_RXD0 */
180 {OFFSET(gpmc_a10), MODE(3) | RXACTIVE}, /* RMII2_RXD1 */
181 {OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */
182 {OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */
183
184 /* gpio2_19, gpio 3_4, not connected on board */
185 {OFFSET(mii1_rxd2), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
186 {OFFSET(mii1_rxdv), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
187
188 /* ETH Management */
189 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
190 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
191
192 {-1},
193};
194
195static struct module_pin_mux mmc1_pin_mux[] = {
196 {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
197 {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
198 {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
199 {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
200 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
201 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
202 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
203 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
204 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
205 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
206 {-1},
207};
208
209static struct module_pin_mux lcd_pin_mux[] = {
210 {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
211 {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
212 {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
213 {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
214 {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
215 {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
216 {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
217 {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
218 {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
219 {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
220 {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
221 {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
222 {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
223 {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
224 {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
225 {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
226
227 {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
228 {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
229 {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
230 {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
231 {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
232 {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
233 {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
234 {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
235
236 {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
237 {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
238 {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
239 {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
240
241 {-1},
242};
243
244void enable_uart0_pin_mux(void)
245{
246 configure_module_pin_mux(uart0_pin_mux);
247}
248
249void enable_i2c_pin_mux(void)
250{
251 configure_module_pin_mux(i2c_pin_mux);
252}
253
254void enable_board_pin_mux(void)
255{
256 configure_module_pin_mux(eth_pin_mux);
257 configure_module_pin_mux(spi0_pin_mux);
258 configure_module_pin_mux(spi1_pin_mux);
259 configure_module_pin_mux(dcan0_pin_mux);
260 configure_module_pin_mux(dcan1_pin_mux);
261 configure_module_pin_mux(uart234_pin_mux);
262 configure_module_pin_mux(mmc1_pin_mux);
263 configure_module_pin_mux(lcd_pin_mux);
264 configure_module_pin_mux(gpios);
265}