Hannes Schmelzer | 8208848 | 2019-08-01 07:04:46 +0200 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * mux.c |
| 4 | * |
| 5 | * Pinmux Setting for B&R BRSMARC1 Board (HW-Rev. 1) |
| 6 | * |
| 7 | * Copyright (C) 2017 Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
| 8 | * B&R Industrial Automation GmbH - http://www.br-automation.com |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | #include <common.h> |
| 13 | #include <asm/arch/sys_proto.h> |
| 14 | #include <asm/arch/hardware.h> |
| 15 | #include <asm/arch/mux.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <i2c.h> |
| 18 | |
| 19 | static struct module_pin_mux spi0_pin_mux[] = { |
| 20 | /* SPI0_SCLK */ |
| 21 | {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE}, |
| 22 | /* SPI0_D0 */ |
| 23 | {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE}, |
| 24 | /* SPI0_D1 */ |
| 25 | {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE}, |
| 26 | /* SPI0_CS0 */ |
| 27 | {OFFSET(spi0_cs0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE}, |
| 28 | /* SPI0_CS1 */ |
| 29 | {OFFSET(spi0_cs1), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE}, |
| 30 | {-1}, |
| 31 | }; |
| 32 | |
| 33 | static struct module_pin_mux spi1_pin_mux[] = { |
| 34 | /* SPI1_SCLK */ |
| 35 | {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE}, |
| 36 | /* SPI1_D0 */ |
| 37 | {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE}, |
| 38 | /* SPI1_D1 */ |
| 39 | {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE}, |
| 40 | /* SPI1_CS0 */ |
| 41 | {OFFSET(mcasp0_ahclkr), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE}, |
| 42 | /* SPI1_CS1 */ |
| 43 | {OFFSET(xdma_event_intr0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE}, |
| 44 | {-1}, |
| 45 | }; |
| 46 | |
| 47 | static struct module_pin_mux dcan0_pin_mux[] = { |
| 48 | /* DCAN0 TX */ |
| 49 | {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN}, |
| 50 | /* DCAN0 RX */ |
| 51 | {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE}, |
| 52 | {-1}, |
| 53 | }; |
| 54 | |
| 55 | static struct module_pin_mux dcan1_pin_mux[] = { |
| 56 | /* DCAN1 TX */ |
| 57 | {OFFSET(uart0_ctsn), MODE(2) | PULLUDEN | PULLUP_EN}, |
| 58 | /* DCAN1 RX */ |
| 59 | {OFFSET(uart0_rtsn), MODE(2) | RXACTIVE}, |
| 60 | {-1}, |
| 61 | }; |
| 62 | |
| 63 | static struct module_pin_mux gpios[] = { |
| 64 | /* GPIO0_7 - LVDS_EN */ |
| 65 | {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | PULLDOWN_EN)}, |
| 66 | /* GPIO0_20 - BKLT_PWM (timer7) */ |
| 67 | {OFFSET(xdma_event_intr1), (MODE(4) | PULLUDDIS | PULLDOWN_EN)}, |
| 68 | /* GPIO2_4 - DISON */ |
| 69 | {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS | PULLDOWN_EN)}, |
| 70 | /* GPIO1_24 - RGB_EN */ |
| 71 | {OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS | PULLDOWN_EN)}, |
| 72 | /* GPIO1_28 - nPD */ |
| 73 | {OFFSET(gpmc_be1n), (MODE(7) | PULLUDEN | PULLUP_EN)}, |
| 74 | /* GPIO2_5 - Watchdog */ |
| 75 | {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS | PULLDOWN_EN)}, |
| 76 | /* GPIO2_0 - ResetOut */ |
| 77 | {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)}, |
| 78 | /* GPIO2_2 - BKLT_EN */ |
| 79 | {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | PULLDOWN_EN)}, |
| 80 | /* GPIO1_17 - GPIO0 */ |
| 81 | {OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS | RXACTIVE)}, |
| 82 | /* GPIO1_18 - GPIO1 */ |
| 83 | {OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS | RXACTIVE)}, |
| 84 | /* GPIO1_19 - GPIO2 */ |
| 85 | {OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS | RXACTIVE)}, |
| 86 | /* GPIO1_22 - GPIO3 */ |
| 87 | {OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS | RXACTIVE)}, |
| 88 | /* GPIO1_23 - GPIO4 */ |
| 89 | {OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS | RXACTIVE)}, |
| 90 | /* GPIO1_25 - GPIO5 */ |
| 91 | {OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS | RXACTIVE)}, |
| 92 | /* GPIO3_7 - GPIO6 */ |
| 93 | {OFFSET(emu0), (MODE(7) | PULLUDDIS | RXACTIVE)}, |
| 94 | /* GPIO3_8 - GPIO7 */ |
| 95 | {OFFSET(emu1), (MODE(7) | PULLUDDIS | RXACTIVE)}, |
| 96 | /* GPIO3_18 - GPIO8 */ |
| 97 | {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS | RXACTIVE)}, |
| 98 | /* GPIO3_19 - GPIO9 */ |
| 99 | {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDDIS | RXACTIVE)}, |
| 100 | /* GPIO3_20 - GPIO10 */ |
| 101 | {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDDIS | RXACTIVE)}, |
| 102 | /* GPIO3_21 - GPIO11 */ |
| 103 | {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDDIS | RXACTIVE)}, |
| 104 | /* GPIO2_28 - DRAM-strapping */ |
| 105 | {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN)}, |
| 106 | /* GPIO2_4 - not routed (Pin U6) */ |
| 107 | {OFFSET(gpmc_wen), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, |
| 108 | /* GPIO2_5 - not routed (Pin T6) */ |
| 109 | {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, |
| 110 | /* GPIO2_28 - not routed (Pin G15) */ |
| 111 | {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, |
| 112 | /* GPIO3_18 - not routed (Pin B12) */ |
| 113 | {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, |
| 114 | {-1}, |
| 115 | }; |
| 116 | |
| 117 | static struct module_pin_mux uart0_pin_mux[] = { |
| 118 | /* UART0_RXD */ |
| 119 | {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, |
| 120 | /* UART0_TXD */ |
| 121 | {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, |
| 122 | {-1}, |
| 123 | }; |
| 124 | |
| 125 | static struct module_pin_mux uart234_pin_mux[] = { |
| 126 | /* UART2_RXD */ |
| 127 | {OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)}, |
| 128 | /* UART2_TXD */ |
| 129 | {OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)}, |
| 130 | |
| 131 | /* UART3_RXD */ |
| 132 | {OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)}, |
| 133 | /* UART3_TXD */ |
| 134 | {OFFSET(mmc0_dat0), (MODE(3) | PULLUDEN)}, |
| 135 | /* UART3_RTS */ |
| 136 | {OFFSET(mmc0_cmd), (MODE(2) | PULLUDEN)}, |
| 137 | /* UART3_CTS */ |
| 138 | {OFFSET(mmc0_clk), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)}, |
| 139 | |
| 140 | /* UART4_RXD */ |
| 141 | {OFFSET(mii1_txd3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)}, |
| 142 | /* UART4_TXD */ |
| 143 | {OFFSET(mii1_txd2), (MODE(3) | PULLUDEN)}, |
| 144 | /* UART4_RTS */ |
| 145 | {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN)}, |
| 146 | /* UART4_CTS */ |
| 147 | {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)}, |
| 148 | |
| 149 | {-1}, |
| 150 | }; |
| 151 | |
| 152 | static struct module_pin_mux i2c_pin_mux[] = { |
| 153 | /* I2C0_DATA */ |
| 154 | {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, |
| 155 | /* I2C0_SCLK */ |
| 156 | {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, |
| 157 | /* I2C1_DATA */ |
| 158 | {OFFSET(uart1_rxd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, |
| 159 | /* I2C1_SCLK */ |
| 160 | {OFFSET(uart1_txd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, |
| 161 | {-1}, |
| 162 | }; |
| 163 | |
| 164 | static struct module_pin_mux eth_pin_mux[] = { |
| 165 | /* ETH1 */ |
| 166 | {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* ETH1_REFCLK */ |
| 167 | {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRSDV */ |
| 168 | {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXER */ |
| 169 | {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ |
| 170 | {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */ |
| 171 | {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */ |
| 172 | {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */ |
| 173 | {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */ |
| 174 | |
| 175 | /* ETH2 */ |
| 176 | {OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* ETH2_REFCLK */ |
| 177 | {OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRSDV */ |
| 178 | {OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXER */ |
| 179 | {OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */ |
| 180 | {OFFSET(gpmc_a11), MODE(3) | RXACTIVE}, /* RMII2_RXD0 */ |
| 181 | {OFFSET(gpmc_a10), MODE(3) | RXACTIVE}, /* RMII2_RXD1 */ |
| 182 | {OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */ |
| 183 | {OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */ |
| 184 | |
| 185 | /* gpio2_19, gpio 3_4, not connected on board */ |
| 186 | {OFFSET(mii1_rxd2), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE}, |
| 187 | {OFFSET(mii1_rxdv), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE}, |
| 188 | |
| 189 | /* ETH Management */ |
| 190 | {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ |
| 191 | {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ |
| 192 | |
| 193 | {-1}, |
| 194 | }; |
| 195 | |
| 196 | static struct module_pin_mux mmc1_pin_mux[] = { |
| 197 | {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ |
| 198 | {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ |
| 199 | {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ |
| 200 | {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ |
| 201 | {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ |
| 202 | {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ |
| 203 | {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ |
| 204 | {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ |
| 205 | {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ |
| 206 | {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ |
| 207 | {-1}, |
| 208 | }; |
| 209 | |
| 210 | static struct module_pin_mux lcd_pin_mux[] = { |
| 211 | {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ |
| 212 | {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ |
| 213 | {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ |
| 214 | {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ |
| 215 | {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ |
| 216 | {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ |
| 217 | {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ |
| 218 | {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ |
| 219 | {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ |
| 220 | {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ |
| 221 | {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ |
| 222 | {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ |
| 223 | {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ |
| 224 | {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ |
| 225 | {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ |
| 226 | {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ |
| 227 | |
| 228 | {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ |
| 229 | {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ |
| 230 | {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ |
| 231 | {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ |
| 232 | {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ |
| 233 | {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ |
| 234 | {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ |
| 235 | {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ |
| 236 | |
| 237 | {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ |
| 238 | {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ |
| 239 | {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ |
| 240 | {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ |
| 241 | |
| 242 | {-1}, |
| 243 | }; |
| 244 | |
| 245 | void enable_uart0_pin_mux(void) |
| 246 | { |
| 247 | configure_module_pin_mux(uart0_pin_mux); |
| 248 | } |
| 249 | |
| 250 | void enable_i2c_pin_mux(void) |
| 251 | { |
| 252 | configure_module_pin_mux(i2c_pin_mux); |
| 253 | } |
| 254 | |
| 255 | void enable_board_pin_mux(void) |
| 256 | { |
| 257 | configure_module_pin_mux(eth_pin_mux); |
| 258 | configure_module_pin_mux(spi0_pin_mux); |
| 259 | configure_module_pin_mux(spi1_pin_mux); |
| 260 | configure_module_pin_mux(dcan0_pin_mux); |
| 261 | configure_module_pin_mux(dcan1_pin_mux); |
| 262 | configure_module_pin_mux(uart234_pin_mux); |
| 263 | configure_module_pin_mux(mmc1_pin_mux); |
| 264 | configure_module_pin_mux(lcd_pin_mux); |
| 265 | configure_module_pin_mux(gpios); |
| 266 | } |