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git01.mediatek.com / filogic / uboot / 324cb4d73d2883138305686b6f013e9e84de580d / . / arch / arm / mach-stm32mp / stm32mp2 / stm32mp25x.c
blob: 7f896a0d65d2f5730bd7b5c7ce4b7a7a07a194ae [file] [log] [blame]
Patrice Chotardd29531c2023-10-27 16:43:04 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
2/*
3 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
4 */
5
6#define LOG_CATEGORY LOGC_ARCH
7
Patrice Chotardd29531c2023-10-27 16:43:04 +0200[diff] [blame]8#include <log.h>
9#include <syscon.h>
10#include <asm/io.h>
11#include <asm/arch/stm32.h>
12#include <asm/arch/sys_proto.h>
13
14/* SYSCFG register */
15#define SYSCFG_DEVICEID_OFFSET 0x6400
16#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
17#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
18#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16)
19#define SYSCFG_DEVICEID_REV_ID_SHIFT 16
20
21/* Device Part Number (RPN) = OTP9 */
22#define RPN_SHIFT 0
23#define RPN_MASK GENMASK(31, 0)
24
25/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines
26 * - 000: Custom package
27 * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm
28 * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm
29 * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
30 * - others: Reserved
31 */
32#define PKG_SHIFT 0
33#define PKG_MASK GENMASK(2, 0)
34
35static u32 read_deviceid(void)
36{
37 void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
38
39 return readl(syscfg + SYSCFG_DEVICEID_OFFSET);
40}
41
42u32 get_cpu_dev(void)
43{
44 return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT;
45}
46
47u32 get_cpu_rev(void)
48{
49 return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT;
50}
51
52/* Get Device Part Number (RPN) from OTP */
53u32 get_cpu_type(void)
54{
55 return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
56}
57
58/* Get Package options from OTP */
59u32 get_cpu_package(void)
60{
61 return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
62}
63
64int get_eth_nb(void)
65{
66 int nb_eth;
67
68 switch (get_cpu_type()) {
69 case CPU_STM32MP257Fxx:
70 fallthrough;
71 case CPU_STM32MP257Dxx:
72 fallthrough;
73 case CPU_STM32MP257Cxx:
74 fallthrough;
75 case CPU_STM32MP257Axx:
76 nb_eth = 5; /* dual ETH with TSN support */
77 break;
78 case CPU_STM32MP253Fxx:
79 fallthrough;
80 case CPU_STM32MP253Dxx:
81 fallthrough;
82 case CPU_STM32MP253Cxx:
83 fallthrough;
84 case CPU_STM32MP253Axx:
85 nb_eth = 2; /* dual ETH */
86 break;
87 case CPU_STM32MP251Fxx:
88 fallthrough;
89 case CPU_STM32MP251Dxx:
90 fallthrough;
91 case CPU_STM32MP251Cxx:
92 fallthrough;
93 case CPU_STM32MP251Axx:
94 nb_eth = 1; /* single ETH */
95 break;
96 default:
97 nb_eth = 0;
98 break;
99 }
100
101 return nb_eth;
102}
103
104void get_soc_name(char name[SOC_NAME_SIZE])
105{
106 char *cpu_s, *cpu_r, *package;
107
108 cpu_s = "????";
109 cpu_r = "?";
110 package = "??";
111 if (get_cpu_dev() == CPU_DEV_STM32MP25) {
112 switch (get_cpu_type()) {
113 case CPU_STM32MP257Fxx:
114 cpu_s = "257F";
115 break;
116 case CPU_STM32MP257Dxx:
117 cpu_s = "257D";
118 break;
119 case CPU_STM32MP257Cxx:
120 cpu_s = "257C";
121 break;
122 case CPU_STM32MP257Axx:
123 cpu_s = "257A";
124 break;
125 case CPU_STM32MP255Fxx:
126 cpu_s = "255F";
127 break;
128 case CPU_STM32MP255Dxx:
129 cpu_s = "255D";
130 break;
131 case CPU_STM32MP255Cxx:
132 cpu_s = "255C";
133 break;
134 case CPU_STM32MP255Axx:
135 cpu_s = "255A";
136 break;
137 case CPU_STM32MP253Fxx:
138 cpu_s = "253F";
139 break;
140 case CPU_STM32MP253Dxx:
141 cpu_s = "253D";
142 break;
143 case CPU_STM32MP253Cxx:
144 cpu_s = "253C";
145 break;
146 case CPU_STM32MP253Axx:
147 cpu_s = "253A";
148 break;
149 case CPU_STM32MP251Fxx:
150 cpu_s = "251F";
151 break;
152 case CPU_STM32MP251Dxx:
153 cpu_s = "251D";
154 break;
155 case CPU_STM32MP251Cxx:
156 cpu_s = "251C";
157 break;
158 case CPU_STM32MP251Axx:
159 cpu_s = "251A";
160 break;
161 default:
162 cpu_s = "25??";
163 break;
164 }
165 /* REVISION */
166 switch (get_cpu_rev()) {
167 case CPU_REV1:
168 cpu_r = "A";
169 break;
Yann Gautierbb5502a2024-01-15 15:05:45 +0100[diff] [blame]170 case CPU_REV2:
171 cpu_r = "B";
172 break;
Patrice Chotardd29531c2023-10-27 16:43:04 +0200[diff] [blame]173 default:
174 break;
175 }
176 /* PACKAGE */
177 switch (get_cpu_package()) {
178 case STM32MP25_PKG_CUSTOM:
179 package = "XX";
180 break;
181 case STM32MP25_PKG_AL_TBGA361:
182 package = "AL";
183 break;
184 case STM32MP25_PKG_AK_TBGA424:
185 package = "AK";
186 break;
187 case STM32MP25_PKG_AI_TBGA436:
188 package = "AI";
189 break;
190 default:
191 break;
192 }
193 }
194
195 snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r);
196}