arch/arm/dts/k3-am625.dtsi

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree Source for AM625 SoC family in Quad core configuration
 *
 * TRM: https://www.ti.com/lit/pdf/spruiv7
 *
 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include "k3-am62.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0: cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			reg = <0x000>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&L2_0>;
			operating-points-v2 = <&a53_opp_table>;
			clocks = <&k3_clks 135 0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			reg = <0x001>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&L2_0>;
			operating-points-v2 = <&a53_opp_table>;
			clocks = <&k3_clks 136 0>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53";
			reg = <0x002>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&L2_0>;
			operating-points-v2 = <&a53_opp_table>;
			clocks = <&k3_clks 137 0>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53";
			reg = <0x003>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&L2_0>;
			operating-points-v2 = <&a53_opp_table>;
			clocks = <&k3_clks 138 0>;
		};
	};

	a53_opp_table: opp-table {
		compatible = "operating-points-v2-ti-cpu";
		opp-shared;
		syscon = <&wkup_conf>;

		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			opp-supported-hw = <0x01 0x0007>;
			clock-latency-ns = <6000000>;
		};

		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			opp-supported-hw = <0x01 0x0007>;
			clock-latency-ns = <6000000>;
		};

		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-supported-hw = <0x01 0x0007>;
			clock-latency-ns = <6000000>;
		};

		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			opp-supported-hw = <0x01 0x0007>;
			clock-latency-ns = <6000000>;
		};

		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-supported-hw = <0x01 0x0006>;
			clock-latency-ns = <6000000>;
		};

		opp-1250000000 {
			opp-hz = /bits/ 64 <1250000000>;
			opp-supported-hw = <0x01 0x0004>;
			clock-latency-ns = <6000000>;
			opp-suspend;
		};
	};

	L2_0: l2-cache0 {
		compatible = "cache";
		cache-unified;
		cache-level = <2>;
		cache-size = <0x80000>;
		cache-line-size = <64>;
		cache-sets = <512>;
	};
};