| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Chin Liang See | cb35060 | 2014-03-04 22:13:53 -0600 | [diff] [blame] | 2 | /* |
| Jit Loon Lim | 977071e | 2024-03-12 22:01:03 +0800 | [diff] [blame] | 3 | * Copyright (C) 2013-2024 Altera Corporation <www.altera.com> |
| Chin Liang See | cb35060 | 2014-03-04 22:13:53 -0600 | [diff] [blame] | 4 | */ |
| 5 | |
| Ley Foon Tan | ec6f882 | 2017-04-26 02:44:33 +0800 | [diff] [blame] | 6 | #ifndef _CLOCK_MANAGER_H_ |
| 7 | #define _CLOCK_MANAGER_H_ |
| Chin Liang See | cb35060 | 2014-03-04 22:13:53 -0600 | [diff] [blame] | 8 | |
| Ley Foon Tan | 2669591 | 2019-11-08 10:38:21 +0800 | [diff] [blame] | 9 | phys_addr_t socfpga_get_clkmgr_addr(void); |
| 10 | |
| Simon Glass | 559f1a8 | 2020-05-10 11:40:12 -0600 | [diff] [blame] | 11 | #ifndef __ASSEMBLY__ |
| Ley Foon Tan | ec6f882 | 2017-04-26 02:44:33 +0800 | [diff] [blame] | 12 | void cm_wait_for_lock(u32 mask); |
| 13 | int cm_wait_for_fsm(void); |
| 14 | void cm_print_clock_quick_summary(void); |
| Siew Chin Lim | 8596188 | 2021-08-10 11:26:33 +0800 | [diff] [blame] | 15 | unsigned long cm_get_mpu_clk_hz(void); |
| Siew Chin Lim | fa2cc49 | 2021-03-24 17:16:49 +0800 | [diff] [blame] | 16 | unsigned int cm_get_qspi_controller_clk_hz(void); |
| Siew Chin Lim | c1888b0 | 2021-03-24 17:16:50 +0800 | [diff] [blame] | 17 | |
| 18 | #if defined(CONFIG_TARGET_SOCFPGA_SOC64) |
| 19 | int cm_set_qspi_controller_clk_hz(u32 clk_hz); |
| 20 | #endif |
| Pavel Machek | 7c8d5a6 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 21 | #endif |
| 22 | |
| Ley Foon Tan | ec6f882 | 2017-04-26 02:44:33 +0800 | [diff] [blame] | 23 | #if defined(CONFIG_TARGET_SOCFPGA_GEN5) |
| 24 | #include <asm/arch/clock_manager_gen5.h> |
| Ley Foon Tan | ca40f29 | 2017-04-26 02:44:39 +0800 | [diff] [blame] | 25 | #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) |
| 26 | #include <asm/arch/clock_manager_arria10.h> |
| Ley Foon Tan | 6751e7d | 2018-05-18 22:05:22 +0800 | [diff] [blame] | 27 | #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) |
| 28 | #include <asm/arch/clock_manager_s10.h> |
| Ley Foon Tan | b7d95b7 | 2019-11-27 15:55:23 +0800 | [diff] [blame] | 29 | #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) |
| 30 | #include <asm/arch/clock_manager_agilex.h> |
| Jit Loon Lim | 977071e | 2024-03-12 22:01:03 +0800 | [diff] [blame] | 31 | #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) |
| 32 | #include <asm/arch/clock_manager_agilex5.h> |
| Siew Chin Lim | 4d7b6dc | 2021-08-10 11:26:34 +0800 | [diff] [blame] | 33 | #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) |
| 34 | #include <asm/arch/clock_manager_n5x.h> |
| Ley Foon Tan | ec6f882 | 2017-04-26 02:44:33 +0800 | [diff] [blame] | 35 | #endif |
| Ley Foon Tan | ca40f29 | 2017-04-26 02:44:39 +0800 | [diff] [blame] | 36 | |
| Chin Liang See | cb35060 | 2014-03-04 22:13:53 -0600 | [diff] [blame] | 37 | #endif /* _CLOCK_MANAGER_H_ */ |