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Shengzhou Liu07886942013-11-22 17:39:11 +08001/*
2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
Shengzhou Liu031228a2014-02-21 13:16:19 +08008 * T2080/T2081 QDS board configuration file
Shengzhou Liu07886942013-11-22 17:39:11 +08009 */
10
Shengzhou Liu031228a2014-02-21 13:16:19 +080011#ifndef __T208xQDS_H
12#define __T208xQDS_H
Shengzhou Liu07886942013-11-22 17:39:11 +080013
Shengzhou Liu07886942013-11-22 17:39:11 +080014#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
15#define CONFIG_MMC
Shengzhou Liu07886942013-11-22 17:39:11 +080016#define CONFIG_USB_EHCI
Shengzhou Liu031228a2014-02-21 13:16:19 +080017#if defined(CONFIG_PPC_T2080)
18#define CONFIG_T2080QDS
Shengzhou Liu07886942013-11-22 17:39:11 +080019#define CONFIG_FSL_SATA_V2
20#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
21#define CONFIG_SRIO1 /* SRIO port 1 */
22#define CONFIG_SRIO2 /* SRIO port 2 */
Shengzhou Liu031228a2014-02-21 13:16:19 +080023#elif defined(CONFIG_PPC_T2081)
24#define CONFIG_T2081QDS
25#endif
Shengzhou Liu07886942013-11-22 17:39:11 +080026
27/* High Level Configuration Options */
Shengzhou Liu07886942013-11-22 17:39:11 +080028#define CONFIG_BOOKE
29#define CONFIG_E500 /* BOOKE e500 family */
30#define CONFIG_E500MC /* BOOKE e500mc family */
31#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Shengzhou Liu07886942013-11-22 17:39:11 +080032#define CONFIG_MP /* support multiple processors */
33#define CONFIG_ENABLE_36BIT_PHYS
34
35#ifdef CONFIG_PHYS_64BIT
36#define CONFIG_ADDR_MAP 1
37#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
38#endif
39
40#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
41#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
42#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta12af67f2014-10-15 11:35:31 +053043#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Shengzhou Liu07886942013-11-22 17:39:11 +080044#define CONFIG_FSL_LAW /* Use common FSL init code */
45#define CONFIG_ENV_OVERWRITE
46
47#ifdef CONFIG_RAMBOOT_PBL
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090048#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080049
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080050#define CONFIG_SPL_FLUSH_IMAGE
51#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080052#define CONFIG_FSL_LAW /* Use common FSL init code */
53#define CONFIG_SYS_TEXT_BASE 0x00201000
54#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
55#define CONFIG_SPL_PAD_TO 0x40000
56#define CONFIG_SPL_MAX_SIZE 0x28000
57#define RESET_VECTOR_OFFSET 0x27FFC
58#define BOOT_PAGE_OFFSET 0x27000
59#ifdef CONFIG_SPL_BUILD
60#define CONFIG_SPL_SKIP_RELOCATE
61#define CONFIG_SPL_COMMON_INIT_DDR
62#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
63#define CONFIG_SYS_NO_FLASH
64#endif
65
66#ifdef CONFIG_NAND
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080067#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
68#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
69#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
70#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
71#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Zhao Qiang55107dc2016-09-08 12:55:32 +080072#if defined(CONFIG_PPC_T2080)
73#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
74#elif defined(CONFIG_PPC_T2081)
75#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
76#endif
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080077#define CONFIG_SPL_NAND_BOOT
78#endif
79
80#ifdef CONFIG_SPIFLASH
81#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080082#define CONFIG_SPL_SPI_FLASH_MINIMAL
83#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
84#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
85#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
86#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
87#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
88#ifndef CONFIG_SPL_BUILD
89#define CONFIG_SYS_MPC85XX_NO_RESETVEC
90#endif
Zhao Qiang55107dc2016-09-08 12:55:32 +080091#if defined(CONFIG_PPC_T2080)
92#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
93#elif defined(CONFIG_PPC_T2081)
94#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
95#endif
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080096#define CONFIG_SPL_SPI_BOOT
97#endif
98
99#ifdef CONFIG_SDCARD
100#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800101#define CONFIG_SPL_MMC_MINIMAL
102#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
103#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
104#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
105#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
106#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
107#ifndef CONFIG_SPL_BUILD
108#define CONFIG_SYS_MPC85XX_NO_RESETVEC
109#endif
Zhao Qiang55107dc2016-09-08 12:55:32 +0800110#if defined(CONFIG_PPC_T2080)
111#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
112#elif defined(CONFIG_PPC_T2081)
113#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
114#endif
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800115#define CONFIG_SPL_MMC_BOOT
Shengzhou Liu07886942013-11-22 17:39:11 +0800116#endif
117
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800118#endif /* CONFIG_RAMBOOT_PBL */
119
Shengzhou Liu07886942013-11-22 17:39:11 +0800120#define CONFIG_SRIO_PCIE_BOOT_MASTER
121#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
122/* Set 1M boot space */
123#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
124#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
125 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
126#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
127#define CONFIG_SYS_NO_FLASH
128#endif
129
130#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +0530131#define CONFIG_SYS_TEXT_BASE 0xeff40000
Shengzhou Liu07886942013-11-22 17:39:11 +0800132#endif
133
134#ifndef CONFIG_RESET_VECTOR_ADDRESS
135#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
136#endif
137
138/*
139 * These can be toggled for performance analysis, otherwise use default.
140 */
141#define CONFIG_SYS_CACHE_STASHING
142#define CONFIG_BTB /* toggle branch predition */
143#define CONFIG_DDR_ECC
144#ifdef CONFIG_DDR_ECC
145#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
146#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
147#endif
148
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800149#ifndef CONFIG_SYS_NO_FLASH
Shengzhou Liu07886942013-11-22 17:39:11 +0800150#define CONFIG_FLASH_CFI_DRIVER
151#define CONFIG_SYS_FLASH_CFI
152#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
153#endif
154
155#if defined(CONFIG_SPIFLASH)
156#define CONFIG_SYS_EXTRA_ENV_RELOC
157#define CONFIG_ENV_IS_IN_SPI_FLASH
158#define CONFIG_ENV_SPI_BUS 0
159#define CONFIG_ENV_SPI_CS 0
160#define CONFIG_ENV_SPI_MAX_HZ 10000000
161#define CONFIG_ENV_SPI_MODE 0
162#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
163#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
164#define CONFIG_ENV_SECT_SIZE 0x10000
165#elif defined(CONFIG_SDCARD)
166#define CONFIG_SYS_EXTRA_ENV_RELOC
167#define CONFIG_ENV_IS_IN_MMC
168#define CONFIG_SYS_MMC_ENV_DEV 0
169#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800170#define CONFIG_ENV_OFFSET (512 * 0x800)
Shengzhou Liu07886942013-11-22 17:39:11 +0800171#elif defined(CONFIG_NAND)
172#define CONFIG_SYS_EXTRA_ENV_RELOC
173#define CONFIG_ENV_IS_IN_NAND
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800174#define CONFIG_ENV_SIZE 0x2000
175#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liu07886942013-11-22 17:39:11 +0800176#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
177#define CONFIG_ENV_IS_IN_REMOTE
178#define CONFIG_ENV_ADDR 0xffe20000
179#define CONFIG_ENV_SIZE 0x2000
180#elif defined(CONFIG_ENV_IS_NOWHERE)
181#define CONFIG_ENV_SIZE 0x2000
182#else
183#define CONFIG_ENV_IS_IN_FLASH
184#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
185#define CONFIG_ENV_SIZE 0x2000
186#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
187#endif
188
189#ifndef __ASSEMBLY__
190unsigned long get_board_sys_clk(void);
191unsigned long get_board_ddr_clk(void);
192#endif
193
194#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
195#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
196
197/*
198 * Config the L3 Cache as L3 SRAM
199 */
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800200#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
201#define CONFIG_SYS_L3_SIZE (512 << 10)
202#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
203#ifdef CONFIG_RAMBOOT_PBL
204#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
205#endif
206#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
207#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
208#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
209#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
Shengzhou Liu07886942013-11-22 17:39:11 +0800210
211#define CONFIG_SYS_DCSRBAR 0xf0000000
212#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
213
214/* EEPROM */
215#define CONFIG_ID_EEPROM
216#define CONFIG_SYS_I2C_EEPROM_NXID
217#define CONFIG_SYS_EEPROM_BUS_NUM 0
218#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
219#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
220
221/*
222 * DDR Setup
223 */
224#define CONFIG_VERY_BIG_RAM
225#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
226#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Shengzhou Liueca52382014-05-20 12:08:20 +0800227#define CONFIG_DIMM_SLOTS_PER_CTLR 2
228#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
229#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
Shengzhou Liu07886942013-11-22 17:39:11 +0800230#define CONFIG_DDR_SPD
231#define CONFIG_SYS_FSL_DDR3
York Sun7a81d902014-10-27 11:31:32 -0700232#define CONFIG_FSL_DDR_INTERACTIVE
Shengzhou Liu07886942013-11-22 17:39:11 +0800233#define CONFIG_SYS_SPD_BUS_NUM 0
234#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
235#define SPD_EEPROM_ADDRESS1 0x51
236#define SPD_EEPROM_ADDRESS2 0x52
237#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
238#define CTRL_INTLV_PREFERED cacheline
239
240/*
241 * IFC Definitions
242 */
243#define CONFIG_SYS_FLASH_BASE 0xe0000000
244#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
245#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
246#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
247 + 0x8000000) | \
248 CSPR_PORT_SIZE_16 | \
249 CSPR_MSEL_NOR | \
250 CSPR_V)
251#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
252#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
253 CSPR_PORT_SIZE_16 | \
254 CSPR_MSEL_NOR | \
255 CSPR_V)
256#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
257/* NOR Flash Timing Params */
258#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
259
260#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
261 FTIM0_NOR_TEADC(0x5) | \
262 FTIM0_NOR_TEAHC(0x5))
263#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
264 FTIM1_NOR_TRAD_NOR(0x1A) |\
265 FTIM1_NOR_TSEQRAD_NOR(0x13))
266#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
267 FTIM2_NOR_TCH(0x4) | \
268 FTIM2_NOR_TWPH(0x0E) | \
269 FTIM2_NOR_TWP(0x1c))
270#define CONFIG_SYS_NOR_FTIM3 0x0
271
272#define CONFIG_SYS_FLASH_QUIET_TEST
273#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
274
275#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
276#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
277#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
278#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
279
280#define CONFIG_SYS_FLASH_EMPTY_INFO
281#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
282 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
283
284#define CONFIG_FSL_QIXIS /* use common QIXIS code */
285#define QIXIS_BASE 0xffdf0000
286#define QIXIS_LBMAP_SWITCH 6
287#define QIXIS_LBMAP_MASK 0x0f
288#define QIXIS_LBMAP_SHIFT 0
289#define QIXIS_LBMAP_DFLTBANK 0x00
290#define QIXIS_LBMAP_ALTBANK 0x04
York Sun23b3df92016-04-07 09:52:11 -0700291#define QIXIS_LBMAP_NAND 0x09
292#define QIXIS_LBMAP_SD 0x00
293#define QIXIS_RCW_SRC_NAND 0x104
294#define QIXIS_RCW_SRC_SD 0x040
Shengzhou Liu07886942013-11-22 17:39:11 +0800295#define QIXIS_RST_CTL_RESET 0x83
296#define QIXIS_RST_FORCE_MEM 0x1
297#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
298#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
299#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
300#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
301
302#define CONFIG_SYS_CSPR3_EXT (0xf)
303#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
304 | CSPR_PORT_SIZE_8 \
305 | CSPR_MSEL_GPCM \
306 | CSPR_V)
307#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
308#define CONFIG_SYS_CSOR3 0x0
309/* QIXIS Timing parameters for IFC CS3 */
310#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
311 FTIM0_GPCM_TEADC(0x0e) | \
312 FTIM0_GPCM_TEAHC(0x0e))
313#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
314 FTIM1_GPCM_TRAD(0x3f))
315#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shengzhou Liubdfeaf62014-03-06 15:07:39 +0800316 FTIM2_GPCM_TCH(0x8) | \
Shengzhou Liu07886942013-11-22 17:39:11 +0800317 FTIM2_GPCM_TWP(0x1f))
318#define CONFIG_SYS_CS3_FTIM3 0x0
319
320/* NAND Flash on IFC */
321#define CONFIG_NAND_FSL_IFC
322#define CONFIG_SYS_NAND_BASE 0xff800000
323#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
324
325#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
326#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
327 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
328 | CSPR_MSEL_NAND /* MSEL = NAND */ \
329 | CSPR_V)
330#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
331
332#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
333 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
334 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
335 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
336 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
337 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
338 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
339
340#define CONFIG_SYS_NAND_ONFI_DETECTION
341
342/* ONFI NAND Flash mode0 Timing Params */
343#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
344 FTIM0_NAND_TWP(0x18) | \
345 FTIM0_NAND_TWCHT(0x07) | \
346 FTIM0_NAND_TWH(0x0a))
347#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
348 FTIM1_NAND_TWBE(0x39) | \
349 FTIM1_NAND_TRR(0x0e) | \
350 FTIM1_NAND_TRP(0x18))
351#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
352 FTIM2_NAND_TREH(0x0a) | \
353 FTIM2_NAND_TWHRE(0x1e))
354#define CONFIG_SYS_NAND_FTIM3 0x0
355
356#define CONFIG_SYS_NAND_DDR_LAW 11
357#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
358#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liu07886942013-11-22 17:39:11 +0800359#define CONFIG_CMD_NAND
360#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
361
362#if defined(CONFIG_NAND)
363#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
364#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
365#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
366#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
367#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
368#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
369#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
370#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
Shengzhou Liub2708d62014-03-13 10:19:00 +0800371#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
372#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
373#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
374#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
375#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
376#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
377#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
378#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
379#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
380#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
Shengzhou Liu07886942013-11-22 17:39:11 +0800381#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
382#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
383#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
384#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
385#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
386#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
387#else
388#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
389#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
390#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
391#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
392#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
393#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
394#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
395#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
Shengzhou Liub2708d62014-03-13 10:19:00 +0800396#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
397#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
398#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
399#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
400#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
401#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
402#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
403#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
Shengzhou Liu07886942013-11-22 17:39:11 +0800404#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
405#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
406#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
407#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
408#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
409#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
410#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
411#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
412#endif
Shengzhou Liu07886942013-11-22 17:39:11 +0800413
414#if defined(CONFIG_RAMBOOT_PBL)
415#define CONFIG_SYS_RAMBOOT
416#endif
417
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800418#ifdef CONFIG_SPL_BUILD
419#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
420#else
421#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
422#endif
423
Shengzhou Liu07886942013-11-22 17:39:11 +0800424#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
425#define CONFIG_MISC_INIT_R
426#define CONFIG_HWCONFIG
427
428/* define to use L1 as initial stack */
429#define CONFIG_L1_INIT_RAM
430#define CONFIG_SYS_INIT_RAM_LOCK
431#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
432#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunee7b4832015-08-17 13:31:51 -0700433#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liu07886942013-11-22 17:39:11 +0800434/* The assembler doesn't like typecast */
435#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
436 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
437 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
438#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
439#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
440 GENERATED_GBL_DATA_SIZE)
441#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530442#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Shengzhou Liu07886942013-11-22 17:39:11 +0800443#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
444
445/*
446 * Serial Port
447 */
448#define CONFIG_CONS_INDEX 1
Shengzhou Liu07886942013-11-22 17:39:11 +0800449#define CONFIG_SYS_NS16550_SERIAL
450#define CONFIG_SYS_NS16550_REG_SIZE 1
451#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
452#define CONFIG_SYS_BAUDRATE_TABLE \
453 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
454#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
455#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
456#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
457#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
458
Shengzhou Liu07886942013-11-22 17:39:11 +0800459/*
460 * I2C
461 */
462#define CONFIG_SYS_I2C
463#define CONFIG_SYS_I2C_FSL
464#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
465#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
466#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
467#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
468#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
469#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
470#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
471#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
472#define CONFIG_SYS_FSL_I2C_SPEED 100000
473#define CONFIG_SYS_FSL_I2C2_SPEED 100000
474#define CONFIG_SYS_FSL_I2C3_SPEED 100000
475#define CONFIG_SYS_FSL_I2C4_SPEED 100000
476#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
477#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
478#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
479#define I2C_MUX_CH_DEFAULT 0x8
480
Ying Zhang8876a512014-10-31 18:06:18 +0800481#define I2C_MUX_CH_VOL_MONITOR 0xa
482
483/* Voltage monitor on channel 2*/
484#define I2C_VOL_MONITOR_ADDR 0x40
485#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
486#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
487#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
488
489#define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
490#ifndef CONFIG_SPL_BUILD
491#define CONFIG_VID
492#endif
493#define CONFIG_VOL_MONITOR_IR36021_SET
494#define CONFIG_VOL_MONITOR_IR36021_READ
495/* The lowest and highest voltage allowed for T208xQDS */
496#define VDD_MV_MIN 819
497#define VDD_MV_MAX 1212
Shengzhou Liu07886942013-11-22 17:39:11 +0800498
499/*
500 * RapidIO
501 */
502#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
503#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
504#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
505#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
506#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
507#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
508/*
509 * for slave u-boot IMAGE instored in master memory space,
510 * PHYS must be aligned based on the SIZE
511 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800512#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
513#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
514#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
515#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Shengzhou Liu07886942013-11-22 17:39:11 +0800516/*
517 * for slave UCODE and ENV instored in master memory space,
518 * PHYS must be aligned based on the SIZE
519 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800520#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Shengzhou Liu07886942013-11-22 17:39:11 +0800521#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
522#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
523
524/* slave core release by master*/
525#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
526#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
527
528/*
529 * SRIO_PCIE_BOOT - SLAVE
530 */
531#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
532#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
533#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
534 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
535#endif
536
537/*
538 * eSPI - Enhanced SPI
539 */
540#ifdef CONFIG_SPI_FLASH
Shengzhou Liu8c7e1e12014-05-21 13:26:17 +0800541#ifndef CONFIG_SPL_BUILD
Shengzhou Liu031228a2014-02-21 13:16:19 +0800542#endif
543
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800544#define CONFIG_SPI_FLASH_BAR
Shengzhou Liu07886942013-11-22 17:39:11 +0800545#define CONFIG_SF_DEFAULT_SPEED 10000000
546#define CONFIG_SF_DEFAULT_MODE 0
547#endif
548
549/*
550 * General PCI
551 * Memory space is mapped 1-1, but I/O space must start from 0.
552 */
Robert P. J. Daya8099812016-05-03 19:52:49 -0400553#define CONFIG_PCIE1 /* PCIE controller 1 */
554#define CONFIG_PCIE2 /* PCIE controller 2 */
555#define CONFIG_PCIE3 /* PCIE controller 3 */
556#define CONFIG_PCIE4 /* PCIE controller 4 */
Zhao Qiangf36e0ba2015-03-26 16:13:09 +0800557#define CONFIG_FSL_PCIE_RESET
Shengzhou Liu07886942013-11-22 17:39:11 +0800558#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
559#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
560/* controller 1, direct to uli, tgtid 3, Base address 20000 */
561#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
562#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
563#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
564#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
565#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
566#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
567#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
568#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
569
570/* controller 2, Slot 2, tgtid 2, Base address 201000 */
571#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
572#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
573#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
574#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
575#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
576#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
577#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
578#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
579
580/* controller 3, Slot 1, tgtid 1, Base address 202000 */
581#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
582#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
583#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
584#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
585#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
586#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
587#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
588#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
589
590/* controller 4, Base address 203000 */
591#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
592#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
593#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
594#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
595#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
596#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
597#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
598
599#ifdef CONFIG_PCI
600#define CONFIG_PCI_INDIRECT_BRIDGE
Shengzhou Liu031228a2014-02-21 13:16:19 +0800601#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
Shengzhou Liu07886942013-11-22 17:39:11 +0800602#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
603#define CONFIG_DOS_PARTITION
604#endif
605
606/* Qman/Bman */
607#ifndef CONFIG_NOBQFMAN
608#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
609#define CONFIG_SYS_BMAN_NUM_PORTALS 18
610#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
611#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
612#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500613#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
614#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
615#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
616#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
617#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
618 CONFIG_SYS_BMAN_CENA_SIZE)
619#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
620#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu07886942013-11-22 17:39:11 +0800621#define CONFIG_SYS_QMAN_NUM_PORTALS 18
622#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
623#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
624#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500625#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
626#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
627#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
628#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
629#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
630 CONFIG_SYS_QMAN_CENA_SIZE)
631#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
632#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu07886942013-11-22 17:39:11 +0800633
634#define CONFIG_SYS_DPAA_FMAN
635#define CONFIG_SYS_DPAA_PME
636#define CONFIG_SYS_PMAN
637#define CONFIG_SYS_DPAA_DCE
638#define CONFIG_SYS_DPAA_RMAN /* RMan */
639#define CONFIG_SYS_INTERLAKEN
640
641/* Default address of microcode for the Linux Fman driver */
642#if defined(CONFIG_SPIFLASH)
643/*
644 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
645 * env, so we got 0x110000.
646 */
647#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiang83a90842014-03-21 16:21:44 +0800648#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Shengzhou Liu07886942013-11-22 17:39:11 +0800649#elif defined(CONFIG_SDCARD)
650/*
651 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800652 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
653 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Shengzhou Liu07886942013-11-22 17:39:11 +0800654 */
655#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800656#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
Shengzhou Liu07886942013-11-22 17:39:11 +0800657#elif defined(CONFIG_NAND)
658#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800659#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liu07886942013-11-22 17:39:11 +0800660#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
661/*
662 * Slave has no ucode locally, it can fetch this from remote. When implementing
663 * in two corenet boards, slave's ucode could be stored in master's memory
664 * space, the address can be mapped from slave TLB->slave LAW->
665 * slave SRIO or PCIE outbound window->master inbound window->
666 * master LAW->the ucode address in master's memory space.
667 */
668#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Zhao Qiang83a90842014-03-21 16:21:44 +0800669#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Shengzhou Liu07886942013-11-22 17:39:11 +0800670#else
671#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiang83a90842014-03-21 16:21:44 +0800672#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Shengzhou Liu07886942013-11-22 17:39:11 +0800673#endif
674#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
675#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
676#endif /* CONFIG_NOBQFMAN */
677
678#ifdef CONFIG_SYS_DPAA_FMAN
679#define CONFIG_FMAN_ENET
680#define CONFIG_PHYLIB_10G
681#define CONFIG_PHY_VITESSE
682#define CONFIG_PHY_REALTEK
683#define CONFIG_PHY_TERANETICS
684#define RGMII_PHY1_ADDR 0x1
685#define RGMII_PHY2_ADDR 0x2
686#define FM1_10GEC1_PHY_ADDR 0x3
687#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
688#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
689#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
690#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
691#endif
692
693#ifdef CONFIG_FMAN_ENET
694#define CONFIG_MII /* MII PHY management */
695#define CONFIG_ETHPRIME "FM1@DTSEC3"
696#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
697#endif
698
699/*
700 * SATA
701 */
702#ifdef CONFIG_FSL_SATA_V2
703#define CONFIG_LIBATA
704#define CONFIG_FSL_SATA
705#define CONFIG_SYS_SATA_MAX_DEVICE 2
706#define CONFIG_SATA1
707#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
708#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
709#define CONFIG_SATA2
710#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
711#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
712#define CONFIG_LBA48
713#define CONFIG_CMD_SATA
714#define CONFIG_DOS_PARTITION
Shengzhou Liu07886942013-11-22 17:39:11 +0800715#endif
716
717/*
718 * USB
719 */
720#ifdef CONFIG_USB_EHCI
Shengzhou Liu07886942013-11-22 17:39:11 +0800721#define CONFIG_USB_EHCI_FSL
722#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Shengzhou Liu07886942013-11-22 17:39:11 +0800723#define CONFIG_HAS_FSL_DR_USB
724#endif
725
726/*
727 * SDHC
728 */
729#ifdef CONFIG_MMC
Shengzhou Liu07886942013-11-22 17:39:11 +0800730#define CONFIG_FSL_ESDHC
Yangbo Lu2abf9272016-01-28 16:33:07 +0800731#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
Shengzhou Liu07886942013-11-22 17:39:11 +0800732#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
733#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
734#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
735#define CONFIG_GENERIC_MMC
Shengzhou Liu07886942013-11-22 17:39:11 +0800736#define CONFIG_DOS_PARTITION
Yangbo Lu90a6cd32015-04-22 13:57:21 +0800737#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
Shengzhou Liu07886942013-11-22 17:39:11 +0800738#endif
739
Shengzhou Liuff16bd82014-04-02 14:28:34 +0800740/*
741 * Dynamic MTD Partition support with mtdparts
742 */
743#ifndef CONFIG_SYS_NO_FLASH
744#define CONFIG_MTD_DEVICE
745#define CONFIG_MTD_PARTITIONS
746#define CONFIG_CMD_MTDPARTS
747#define CONFIG_FLASH_CFI_MTD
748#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
749 "spi0=spife110000.0"
750#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
751 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
752 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
753 "1m(uboot),5m(kernel),128k(dtb),-(user)"
754#endif
755
Shengzhou Liu07886942013-11-22 17:39:11 +0800756/*
757 * Environment
758 */
759#define CONFIG_LOADS_ECHO /* echo on for serial download */
760#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
761
762/*
763 * Command line configuration.
764 */
Shengzhou Liu07886942013-11-22 17:39:11 +0800765#define CONFIG_CMD_ERRATA
Shengzhou Liu07886942013-11-22 17:39:11 +0800766#define CONFIG_CMD_IRQ
Shengzhou Liu07886942013-11-22 17:39:11 +0800767#define CONFIG_CMD_REGINFO
Shengzhou Liu07886942013-11-22 17:39:11 +0800768
769#ifdef CONFIG_PCI
770#define CONFIG_CMD_PCI
Shengzhou Liu07886942013-11-22 17:39:11 +0800771#endif
772
Ruchika Gupta12af67f2014-10-15 11:35:31 +0530773/* Hash command with SHA acceleration supported in hardware */
774#ifdef CONFIG_FSL_CAAM
775#define CONFIG_CMD_HASH
776#define CONFIG_SHA_HW_ACCEL
777#endif
778
Shengzhou Liu07886942013-11-22 17:39:11 +0800779/*
780 * Miscellaneous configurable options
781 */
782#define CONFIG_SYS_LONGHELP /* undef to save memory */
783#define CONFIG_CMDLINE_EDITING /* Command-line editing */
784#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
785#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liu07886942013-11-22 17:39:11 +0800786#ifdef CONFIG_CMD_KGDB
787#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
788#else
789#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
790#endif
791#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
792#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
793#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Shengzhou Liu07886942013-11-22 17:39:11 +0800794
795/*
796 * For booting Linux, the board info and command line data
797 * have to be in the first 64 MB of memory, since this is
798 * the maximum mapped by the Linux kernel during initialization.
799 */
800#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
801#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
802
803#ifdef CONFIG_CMD_KGDB
804#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
805#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
806#endif
807
808/*
809 * Environment Configuration
810 */
811#define CONFIG_ROOTPATH "/opt/nfsroot"
812#define CONFIG_BOOTFILE "uImage"
813#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
814
815/* default location for tftp and bootm */
816#define CONFIG_LOADADDR 1000000
817#define CONFIG_BAUDRATE 115200
Shengzhou Liu07886942013-11-22 17:39:11 +0800818#define __USB_PHY_TYPE utmi
819
820#define CONFIG_EXTRA_ENV_SETTINGS \
821 "hwconfig=fsl_ddr:" \
822 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
823 "bank_intlv=auto;" \
824 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
825 "netdev=eth0\0" \
826 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
827 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
828 "tftpflash=tftpboot $loadaddr $uboot && " \
829 "protect off $ubootaddr +$filesize && " \
830 "erase $ubootaddr +$filesize && " \
831 "cp.b $loadaddr $ubootaddr $filesize && " \
832 "protect on $ubootaddr +$filesize && " \
833 "cmp.b $loadaddr $ubootaddr $filesize\0" \
834 "consoledev=ttyS0\0" \
835 "ramdiskaddr=2000000\0" \
836 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500837 "fdtaddr=1e00000\0" \
Shengzhou Liu07886942013-11-22 17:39:11 +0800838 "fdtfile=t2080qds/t2080qds.dtb\0" \
Kim Phillips1dedccc2014-05-14 19:33:45 -0500839 "bdev=sda3\0"
Shengzhou Liu07886942013-11-22 17:39:11 +0800840
841/*
842 * For emulation this causes u-boot to jump to the start of the
843 * proof point app code automatically
844 */
845#define CONFIG_PROOF_POINTS \
846 "setenv bootargs root=/dev/$bdev rw " \
847 "console=$consoledev,$baudrate $othbootargs;" \
848 "cpu 1 release 0x29000000 - - -;" \
849 "cpu 2 release 0x29000000 - - -;" \
850 "cpu 3 release 0x29000000 - - -;" \
851 "cpu 4 release 0x29000000 - - -;" \
852 "cpu 5 release 0x29000000 - - -;" \
853 "cpu 6 release 0x29000000 - - -;" \
854 "cpu 7 release 0x29000000 - - -;" \
855 "go 0x29000000"
856
857#define CONFIG_HVBOOT \
858 "setenv bootargs config-addr=0x60000000; " \
859 "bootm 0x01000000 - 0x00f00000"
860
861#define CONFIG_ALU \
862 "setenv bootargs root=/dev/$bdev rw " \
863 "console=$consoledev,$baudrate $othbootargs;" \
864 "cpu 1 release 0x01000000 - - -;" \
865 "cpu 2 release 0x01000000 - - -;" \
866 "cpu 3 release 0x01000000 - - -;" \
867 "cpu 4 release 0x01000000 - - -;" \
868 "cpu 5 release 0x01000000 - - -;" \
869 "cpu 6 release 0x01000000 - - -;" \
870 "cpu 7 release 0x01000000 - - -;" \
871 "go 0x01000000"
872
873#define CONFIG_LINUX \
874 "setenv bootargs root=/dev/ram rw " \
875 "console=$consoledev,$baudrate $othbootargs;" \
876 "setenv ramdiskaddr 0x02000000;" \
877 "setenv fdtaddr 0x00c00000;" \
878 "setenv loadaddr 0x1000000;" \
879 "bootm $loadaddr $ramdiskaddr $fdtaddr"
880
881#define CONFIG_HDBOOT \
882 "setenv bootargs root=/dev/$bdev rw " \
883 "console=$consoledev,$baudrate $othbootargs;" \
884 "tftp $loadaddr $bootfile;" \
885 "tftp $fdtaddr $fdtfile;" \
886 "bootm $loadaddr - $fdtaddr"
887
888#define CONFIG_NFSBOOTCOMMAND \
889 "setenv bootargs root=/dev/nfs rw " \
890 "nfsroot=$serverip:$rootpath " \
891 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
892 "console=$consoledev,$baudrate $othbootargs;" \
893 "tftp $loadaddr $bootfile;" \
894 "tftp $fdtaddr $fdtfile;" \
895 "bootm $loadaddr - $fdtaddr"
896
897#define CONFIG_RAMBOOTCOMMAND \
898 "setenv bootargs root=/dev/ram rw " \
899 "console=$consoledev,$baudrate $othbootargs;" \
900 "tftp $ramdiskaddr $ramdiskfile;" \
901 "tftp $loadaddr $bootfile;" \
902 "tftp $fdtaddr $fdtfile;" \
903 "bootm $loadaddr $ramdiskaddr $fdtaddr"
904
905#define CONFIG_BOOTCOMMAND CONFIG_LINUX
906
Shengzhou Liu07886942013-11-22 17:39:11 +0800907#include <asm/fsl_secure_boot.h>
Aneesh Bansal962021a2016-01-22 16:37:22 +0530908
Shengzhou Liu031228a2014-02-21 13:16:19 +0800909#endif /* __T208xQDS_H */