blob: d868ce231544288dbc60d95ba758348737bd9a73 [file] [log] [blame]
Jon Loeliger3e2d0912007-04-11 16:50:57 -05001/*
Kumar Galaa9db4ec2011-01-11 00:52:35 -06002 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
Jon Loeliger3e2d0912007-04-11 16:50:57 -05003 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Jon Loeliger3e2d0912007-04-11 16:50:57 -05005 */
6
7/*
8 * mpc8544ds board configuration file
9 *
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/* High Level Configuration Options */
15#define CONFIG_BOOKE 1 /* BOOKE */
16#define CONFIG_E500 1 /* BOOKE e500 family */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050017#define CONFIG_MPC8544 1
18#define CONFIG_MPC8544DS 1
19
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020020#ifndef CONFIG_SYS_TEXT_BASE
21#define CONFIG_SYS_TEXT_BASE 0xfff80000
22#endif
23
Ed Swarthout52b98522007-07-27 01:50:51 -050024#define CONFIG_PCI1 1 /* PCI controller 1 */
Robert P. J. Daya8099812016-05-03 19:52:49 -040025#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
26#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
27#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
Ed Swarthout52b98522007-07-27 01:50:51 -050028#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhosb4458732013-05-30 07:06:12 +000029#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala93166d22007-12-07 12:17:34 -060030#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala7738d5c2008-10-21 11:33:58 -050031#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050032
Kumar Gala85af2b52008-01-16 01:16:16 -060033#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
34
Ed Swarthout52b98522007-07-27 01:50:51 -050035#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050036#define CONFIG_ENV_OVERWRITE
Ed Swarthout52b98522007-07-27 01:50:51 -050037#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050038
Jon Loeliger3e2d0912007-04-11 16:50:57 -050039#ifndef __ASSEMBLY__
40extern unsigned long get_board_sys_clk(unsigned long dummy);
41#endif
42#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
43
44/*
45 * These can be toggled for performance analysis, otherwise use default.
46 */
Ed Swarthout52b98522007-07-27 01:50:51 -050047#define CONFIG_L2_CACHE /* toggle L2 cache */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050048#define CONFIG_BTB /* toggle branch predition */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050049
50/*
51 * Only possible on E500 Version 2 or newer cores.
52 */
53#define CONFIG_ENABLE_36BIT_PHYS 1
54
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020055#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
56#define CONFIG_SYS_MEMTEST_END 0x00400000
Ed Swarthout52b98522007-07-27 01:50:51 -050057#define CONFIG_PANIC_HANG /* do not reset board on panic */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050058
Timur Tabid8f341c2011-08-04 18:03:41 -050059#define CONFIG_SYS_CCSRBAR 0xe0000000
60#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Jon Loeliger3e2d0912007-04-11 16:50:57 -050061
Kumar Gala573ad302008-08-26 08:02:30 -050062/* DDR Setup */
York Sunf0626592013-09-30 09:22:09 -070063#define CONFIG_SYS_FSL_DDR2
Kumar Gala573ad302008-08-26 08:02:30 -050064#undef CONFIG_FSL_DDR_INTERACTIVE
65#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
66#define CONFIG_DDR_SPD
67
Dave Liud3ca1242008-10-28 17:53:38 +080068#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Kumar Gala573ad302008-08-26 08:02:30 -050069#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
70
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
72#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala573ad302008-08-26 08:02:30 -050073#define CONFIG_VERY_BIG_RAM
74
75#define CONFIG_NUM_DDR_CONTROLLERS 1
76#define CONFIG_DIMM_SLOTS_PER_CTLR 1
77#define CONFIG_CHIP_SELECTS_PER_CTRL 2
Jon Loeliger3e2d0912007-04-11 16:50:57 -050078
Kumar Gala573ad302008-08-26 08:02:30 -050079/* I2C addresses of SPD EEPROMs */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050080#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
81
Kumar Gala573ad302008-08-26 08:02:30 -050082/* Make sure required options are set */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050083#ifndef CONFIG_SPD_EEPROM
84#error ("CONFIG_SPD_EEPROM is required")
85#endif
86
87#undef CONFIG_CLOCKS_IN_MHZ
88
89/*
90 * Memory map
91 *
92 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
93 *
94 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
95 *
96 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
97 *
98 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
99 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
100 *
101 * Localbus cacheable
102 *
103 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
104 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
105 *
106 * Localbus non-cacheable
107 *
108 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
109 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
110 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
111 *
112 */
113
114/*
115 * Local Bus Definitions
116 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500118
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500120
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200121#define CONFIG_SYS_BR0_PRELIM 0xff801001
122#define CONFIG_SYS_BR1_PRELIM 0xfe801001
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500123
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200124#define CONFIG_SYS_OR0_PRELIM 0xff806e65
125#define CONFIG_SYS_OR1_PRELIM 0xff806e65
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500126
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500128
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_FLASH_QUIET_TEST
130#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
131#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
132#undef CONFIG_SYS_FLASH_CHECKSUM
133#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
134#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Galaded59a12008-06-09 18:55:38 -0500135#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500136
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200137#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500138
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200139#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200140#define CONFIG_SYS_FLASH_CFI
141#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500142
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500144
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
146#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500147
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
149#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500150
Kim Phillips53b34982007-08-21 17:00:17 -0500151#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500152#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
153#define PIXIS_ID 0x0 /* Board ID at offset 0 */
154#define PIXIS_VER 0x1 /* Board version at offset 1 */
155#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
156#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
157#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
158 * register */
159#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
160#define PIXIS_VCTL 0x10 /* VELA Control Register */
161#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
162#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
163#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Galae21db032009-07-14 22:42:01 -0500164#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
165#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500166#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
167#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
168#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
169#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500170#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200171#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500172#define PIXIS_VSPEED2_TSEC1SER 0x2
173#define PIXIS_VSPEED2_TSEC3SER 0x1
174#define PIXIS_VCFGEN1_TSEC1SER 0x20
175#define PIXIS_VCFGEN1_TSEC3SER 0x40
Liu Yu46269062008-10-10 11:40:58 +0800176#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
177#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500178
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200179#define CONFIG_SYS_INIT_RAM_LOCK 1
180#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200181#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500182
Wolfgang Denk0191e472010-10-26 14:34:52 +0200183#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500185
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
187#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500188
189/* Serial Port - controlled on board with jumper J8
190 * open - index 2
191 * shorted - index 1
192 */
193#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200194#define CONFIG_SYS_NS16550_SERIAL
195#define CONFIG_SYS_NS16550_REG_SIZE 1
196#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500197
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500199 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
202#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500203
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500204/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200205#define CONFIG_SYS_I2C
206#define CONFIG_SYS_I2C_FSL
207#define CONFIG_SYS_FSL_I2C_SPEED 400000
208#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
Benjamin Kamathe77bd682016-06-29 16:44:38 -0700209#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
Heiko Schocherf2850742012-10-24 13:48:22 +0200210#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500212
213/*
214 * General PCI
215 * Memory space is mapped 1-1, but I/O space must start from 0.
216 */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600217#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600219#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200220#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500221
Kumar Galaef43b6e2008-12-02 16:08:39 -0600222#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600223#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600224#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200225#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600226#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600227#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
229#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500230
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500231/* controller 2, Slot 1, tgtid 1, Base address 9000 */
Kumar Galacc46bc72010-12-17 06:01:24 -0600232#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Kumar Galaef43b6e2008-12-02 16:08:39 -0600233#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600234#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600235#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200236#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600237#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600238#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200239#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
240#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500241
242/* controller 1, Slot 2,tgtid 2, Base address a000 */
Kumar Galacc46bc72010-12-17 06:01:24 -0600243#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Kumar Galaef43b6e2008-12-02 16:08:39 -0600244#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600245#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600246#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200247#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600248#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600249#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200250#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
251#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500252
253/* controller 3, direct to uli, tgtid 3, Base address b000 */
Kumar Galacc46bc72010-12-17 06:01:24 -0600254#define CONFIG_SYS_PCIE3_NAME "ULI"
Kumar Galaef43b6e2008-12-02 16:08:39 -0600255#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600256#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600257#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200258#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600259#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
Kumar Gala64bb6d12008-12-02 16:08:37 -0600260#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200261#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
262#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600263#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
Kumar Gala3fe80872008-12-02 16:08:36 -0600264#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600265#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200266#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500267
268#if defined(CONFIG_PCI)
269
Kumar Gala559e5312008-07-14 14:07:03 -0500270/*PCIE video card used*/
Kumar Gala60ff4642008-12-02 16:08:40 -0600271#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
Kumar Gala559e5312008-07-14 14:07:03 -0500272
273/*PCI video card used*/
Kumar Gala60ff4642008-12-02 16:08:40 -0600274/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
Kumar Gala559e5312008-07-14 14:07:03 -0500275
276/* video */
Kumar Gala559e5312008-07-14 14:07:03 -0500277
278#if defined(CONFIG_VIDEO)
279#define CONFIG_BIOSEMU
Kumar Gala559e5312008-07-14 14:07:03 -0500280#define CONFIG_ATI_RADEON_FB
281#define CONFIG_VIDEO_LOGO
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200282#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala559e5312008-07-14 14:07:03 -0500283#endif
284
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500285#undef CONFIG_EEPRO100
286#undef CONFIG_TULIP
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500287
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500288#ifndef CONFIG_PCI_PNP
Kumar Gala64bb6d12008-12-02 16:08:37 -0600289 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
290 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500291 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
292#endif
293
294#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
295#define CONFIG_DOS_PARTITION
296#define CONFIG_SCSI_AHCI
297
298#ifdef CONFIG_SCSI_AHCI
Rob Herring83f66482013-08-24 10:10:54 -0500299#define CONFIG_LIBATA
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500300#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200301#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
302#define CONFIG_SYS_SCSI_MAX_LUN 1
303#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
304#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500305#endif /* SCSCI */
306
307#endif /* CONFIG_PCI */
308
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500309#if defined(CONFIG_TSEC_ENET)
310
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500311#define CONFIG_MII 1 /* MII PHY management */
312#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
Kim Phillips177e58f2007-05-16 16:52:19 -0500313#define CONFIG_TSEC1 1
314#define CONFIG_TSEC1_NAME "eTSEC1"
315#define CONFIG_TSEC3 1
316#define CONFIG_TSEC3_NAME "eTSEC3"
Ed Swarthout52b98522007-07-27 01:50:51 -0500317
Liu Yu46269062008-10-10 11:40:58 +0800318#define CONFIG_PIXIS_SGMII_CMD
Andy Fleming3d19fad2008-08-31 16:33:28 -0500319#define CONFIG_FSL_SGMII_RISER 1
320#define SGMII_RISER_PHY_OFFSET 0x1c
321
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500322#define TSEC1_PHY_ADDR 0
323#define TSEC3_PHY_ADDR 1
324
Andy Fleming09b88df2007-08-15 20:03:25 -0500325#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
326#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
327
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500328#define TSEC1_PHYIDX 0
329#define TSEC3_PHYIDX 0
330
331#define CONFIG_ETHPRIME "eTSEC1"
332
333#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500334#endif /* CONFIG_TSEC_ENET */
335
336/*
337 * Environment
338 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200339#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200340#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200341#define CONFIG_ENV_ADDR 0xfff80000
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500342#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200343#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500344#endif
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200345#define CONFIG_ENV_SIZE 0x2000
346#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500347
348#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200349#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500350
Jon Loeligere63319f2007-06-13 13:22:08 -0500351/*
Jon Loeligered26c742007-07-10 09:10:49 -0500352 * BOOTP options
353 */
354#define CONFIG_BOOTP_BOOTFILESIZE
355#define CONFIG_BOOTP_BOOTPATH
356#define CONFIG_BOOTP_GATEWAY
357#define CONFIG_BOOTP_HOSTNAME
358
Jon Loeligered26c742007-07-10 09:10:49 -0500359/*
Jon Loeligere63319f2007-06-13 13:22:08 -0500360 * Command line configuration.
361 */
Kumar Gala489675d2008-09-22 23:40:42 -0500362#define CONFIG_CMD_IRQ
Becky Bruceee888da2010-06-17 11:37:25 -0500363#define CONFIG_CMD_REGINFO
Jon Loeligere63319f2007-06-13 13:22:08 -0500364
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500365#if defined(CONFIG_PCI)
Jon Loeligere63319f2007-06-13 13:22:08 -0500366 #define CONFIG_CMD_PCI
Simon Glass8706b812016-05-01 11:36:02 -0600367 #define CONFIG_SCSI
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500368#endif
Jon Loeligere63319f2007-06-13 13:22:08 -0500369
Hongtao Jia7cfc5c82012-12-20 19:39:53 +0000370/*
371 * USB
372 */
373#define CONFIG_USB_EHCI
374
375#ifdef CONFIG_USB_EHCI
Hongtao Jia7cfc5c82012-12-20 19:39:53 +0000376#define CONFIG_USB_EHCI_PCI
377#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Hongtao Jia7cfc5c82012-12-20 19:39:53 +0000378#define CONFIG_PCI_EHCI_DEVICE 0
379#endif
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500380
381#undef CONFIG_WATCHDOG /* watchdog disabled */
382
383/*
384 * Miscellaneous configurable options
385 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200386#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillipsf7758c12010-07-14 19:47:18 -0500387#define CONFIG_CMDLINE_EDITING /* Command-line editing */
388#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200389#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeligere63319f2007-06-13 13:22:08 -0500390#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200391#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500392#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200393#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500394#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200395#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
396#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
397#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500398
399/*
400 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500401 * have to be in the first 64 MB of memory, since this is
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500402 * the maximum mapped by the Linux kernel during initialization.
403 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500404#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
405#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500406
Jon Loeligere63319f2007-06-13 13:22:08 -0500407#if defined(CONFIG_CMD_KGDB)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500408#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500409#endif
410
411/*
412 * Environment Configuration
413 */
414
415/* The mac addresses for all ethernet interface */
416#if defined(CONFIG_TSEC_ENET)
Kumar Gala0eb61912007-08-16 11:01:21 -0500417#define CONFIG_HAS_ETH0
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500418#define CONFIG_HAS_ETH1
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500419#endif
420
421#define CONFIG_IPADDR 192.168.1.251
422
423#define CONFIG_HOSTNAME 8544ds_unknown
Joe Hershberger257ff782011-10-13 13:03:47 +0000424#define CONFIG_ROOTPATH "/nfs/mpc85xx"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000425#define CONFIG_BOOTFILE "8544ds/uImage.uboot"
Ed Swarthout52b98522007-07-27 01:50:51 -0500426#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500427
Kumar Gala937176b2007-11-27 22:42:34 -0600428#define CONFIG_SERVERIP 192.168.1.1
429#define CONFIG_GATEWAYIP 192.168.1.1
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500430#define CONFIG_NETMASK 255.255.0.0
431
432#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
433
Ed Swarthout52b98522007-07-27 01:50:51 -0500434#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500435
436#define CONFIG_BAUDRATE 115200
437
Ed Swarthout52b98522007-07-27 01:50:51 -0500438#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200439"netdev=eth0\0" \
440"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
441"tftpflash=tftpboot $loadaddr $uboot; " \
442 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
443 " +$filesize; " \
444 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
445 " +$filesize; " \
446 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
447 " $filesize; " \
448 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
449 " +$filesize; " \
450 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
451 " $filesize\0" \
452"consoledev=ttyS0\0" \
453"ramdiskaddr=2000000\0" \
454"ramdiskfile=8544ds/ramdisk.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500455"fdtaddr=1e00000\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200456"fdtfile=8544ds/mpc8544ds.dtb\0" \
457"bdev=sda3\0"
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500458
459#define CONFIG_NFSBOOTCOMMAND \
460 "setenv bootargs root=/dev/nfs rw " \
461 "nfsroot=$serverip:$rootpath " \
462 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
463 "console=$consoledev,$baudrate $othbootargs;" \
464 "tftp $loadaddr $bootfile;" \
Kumar Gala937176b2007-11-27 22:42:34 -0600465 "tftp $fdtaddr $fdtfile;" \
466 "bootm $loadaddr - $fdtaddr"
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500467
Ed Swarthout52b98522007-07-27 01:50:51 -0500468#define CONFIG_RAMBOOTCOMMAND \
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500469 "setenv bootargs root=/dev/ram rw " \
470 "console=$consoledev,$baudrate $othbootargs;" \
471 "tftp $ramdiskaddr $ramdiskfile;" \
472 "tftp $loadaddr $bootfile;" \
Kumar Gala937176b2007-11-27 22:42:34 -0600473 "tftp $fdtaddr $fdtfile;" \
474 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500475
Ed Swarthout52b98522007-07-27 01:50:51 -0500476#define CONFIG_BOOTCOMMAND \
477 "setenv bootargs root=/dev/$bdev rw " \
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500478 "console=$consoledev,$baudrate $othbootargs;" \
479 "tftp $loadaddr $bootfile;" \
Kumar Gala937176b2007-11-27 22:42:34 -0600480 "tftp $fdtaddr $fdtfile;" \
481 "bootm $loadaddr - $fdtaddr"
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500482
483#endif /* __CONFIG_H */