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York Sun0789dc92012-12-23 19:25:27 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
York Sun0789dc92012-12-23 19:25:27 +00005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10/*
11 * B4860 QDS board configuration file
12 */
13#define CONFIG_B4860QDS
York Sun0789dc92012-12-23 19:25:27 +000014
15#ifdef CONFIG_RAMBOOT_PBL
Prabhakar Kushwaha33542982014-04-08 19:13:44 +053016#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
17#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
18#ifndef CONFIG_NAND
York Sun0789dc92012-12-23 19:25:27 +000019#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Prabhakar Kushwaha33542982014-04-08 19:13:44 +053021#else
Prabhakar Kushwaha33542982014-04-08 19:13:44 +053022#define CONFIG_SPL_FLUSH_IMAGE
23#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Prabhakar Kushwaha33542982014-04-08 19:13:44 +053024#define CONFIG_FSL_LAW /* Use common FSL init code */
25#define CONFIG_SYS_TEXT_BASE 0x00201000
26#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
27#define CONFIG_SPL_PAD_TO 0x40000
28#define CONFIG_SPL_MAX_SIZE 0x28000
29#define RESET_VECTOR_OFFSET 0x27FFC
30#define BOOT_PAGE_OFFSET 0x27000
Prabhakar Kushwaha33542982014-04-08 19:13:44 +053031#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
32#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
33#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
34#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
35#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
36#define CONFIG_SPL_NAND_BOOT
37#ifdef CONFIG_SPL_BUILD
38#define CONFIG_SPL_SKIP_RELOCATE
39#define CONFIG_SPL_COMMON_INIT_DDR
40#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
41#define CONFIG_SYS_NO_FLASH
42#endif
43#endif
York Sun0789dc92012-12-23 19:25:27 +000044#endif
45
Liu Gang0ff15f92013-05-07 16:30:48 +080046#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
47/* Set 1M boot space */
48#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
49#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
50 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
51#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
52#define CONFIG_SYS_NO_FLASH
53#endif
54
York Sun0789dc92012-12-23 19:25:27 +000055/* High Level Configuration Options */
56#define CONFIG_BOOKE
York Sun0789dc92012-12-23 19:25:27 +000057#define CONFIG_E500 /* BOOKE e500 family */
58#define CONFIG_E500MC /* BOOKE e500mc family */
59#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
York Sun0789dc92012-12-23 19:25:27 +000060#define CONFIG_MP /* support multiple processors */
61
62#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053063#define CONFIG_SYS_TEXT_BASE 0xeff40000
York Sun0789dc92012-12-23 19:25:27 +000064#endif
65
66#ifndef CONFIG_RESET_VECTOR_ADDRESS
67#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
68#endif
69
70#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
71#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
72#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta12af67f2014-10-15 11:35:31 +053073#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Robert P. J. Daya8099812016-05-03 19:52:49 -040074#define CONFIG_PCIE1 /* PCIE controller 1 */
York Sun0789dc92012-12-23 19:25:27 +000075#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
76#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
77
78#ifndef CONFIG_PPC_B4420
79#define CONFIG_SYS_SRIO
80#define CONFIG_SRIO1 /* SRIO port 1 */
81#define CONFIG_SRIO2 /* SRIO port 2 */
Liu Gangc13bc8f2013-05-07 16:30:47 +080082#define CONFIG_SRIO_PCIE_BOOT_MASTER
York Sun0789dc92012-12-23 19:25:27 +000083#endif
84
85#define CONFIG_FSL_LAW /* Use common FSL init code */
86
87/* I2C bus multiplexer */
88#define I2C_MUX_PCA_ADDR 0x77
89
90/* VSC Crossbar switches */
91#define CONFIG_VSC_CROSSBAR
92#define I2C_CH_DEFAULT 0x8
93#define I2C_CH_VSC3316 0xc
94#define I2C_CH_VSC3308 0xd
95
96#define VSC3316_TX_ADDRESS 0x70
97#define VSC3316_RX_ADDRESS 0x71
98#define VSC3308_TX_ADDRESS 0x02
99#define VSC3308_RX_ADDRESS 0x03
100
Shaveta Leekhad1cb7742013-07-02 14:43:53 +0530101/* IDT clock synthesizers */
102#define CONFIG_IDT8T49N222A
103#define I2C_CH_IDT 0x9
104
105#define IDT_SERDES1_ADDRESS 0x6E
106#define IDT_SERDES2_ADDRESS 0x6C
107
Shaveta Leekhae1b6f4c2014-04-11 14:12:40 +0530108/* Voltage monitor on channel 2*/
109#define I2C_MUX_CH_VOL_MONITOR 0xa
110#define I2C_VOL_MONITOR_ADDR 0x40
111#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
112#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
113#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
114
115#define CONFIG_ZM7300
116#define I2C_MUX_CH_DPM 0xa
117#define I2C_DPM_ADDR 0x28
118
York Sun0789dc92012-12-23 19:25:27 +0000119#define CONFIG_ENV_OVERWRITE
120
121#ifdef CONFIG_SYS_NO_FLASH
Liu Gang0ff15f92013-05-07 16:30:48 +0800122#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
York Sun0789dc92012-12-23 19:25:27 +0000123#define CONFIG_ENV_IS_NOWHERE
Liu Gang0ff15f92013-05-07 16:30:48 +0800124#endif
York Sun0789dc92012-12-23 19:25:27 +0000125#else
126#define CONFIG_FLASH_CFI_DRIVER
127#define CONFIG_SYS_FLASH_CFI
128#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
129#endif
130
York Sun0789dc92012-12-23 19:25:27 +0000131#if defined(CONFIG_SPIFLASH)
132#define CONFIG_SYS_EXTRA_ENV_RELOC
133#define CONFIG_ENV_IS_IN_SPI_FLASH
134#define CONFIG_ENV_SPI_BUS 0
135#define CONFIG_ENV_SPI_CS 0
136#define CONFIG_ENV_SPI_MAX_HZ 10000000
137#define CONFIG_ENV_SPI_MODE 0
138#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
139#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
140#define CONFIG_ENV_SECT_SIZE 0x10000
141#elif defined(CONFIG_SDCARD)
142#define CONFIG_SYS_EXTRA_ENV_RELOC
143#define CONFIG_ENV_IS_IN_MMC
144#define CONFIG_SYS_MMC_ENV_DEV 0
145#define CONFIG_ENV_SIZE 0x2000
146#define CONFIG_ENV_OFFSET (512 * 1097)
147#elif defined(CONFIG_NAND)
148#define CONFIG_SYS_EXTRA_ENV_RELOC
149#define CONFIG_ENV_IS_IN_NAND
Prabhakar Kushwaha33542982014-04-08 19:13:44 +0530150#define CONFIG_ENV_SIZE 0x2000
151#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang0ff15f92013-05-07 16:30:48 +0800152#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
153#define CONFIG_ENV_IS_IN_REMOTE
154#define CONFIG_ENV_ADDR 0xffe20000
155#define CONFIG_ENV_SIZE 0x2000
156#elif defined(CONFIG_ENV_IS_NOWHERE)
157#define CONFIG_ENV_SIZE 0x2000
York Sun0789dc92012-12-23 19:25:27 +0000158#else
159#define CONFIG_ENV_IS_IN_FLASH
160#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
161#define CONFIG_ENV_SIZE 0x2000
162#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
163#endif
York Sun0789dc92012-12-23 19:25:27 +0000164
165#ifndef __ASSEMBLY__
166unsigned long get_board_sys_clk(void);
167unsigned long get_board_ddr_clk(void);
168#endif
169#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
170#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
171
172/*
173 * These can be toggled for performance analysis, otherwise use default.
174 */
175#define CONFIG_SYS_CACHE_STASHING
176#define CONFIG_BTB /* toggle branch predition */
177#define CONFIG_DDR_ECC
178#ifdef CONFIG_DDR_ECC
179#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
180#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
181#endif
182
183#define CONFIG_ENABLE_36BIT_PHYS
184
185#ifdef CONFIG_PHYS_64BIT
186#define CONFIG_ADDR_MAP
187#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
188#endif
189
190#if 0
191#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
192#endif
193#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
194#define CONFIG_SYS_MEMTEST_END 0x00400000
195#define CONFIG_SYS_ALT_MEMTEST
196#define CONFIG_PANIC_HANG /* do not reset board on panic */
197
198/*
199 * Config the L3 Cache as L3 SRAM
200 */
Prabhakar Kushwaha33542982014-04-08 19:13:44 +0530201#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
202#define CONFIG_SYS_L3_SIZE 256 << 10
203#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
204#ifdef CONFIG_NAND
205#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
206#endif
207#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
208#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
209#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
210#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
York Sun0789dc92012-12-23 19:25:27 +0000211
212#ifdef CONFIG_PHYS_64BIT
213#define CONFIG_SYS_DCSRBAR 0xf0000000
214#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
215#endif
216
217/* EEPROM */
Shaveta Leekha35a95292014-09-04 16:17:09 +0530218#define CONFIG_ID_EEPROM
York Sun0789dc92012-12-23 19:25:27 +0000219#define CONFIG_SYS_I2C_EEPROM_NXID
220#define CONFIG_SYS_EEPROM_BUS_NUM 0
221#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
222#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
223#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
224#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
225
226/*
227 * DDR Setup
228 */
229#define CONFIG_VERY_BIG_RAM
230#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
231#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
232
233/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
234#define CONFIG_DIMM_SLOTS_PER_CTLR 1
235#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
236
237#define CONFIG_DDR_SPD
238#define CONFIG_SYS_DDR_RAW_TIMING
York Sunf0626592013-09-30 09:22:09 -0700239#define CONFIG_SYS_FSL_DDR3
Prabhakar Kushwaha33542982014-04-08 19:13:44 +0530240#ifndef CONFIG_SPL_BUILD
York Sun0789dc92012-12-23 19:25:27 +0000241#define CONFIG_FSL_DDR_INTERACTIVE
Prabhakar Kushwaha33542982014-04-08 19:13:44 +0530242#endif
York Sun0789dc92012-12-23 19:25:27 +0000243
244#define CONFIG_SYS_SPD_BUS_NUM 0
245#define SPD_EEPROM_ADDRESS1 0x51
246#define SPD_EEPROM_ADDRESS2 0x53
247
248#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
249#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
250
251/*
252 * IFC Definitions
253 */
254#define CONFIG_SYS_FLASH_BASE 0xe0000000
255#ifdef CONFIG_PHYS_64BIT
256#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
257#else
258#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
259#endif
260
261#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
262#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
263 + 0x8000000) | \
264 CSPR_PORT_SIZE_16 | \
265 CSPR_MSEL_NOR | \
266 CSPR_V)
267#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
268#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
269 CSPR_PORT_SIZE_16 | \
270 CSPR_MSEL_NOR | \
271 CSPR_V)
272#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
273/* NOR Flash Timing Params */
274#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
275#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
Prabhakar Kushwahae905f032013-05-17 13:40:52 +0530276 FTIM0_NOR_TEADC(0x04) | \
York Sun0789dc92012-12-23 19:25:27 +0000277 FTIM0_NOR_TEAHC(0x20))
278#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
279 FTIM1_NOR_TRAD_NOR(0x1A) |\
280 FTIM1_NOR_TSEQRAD_NOR(0x13))
281#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
282 FTIM2_NOR_TCH(0x0E) | \
283 FTIM2_NOR_TWPH(0x0E) | \
284 FTIM2_NOR_TWP(0x1c))
285#define CONFIG_SYS_NOR_FTIM3 0x0
286
287#define CONFIG_SYS_FLASH_QUIET_TEST
288#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
289
290#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
291#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
292#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
293#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
294
295#define CONFIG_SYS_FLASH_EMPTY_INFO
296#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
297 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
298
299#define CONFIG_FSL_QIXIS /* use common QIXIS code */
300#define CONFIG_FSL_QIXIS_V2
301#define QIXIS_BASE 0xffdf0000
302#ifdef CONFIG_PHYS_64BIT
303#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
304#else
305#define QIXIS_BASE_PHYS QIXIS_BASE
306#endif
307#define QIXIS_LBMAP_SWITCH 0x01
308#define QIXIS_LBMAP_MASK 0x0f
309#define QIXIS_LBMAP_SHIFT 0
310#define QIXIS_LBMAP_DFLTBANK 0x00
311#define QIXIS_LBMAP_ALTBANK 0x02
312#define QIXIS_RST_CTL_RESET 0x31
313#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
314#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
315#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
316
317#define CONFIG_SYS_CSPR3_EXT (0xf)
318#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
319 | CSPR_PORT_SIZE_8 \
320 | CSPR_MSEL_GPCM \
321 | CSPR_V)
322#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
323#define CONFIG_SYS_CSOR3 0x0
324/* QIXIS Timing parameters for IFC CS3 */
325#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
326 FTIM0_GPCM_TEADC(0x0e) | \
327 FTIM0_GPCM_TEAHC(0x0e))
328#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
329 FTIM1_GPCM_TRAD(0x1f))
330#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiec2bc4602014-06-26 14:41:33 +0800331 FTIM2_GPCM_TCH(0x8) | \
York Sun0789dc92012-12-23 19:25:27 +0000332 FTIM2_GPCM_TWP(0x1f))
333#define CONFIG_SYS_CS3_FTIM3 0x0
334
335/* NAND Flash on IFC */
336#define CONFIG_NAND_FSL_IFC
York Sun83cbd0c2013-12-17 11:21:09 -0800337#define CONFIG_SYS_NAND_MAX_ECCPOS 256
338#define CONFIG_SYS_NAND_MAX_OOBFREE 2
York Sun0789dc92012-12-23 19:25:27 +0000339#define CONFIG_SYS_NAND_BASE 0xff800000
340#ifdef CONFIG_PHYS_64BIT
341#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
342#else
343#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
344#endif
345
346#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
347#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
348 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
349 | CSPR_MSEL_NAND /* MSEL = NAND */ \
350 | CSPR_V)
351#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
352
353#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
354 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
355 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
356 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
357 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
358 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
359 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
360
361#define CONFIG_SYS_NAND_ONFI_DETECTION
362
363/* ONFI NAND Flash mode0 Timing Params */
364#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
365 FTIM0_NAND_TWP(0x18) | \
366 FTIM0_NAND_TWCHT(0x07) | \
367 FTIM0_NAND_TWH(0x0a))
368#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
369 FTIM1_NAND_TWBE(0x39) | \
370 FTIM1_NAND_TRR(0x0e) | \
371 FTIM1_NAND_TRP(0x18))
372#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
373 FTIM2_NAND_TREH(0x0a) | \
374 FTIM2_NAND_TWHRE(0x1e))
375#define CONFIG_SYS_NAND_FTIM3 0x0
376
377#define CONFIG_SYS_NAND_DDR_LAW 11
378
379#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
380#define CONFIG_SYS_MAX_NAND_DEVICE 1
York Sun0789dc92012-12-23 19:25:27 +0000381#define CONFIG_CMD_NAND
382
383#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
384
385#if defined(CONFIG_NAND)
386#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
387#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
388#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
389#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
390#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
391#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
392#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
393#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
394#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
395#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
396#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
397#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
398#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
399#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
400#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
401#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
402#else
403#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
404#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
405#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
406#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
407#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
408#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
409#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
410#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
411#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
412#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
413#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
414#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
415#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
416#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
417#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
418#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
419#endif
420#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
421#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
422#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
423#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
424#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
425#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
426#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
427#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
428
Prabhakar Kushwaha33542982014-04-08 19:13:44 +0530429#ifdef CONFIG_SPL_BUILD
430#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
431#else
432#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
433#endif
York Sun0789dc92012-12-23 19:25:27 +0000434
435#if defined(CONFIG_RAMBOOT_PBL)
436#define CONFIG_SYS_RAMBOOT
437#endif
438
439#define CONFIG_BOARD_EARLY_INIT_R
440#define CONFIG_MISC_INIT_R
441
442#define CONFIG_HWCONFIG
443
444/* define to use L1 as initial stack */
445#define CONFIG_L1_INIT_RAM
446#define CONFIG_SYS_INIT_RAM_LOCK
447#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
448#ifdef CONFIG_PHYS_64BIT
449#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunee7b4832015-08-17 13:31:51 -0700450#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
York Sun0789dc92012-12-23 19:25:27 +0000451/* The assembler doesn't like typecast */
452#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
453 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
454 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
455#else
York Sunee7b4832015-08-17 13:31:51 -0700456#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
York Sun0789dc92012-12-23 19:25:27 +0000457#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
458#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
459#endif
460#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
461
462#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
463 GENERATED_GBL_DATA_SIZE)
464#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
465
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530466#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
York Sun0789dc92012-12-23 19:25:27 +0000467#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
468
469/* Serial Port - controlled on board with jumper J8
470 * open - index 2
471 * shorted - index 1
472 */
473#define CONFIG_CONS_INDEX 1
York Sun0789dc92012-12-23 19:25:27 +0000474#define CONFIG_SYS_NS16550_SERIAL
475#define CONFIG_SYS_NS16550_REG_SIZE 1
476#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
477
478#define CONFIG_SYS_BAUDRATE_TABLE \
479 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
480
481#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
482#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
483#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
484#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
York Sun0789dc92012-12-23 19:25:27 +0000485
York Sun0789dc92012-12-23 19:25:27 +0000486/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200487#define CONFIG_SYS_I2C
488#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
489#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
490#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
491#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
492#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
493#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
494#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
York Sun0789dc92012-12-23 19:25:27 +0000495
496/*
497 * RTC configuration
498 */
499#define RTC
500#define CONFIG_RTC_DS3231 1
501#define CONFIG_SYS_I2C_RTC_ADDR 0x68
502
503/*
504 * RapidIO
505 */
506#ifdef CONFIG_SYS_SRIO
507#ifdef CONFIG_SRIO1
508#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
509#ifdef CONFIG_PHYS_64BIT
510#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
511#else
512#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
513#endif
514#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
515#endif
516
517#ifdef CONFIG_SRIO2
518#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
519#ifdef CONFIG_PHYS_64BIT
520#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
521#else
522#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
523#endif
524#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
525#endif
526#endif
527
528/*
529 * for slave u-boot IMAGE instored in master memory space,
530 * PHYS must be aligned based on the SIZE
531 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800532#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
533#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
534#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
535#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
York Sun0789dc92012-12-23 19:25:27 +0000536/*
537 * for slave UCODE and ENV instored in master memory space,
538 * PHYS must be aligned based on the SIZE
539 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800540#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
York Sun0789dc92012-12-23 19:25:27 +0000541#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
542#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
543
544/* slave core release by master*/
545#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
546#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
547
548/*
549 * SRIO_PCIE_BOOT - SLAVE
550 */
551#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
552#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
553#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
554 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
555#endif
556
557/*
558 * eSPI - Enhanced SPI
559 */
York Sun0789dc92012-12-23 19:25:27 +0000560#define CONFIG_SF_DEFAULT_SPEED 10000000
561#define CONFIG_SF_DEFAULT_MODE 0
562
563/*
Shaveta Leekha43e0f7b2013-03-25 07:40:24 +0000564 * MAPLE
565 */
566#ifdef CONFIG_PHYS_64BIT
567#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
568#else
569#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
570#endif
571
572/*
York Sun0789dc92012-12-23 19:25:27 +0000573 * General PCI
574 * Memory space is mapped 1-1, but I/O space must start from 0.
575 */
576
577/* controller 1, direct to uli, tgtid 3, Base address 20000 */
578#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
579#ifdef CONFIG_PHYS_64BIT
580#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
581#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
582#else
583#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
584#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
585#endif
586#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
587#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
588#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
589#ifdef CONFIG_PHYS_64BIT
590#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
591#else
592#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
593#endif
594#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
595
596/* Qman/Bman */
597#ifndef CONFIG_NOBQFMAN
598#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
599#define CONFIG_SYS_BMAN_NUM_PORTALS 25
600#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
601#ifdef CONFIG_PHYS_64BIT
602#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
603#else
604#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
605#endif
606#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500607#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
608#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
609#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
610#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
611#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
612 CONFIG_SYS_BMAN_CENA_SIZE)
613#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
614#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
York Sun0789dc92012-12-23 19:25:27 +0000615#define CONFIG_SYS_QMAN_NUM_PORTALS 25
616#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
617#ifdef CONFIG_PHYS_64BIT
618#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
619#else
620#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
621#endif
622#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500623#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
624#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
625#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
626#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
627#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
628 CONFIG_SYS_QMAN_CENA_SIZE)
629#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
630#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
York Sun0789dc92012-12-23 19:25:27 +0000631
632#define CONFIG_SYS_DPAA_FMAN
633
Minghuan Lian621de442013-07-03 18:32:41 +0800634#define CONFIG_SYS_DPAA_RMAN
635
York Sun0789dc92012-12-23 19:25:27 +0000636/* Default address of microcode for the Linux Fman driver */
637#if defined(CONFIG_SPIFLASH)
638/*
639 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
640 * env, so we got 0x110000.
641 */
642#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiang83a90842014-03-21 16:21:44 +0800643#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
York Sun0789dc92012-12-23 19:25:27 +0000644#elif defined(CONFIG_SDCARD)
645/*
646 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
647 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
648 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
649 */
650#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Zhao Qiang83a90842014-03-21 16:21:44 +0800651#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
York Sun0789dc92012-12-23 19:25:27 +0000652#elif defined(CONFIG_NAND)
653#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Prabhakar Kushwaha33542982014-04-08 19:13:44 +0530654#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang0ff15f92013-05-07 16:30:48 +0800655#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
656/*
657 * Slave has no ucode locally, it can fetch this from remote. When implementing
658 * in two corenet boards, slave's ucode could be stored in master's memory
659 * space, the address can be mapped from slave TLB->slave LAW->
660 * slave SRIO or PCIE outbound window->master inbound window->
661 * master LAW->the ucode address in master's memory space.
662 */
663#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Zhao Qiang83a90842014-03-21 16:21:44 +0800664#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
York Sun0789dc92012-12-23 19:25:27 +0000665#else
666#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiang83a90842014-03-21 16:21:44 +0800667#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
York Sun0789dc92012-12-23 19:25:27 +0000668#endif
669#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
670#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
671#endif /* CONFIG_NOBQFMAN */
672
673#ifdef CONFIG_SYS_DPAA_FMAN
674#define CONFIG_FMAN_ENET
675#define CONFIG_PHYLIB_10G
676#define CONFIG_PHY_VITESSE
677#define CONFIG_PHY_TERANETICS
678#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
679#define SGMII_CARD_PORT2_PHY_ADDR 0x10
680#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
681#define SGMII_CARD_PORT4_PHY_ADDR 0x11
682#endif
683
684#ifdef CONFIG_PCI
Gabor Juhosb4458732013-05-30 07:06:12 +0000685#define CONFIG_PCI_INDIRECT_BRIDGE
York Sun0789dc92012-12-23 19:25:27 +0000686
687#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
688#define CONFIG_DOS_PARTITION
689#endif /* CONFIG_PCI */
690
691#ifdef CONFIG_FMAN_ENET
Shaveta Leekha7c689e22014-11-12 16:00:22 +0530692#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
693#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
Suresh Gupta4c3db712013-03-25 07:40:13 +0000694
695/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
696#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
697#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
698
York Sun0789dc92012-12-23 19:25:27 +0000699#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
700#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
701#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
702#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
703
704#define CONFIG_MII /* MII PHY management */
705#define CONFIG_ETHPRIME "FM1@DTSEC1"
706#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
707#endif
708
Shaohui Xie60c3b092014-11-13 11:27:49 +0800709#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
710
York Sun0789dc92012-12-23 19:25:27 +0000711/*
712 * Environment
713 */
714#define CONFIG_LOADS_ECHO /* echo on for serial download */
715#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
716
717/*
718 * Command line configuration.
719 */
York Sun0789dc92012-12-23 19:25:27 +0000720#define CONFIG_CMD_DATE
York Sun0789dc92012-12-23 19:25:27 +0000721#define CONFIG_CMD_EEPROM
York Sun0789dc92012-12-23 19:25:27 +0000722#define CONFIG_CMD_ERRATA
York Sun0789dc92012-12-23 19:25:27 +0000723#define CONFIG_CMD_IRQ
York Sun0789dc92012-12-23 19:25:27 +0000724#define CONFIG_CMD_REGINFO
York Sun0789dc92012-12-23 19:25:27 +0000725
726#ifdef CONFIG_PCI
727#define CONFIG_CMD_PCI
York Sun0789dc92012-12-23 19:25:27 +0000728#endif
729
Ruchika Gupta12af67f2014-10-15 11:35:31 +0530730/* Hash command with SHA acceleration supported in hardware */
731#ifdef CONFIG_FSL_CAAM
732#define CONFIG_CMD_HASH
733#define CONFIG_SHA_HW_ACCEL
734#endif
735
York Sun0789dc92012-12-23 19:25:27 +0000736/*
737* USB
738*/
739#define CONFIG_HAS_FSL_DR_USB
740
741#ifdef CONFIG_HAS_FSL_DR_USB
742#define CONFIG_USB_EHCI
743
744#ifdef CONFIG_USB_EHCI
York Sun0789dc92012-12-23 19:25:27 +0000745#define CONFIG_USB_EHCI_FSL
746#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
York Sun0789dc92012-12-23 19:25:27 +0000747#endif
748#endif
749
750/*
751 * Miscellaneous configurable options
752 */
753#define CONFIG_SYS_LONGHELP /* undef to save memory */
754#define CONFIG_CMDLINE_EDITING /* Command-line editing */
755#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
756#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
York Sun0789dc92012-12-23 19:25:27 +0000757#ifdef CONFIG_CMD_KGDB
758#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
759#else
760#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
761#endif
762#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
763#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
764#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
York Sun0789dc92012-12-23 19:25:27 +0000765
766/*
767 * For booting Linux, the board info and command line data
768 * have to be in the first 64 MB of memory, since this is
769 * the maximum mapped by the Linux kernel during initialization.
770 */
771#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
772#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
773
774#ifdef CONFIG_CMD_KGDB
775#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
York Sun0789dc92012-12-23 19:25:27 +0000776#endif
777
778/*
779 * Environment Configuration
780 */
781#define CONFIG_ROOTPATH "/opt/nfsroot"
782#define CONFIG_BOOTFILE "uImage"
783#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
784
785/* default location for tftp and bootm */
786#define CONFIG_LOADADDR 1000000
787
York Sun0789dc92012-12-23 19:25:27 +0000788
789#define CONFIG_BAUDRATE 115200
790
791#define __USB_PHY_TYPE ulpi
792
Shaveta Leekha82699a62014-09-04 11:43:57 +0530793#ifdef CONFIG_PPC_B4860
794#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
795 "bank_intlv=cs0_cs1;" \
796 "en_cpc:cpc2;"
797#else
798#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
799#endif
800
York Sun0789dc92012-12-23 19:25:27 +0000801#define CONFIG_EXTRA_ENV_SETTINGS \
Shaveta Leekha82699a62014-09-04 11:43:57 +0530802 HWCONFIG \
York Sun0789dc92012-12-23 19:25:27 +0000803 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
804 "netdev=eth0\0" \
805 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
806 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
807 "tftpflash=tftpboot $loadaddr $uboot && " \
808 "protect off $ubootaddr +$filesize && " \
809 "erase $ubootaddr +$filesize && " \
810 "cp.b $loadaddr $ubootaddr $filesize && " \
811 "protect on $ubootaddr +$filesize && " \
812 "cmp.b $loadaddr $ubootaddr $filesize\0" \
813 "consoledev=ttyS0\0" \
814 "ramdiskaddr=2000000\0" \
815 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500816 "fdtaddr=1e00000\0" \
York Sun0789dc92012-12-23 19:25:27 +0000817 "fdtfile=b4860qds/b4860qds.dtb\0" \
Kim Phillips1dedccc2014-05-14 19:33:45 -0500818 "bdev=sda3\0"
York Sun0789dc92012-12-23 19:25:27 +0000819
820/* For emulation this causes u-boot to jump to the start of the proof point
821 app code automatically */
822#define CONFIG_PROOF_POINTS \
823 "setenv bootargs root=/dev/$bdev rw " \
824 "console=$consoledev,$baudrate $othbootargs;" \
825 "cpu 1 release 0x29000000 - - -;" \
826 "cpu 2 release 0x29000000 - - -;" \
827 "cpu 3 release 0x29000000 - - -;" \
828 "cpu 4 release 0x29000000 - - -;" \
829 "cpu 5 release 0x29000000 - - -;" \
830 "cpu 6 release 0x29000000 - - -;" \
831 "cpu 7 release 0x29000000 - - -;" \
832 "go 0x29000000"
833
834#define CONFIG_HVBOOT \
835 "setenv bootargs config-addr=0x60000000; " \
836 "bootm 0x01000000 - 0x00f00000"
837
838#define CONFIG_ALU \
839 "setenv bootargs root=/dev/$bdev rw " \
840 "console=$consoledev,$baudrate $othbootargs;" \
841 "cpu 1 release 0x01000000 - - -;" \
842 "cpu 2 release 0x01000000 - - -;" \
843 "cpu 3 release 0x01000000 - - -;" \
844 "cpu 4 release 0x01000000 - - -;" \
845 "cpu 5 release 0x01000000 - - -;" \
846 "cpu 6 release 0x01000000 - - -;" \
847 "cpu 7 release 0x01000000 - - -;" \
848 "go 0x01000000"
849
850#define CONFIG_LINUX \
851 "setenv bootargs root=/dev/ram rw " \
852 "console=$consoledev,$baudrate $othbootargs;" \
853 "setenv ramdiskaddr 0x02000000;" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500854 "setenv fdtaddr 0x01e00000;" \
York Sun0789dc92012-12-23 19:25:27 +0000855 "setenv loadaddr 0x1000000;" \
856 "bootm $loadaddr $ramdiskaddr $fdtaddr"
857
858#define CONFIG_HDBOOT \
859 "setenv bootargs root=/dev/$bdev rw " \
860 "console=$consoledev,$baudrate $othbootargs;" \
861 "tftp $loadaddr $bootfile;" \
862 "tftp $fdtaddr $fdtfile;" \
863 "bootm $loadaddr - $fdtaddr"
864
865#define CONFIG_NFSBOOTCOMMAND \
866 "setenv bootargs root=/dev/nfs rw " \
867 "nfsroot=$serverip:$rootpath " \
868 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
869 "console=$consoledev,$baudrate $othbootargs;" \
870 "tftp $loadaddr $bootfile;" \
871 "tftp $fdtaddr $fdtfile;" \
872 "bootm $loadaddr - $fdtaddr"
873
874#define CONFIG_RAMBOOTCOMMAND \
875 "setenv bootargs root=/dev/ram rw " \
876 "console=$consoledev,$baudrate $othbootargs;" \
877 "tftp $ramdiskaddr $ramdiskfile;" \
878 "tftp $loadaddr $bootfile;" \
879 "tftp $fdtaddr $fdtfile;" \
880 "bootm $loadaddr $ramdiskaddr $fdtaddr"
881
882#define CONFIG_BOOTCOMMAND CONFIG_LINUX
883
York Sun0789dc92012-12-23 19:25:27 +0000884#include <asm/fsl_secure_boot.h>
York Sun0789dc92012-12-23 19:25:27 +0000885
York Sun0789dc92012-12-23 19:25:27 +0000886#endif /* __CONFIG_H */