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git01.mediatek.com / filogic / uboot / 3024ebd365cd4fba6b43f92208deac689c2c3407 / . / arch / arm / cpu / arm926ejs / start.S
blob: 0afcc47aad7d4d522d6f50c14a166bb3a950e511 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]2/*
3 * armboot - Startup Code for ARM926EJS CPU-core
4 *
5 * Copyright (c) 2003 Texas Instruments
6 *
wdenke3a06802004-06-06 23:13:55 +0000[diff] [blame]7 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]8 *
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200[diff] [blame]9 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
10 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
Detlev Zundelf1b3f2b2009-05-13 10:54:10 +0200[diff] [blame]11 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]12 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
13 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
Albert ARIBAUD340983d2011-04-22 19:41:02 +0200[diff] [blame]14 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]15 */
16
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]17#include <asm-offsets.h>
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]18#include <config.h>
Wolfgang Denk66e8d442009-07-24 00:17:48 +0200[diff] [blame]19#include <common.h>
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]20
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]21/*
22 *************************************************************************
23 *
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]24 * Startup Code (reset vector)
25 *
26 * do important init only if we don't start from memory!
27 * setup Memory and board specific bits prior to relocation.
28 * relocate armboot to ram
29 * setup stack
30 *
31 *************************************************************************
32 */
33
Albert ARIBAUD9852cc62014-04-15 16:13:51 +0200[diff] [blame]34 .globl reset
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200[diff] [blame]35
36reset:
37 /*
38 * set the cpu to SVC32 mode
39 */
40 mrs r0,cpsr
41 bic r0,r0,#0x1f
42 orr r0,r0,#0xd3
43 msr cpsr,r0
44
45 /*
46 * we do sys-critical inits only at reboot,
47 * not when booting from ram!
48 */
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]49#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200[diff] [blame]50 bl cpu_init_crit
Christian Riesch11bf5762012-02-02 00:44:37 +0000[diff] [blame]51#endif
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200[diff] [blame]52
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000[diff] [blame]53 bl _main
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200[diff] [blame]54
55/*------------------------------------------------------------------------------*/
56
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000[diff] [blame]57 .globl c_runtime_cpu_setup
58c_runtime_cpu_setup:
59
60 bx lr
61
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]62/*
63 *************************************************************************
64 *
65 * CPU_init_critical registers
66 *
67 * setup important registers
68 * setup memory timing
69 *
70 *************************************************************************
71 */
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]72#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]73cpu_init_crit:
74 /*
Sughosh Ganu4cb71862012-02-02 00:44:38 +0000[diff] [blame]75 * flush D cache before disabling it
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]76 */
77 mov r0, #0
Sughosh Ganu4cb71862012-02-02 00:44:38 +0000[diff] [blame]78flush_dcache:
79 mrc p15, 0, r15, c7, c10, 3
80 bne flush_dcache
81
82 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
83 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]84
85 /*
Christian Riescha927d262012-02-02 00:44:40 +0000[diff] [blame]86 * disable MMU and D cache
Trevor Woerner43ec7e02019-05-03 09:41:00 -0400[diff] [blame]87 * enable I cache if SYS_ICACHE_OFF is not defined
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]88 */
89 mrc p15, 0, r0, c1, c0, 0
Christian Riesch48c2d6d2012-02-02 00:44:39 +0000[diff] [blame]90 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]91 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
Christian Riesch48c2d6d2012-02-02 00:44:39 +0000[diff] [blame]92#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
93 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
94#else
95 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
96#endif
Yuichiro Goto8d4b7e92016-02-25 10:23:34 +0900[diff] [blame]97 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
Trevor Woerner43ec7e02019-05-03 09:41:00 -0400[diff] [blame]98#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]99 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
Christian Riescha927d262012-02-02 00:44:40 +0000[diff] [blame]100#endif
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]101 mcr p15, 0, r0, c1, c0, 0
102
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]103#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]104 /*
105 * Go setup Memory and board specific bits prior to relocation.
106 */
Mans Rullgard96db04f2018-04-21 16:11:07 +0100[diff] [blame]107 mov r4, lr /* perserve link reg across call */
Wolfgang Denk7f88a5e2005-10-06 17:08:18 +0200[diff] [blame]108 bl lowlevel_init /* go setup pll,mux,memory */
Mans Rullgard96db04f2018-04-21 16:11:07 +0100[diff] [blame]109 mov lr, r4 /* restore link */
Simon Glass90844072016-05-05 07:28:06 -0600[diff] [blame]110#endif
Heiko Schocherc8a6d752011-11-09 20:06:23 +0000[diff] [blame]111 mov pc, lr /* back to my caller */
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]112#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */