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Stefan Roesed07117e2007-02-20 10:27:08 +01001/*
Stefan Roese77c1f1d2009-11-19 14:03:17 +01002 * (C) Copyright 2007-2009
Stefan Roesed07117e2007-02-20 10:27:08 +01003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
6 *
7 * (C) Copyright 2001
8 * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
wdenkc6097192002-11-03 00:24:07 +000028
29#include <common.h>
30#include <ppc4xx.h>
Stefan Roesed07117e2007-02-20 10:27:08 +010031#include <4xx_i2c.h>
wdenkc6097192002-11-03 00:24:07 +000032#include <i2c.h>
Stefan Roesed07117e2007-02-20 10:27:08 +010033#include <asm-ppc/io.h>
wdenkc6097192002-11-03 00:24:07 +000034
35#ifdef CONFIG_HARD_I2C
36
Wolfgang Denk6405a152006-03-31 18:32:53 +020037DECLARE_GLOBAL_DATA_PTR;
38
Stefan Roesed07117e2007-02-20 10:27:08 +010039#if defined(CONFIG_I2C_MULTI_BUS)
Stefan Roese77c1f1d2009-11-19 14:03:17 +010040/*
41 * Initialize the bus pointer to whatever one the SPD EEPROM is on.
Stefan Roesed07117e2007-02-20 10:27:08 +010042 * Default is bus 0. This is necessary because the DDR initialization
43 * runs from ROM, and we can't switch buses because we can't modify
44 * the global variables.
45 */
Trent Piepho3e9dabd2008-11-12 17:29:48 -080046#ifndef CONFIG_SYS_SPD_BUS_NUM
47#define CONFIG_SYS_SPD_BUS_NUM 0
Stefan Roesed07117e2007-02-20 10:27:08 +010048#endif
Stefan Roese77c1f1d2009-11-19 14:03:17 +010049static unsigned int i2c_bus_num __attribute__ ((section (".data"))) =
50 CONFIG_SYS_SPD_BUS_NUM;
Stefan Roesed07117e2007-02-20 10:27:08 +010051#endif /* CONFIG_I2C_MULTI_BUS */
wdenkc6097192002-11-03 00:24:07 +000052
Stefan Roesed07117e2007-02-20 10:27:08 +010053static void _i2c_bus_reset(void)
wdenkc6097192002-11-03 00:24:07 +000054{
Stefan Roese77c1f1d2009-11-19 14:03:17 +010055 struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
Stefan Roesed07117e2007-02-20 10:27:08 +010056 int i;
57 u8 dc;
wdenkc6097192002-11-03 00:24:07 +000058
59 /* Reset status register */
60 /* write 1 in SCMP and IRQA to clear these fields */
Stefan Roese77c1f1d2009-11-19 14:03:17 +010061 out_8(&i2c->sts, 0x0A);
wdenkc6097192002-11-03 00:24:07 +000062
63 /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
Stefan Roese77c1f1d2009-11-19 14:03:17 +010064 out_8(&i2c->extsts, 0x8F);
wdenkc6097192002-11-03 00:24:07 +000065
Wolfgang Denka1be4762008-05-20 16:00:29 +020066 /* Place chip in the reset state */
Stefan Roese77c1f1d2009-11-19 14:03:17 +010067 out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
wdenkc6097192002-11-03 00:24:07 +000068
Stefan Roesed07117e2007-02-20 10:27:08 +010069 /* Check if bus is free */
Stefan Roese77c1f1d2009-11-19 14:03:17 +010070 dc = in_8(&i2c->directcntl);
Stefan Roesed07117e2007-02-20 10:27:08 +010071 if (!DIRCTNL_FREE(dc)){
72 /* Try to set bus free state */
Stefan Roese77c1f1d2009-11-19 14:03:17 +010073 out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
Stefan Roesed07117e2007-02-20 10:27:08 +010074
75 /* Wait until we regain bus control */
76 for (i = 0; i < 100; ++i) {
Stefan Roese77c1f1d2009-11-19 14:03:17 +010077 dc = in_8(&i2c->directcntl);
Stefan Roesed07117e2007-02-20 10:27:08 +010078 if (DIRCTNL_FREE(dc))
79 break;
80
81 /* Toggle SCL line */
82 dc ^= IIC_DIRCNTL_SCC;
Stefan Roese77c1f1d2009-11-19 14:03:17 +010083 out_8(&i2c->directcntl, dc);
Stefan Roesed07117e2007-02-20 10:27:08 +010084 udelay(10);
85 dc ^= IIC_DIRCNTL_SCC;
Stefan Roese77c1f1d2009-11-19 14:03:17 +010086 out_8(&i2c->directcntl, dc);
wdenkc6097192002-11-03 00:24:07 +000087 }
88 }
Stefan Roesed07117e2007-02-20 10:27:08 +010089
90 /* Remove reset */
Stefan Roese77c1f1d2009-11-19 14:03:17 +010091 out_8(&i2c->xtcntlss, 0);
wdenkc6097192002-11-03 00:24:07 +000092}
93
Stefan Roese77c1f1d2009-11-19 14:03:17 +010094void i2c_init(int speed, int slaveaddr)
wdenkc6097192002-11-03 00:24:07 +000095{
Stefan Roese77c1f1d2009-11-19 14:03:17 +010096 struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
wdenkc6097192002-11-03 00:24:07 +000097 int val, divisor;
Stefan Roesed07117e2007-02-20 10:27:08 +010098 int bus;
wdenkc6097192002-11-03 00:24:07 +000099
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#ifdef CONFIG_SYS_I2C_INIT_BOARD
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100101 /*
102 * Call board specific i2c bus reset routine before accessing the
103 * environment, which might be in a chip on that bus. For details
104 * about this problem see doc/I2C_Edge_Conditions.
105 */
wdenkcc1e2562003-03-06 13:39:27 +0000106 i2c_init_board();
107#endif
108
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200109 for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) {
Stefan Roesed07117e2007-02-20 10:27:08 +0100110 I2C_SET_BUS(bus);
wdenkc6097192002-11-03 00:24:07 +0000111
Stefan Roesed07117e2007-02-20 10:27:08 +0100112 /* Handle possible failed I2C state */
113 /* FIXME: put this into i2c_init_board()? */
114 _i2c_bus_reset();
wdenkc6097192002-11-03 00:24:07 +0000115
Stefan Roesed07117e2007-02-20 10:27:08 +0100116 /* clear lo master address */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100117 out_8(&i2c->lmadr, 0);
wdenkc6097192002-11-03 00:24:07 +0000118
Stefan Roesed07117e2007-02-20 10:27:08 +0100119 /* clear hi master address */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100120 out_8(&i2c->hmadr, 0);
wdenkc6097192002-11-03 00:24:07 +0000121
Stefan Roesed07117e2007-02-20 10:27:08 +0100122 /* clear lo slave address */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100123 out_8(&i2c->lsadr, 0);
wdenkc6097192002-11-03 00:24:07 +0000124
Stefan Roesed07117e2007-02-20 10:27:08 +0100125 /* clear hi slave address */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100126 out_8(&i2c->hsadr, 0);
wdenkc6097192002-11-03 00:24:07 +0000127
Stefan Roesed07117e2007-02-20 10:27:08 +0100128 /* Clock divide Register */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100129 /* set divisor according to freq_opb */
130 divisor = (get_OPB_freq() - 1) / 10000000;
Stefan Roesed07117e2007-02-20 10:27:08 +0100131 if (divisor == 0)
132 divisor = 1;
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100133 out_8(&i2c->clkdiv, divisor);
wdenkc6097192002-11-03 00:24:07 +0000134
Stefan Roesed07117e2007-02-20 10:27:08 +0100135 /* no interrupts */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100136 out_8(&i2c->intrmsk, 0);
wdenkc6097192002-11-03 00:24:07 +0000137
Stefan Roesed07117e2007-02-20 10:27:08 +0100138 /* clear transfer count */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100139 out_8(&i2c->xfrcnt, 0);
wdenkc6097192002-11-03 00:24:07 +0000140
Stefan Roesed07117e2007-02-20 10:27:08 +0100141 /* clear extended control & stat */
142 /* write 1 in SRC SRS SWC SWS to clear these fields */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100143 out_8(&i2c->xtcntlss, 0xF0);
wdenkc6097192002-11-03 00:24:07 +0000144
Stefan Roesed07117e2007-02-20 10:27:08 +0100145 /* Mode Control Register
146 Flush Slave/Master data buffer */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100147 out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
wdenkc6097192002-11-03 00:24:07 +0000148
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100149 val = in_8(&i2c->mdcntl);
wdenkc6097192002-11-03 00:24:07 +0000150
Stefan Roesed07117e2007-02-20 10:27:08 +0100151 /* Ignore General Call, slave transfers are ignored,
152 * disable interrupts, exit unknown bus state, enable hold
153 * SCL 100kHz normaly or FastMode for 400kHz and above
154 */
wdenkc6097192002-11-03 00:24:07 +0000155
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100156 val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
Stefan Roesed07117e2007-02-20 10:27:08 +0100157 if (speed >= 400000)
158 val |= IIC_MDCNTL_FSM;
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100159 out_8(&i2c->mdcntl, val);
wdenkc6097192002-11-03 00:24:07 +0000160
Stefan Roesed07117e2007-02-20 10:27:08 +0100161 /* clear control reg */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100162 out_8(&i2c->cntl, 0x00);
Stefan Roesed07117e2007-02-20 10:27:08 +0100163 }
wdenkc6097192002-11-03 00:24:07 +0000164
Stefan Roesed07117e2007-02-20 10:27:08 +0100165 /* set to SPD bus as default bus upon powerup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166 I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
wdenkc6097192002-11-03 00:24:07 +0000167}
168
169/*
Stefan Roesed07117e2007-02-20 10:27:08 +0100170 * This code tries to use the features of the 405GP i2c
171 * controller. It will transfer up to 4 bytes in one pass
172 * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
173 * is possible to do out16(lhz) transfers.
174 *
175 * cmd_type is 0 for write 1 for read.
176 *
177 * addr_len can take any value from 0-255, it is only limited
178 * by the char, we could make it larger if needed. If it is
179 * 0 we skip the address write cycle.
180 *
181 * Typical case is a Write of an addr followd by a Read. The
182 * IBM FAQ does not cover this. On the last byte of the write
183 * we don't set the creg CHT bit, and on the first bytes of the
184 * read we set the RPST bit.
185 *
186 * It does not support address only transfers, there must be
187 * a data part. If you want to write the address yourself, put
188 * it in the data pointer.
189 *
190 * It does not support transfer to/from address 0.
191 *
192 * It does not check XFRCNT.
193 */
194static int i2c_transfer(unsigned char cmd_type,
195 unsigned char chip,
196 unsigned char addr[],
197 unsigned char addr_len,
198 unsigned char data[],
199 unsigned short data_len)
wdenkc6097192002-11-03 00:24:07 +0000200{
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100201 struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
202 u8 *ptr;
wdenk57b2d802003-06-27 21:31:46 +0000203 int reading;
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100204 int tran, cnt;
wdenk57b2d802003-06-27 21:31:46 +0000205 int result;
206 int status;
207 int i;
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100208 u8 creg;
wdenkc6097192002-11-03 00:24:07 +0000209
Stefan Roesed07117e2007-02-20 10:27:08 +0100210 if (data == 0 || data_len == 0) {
211 /* Don't support data transfer of no length or to address 0 */
wdenk57b2d802003-06-27 21:31:46 +0000212 printf( "i2c_transfer: bad call\n" );
213 return IIC_NOK;
214 }
Stefan Roesed07117e2007-02-20 10:27:08 +0100215 if (addr && addr_len) {
wdenk57b2d802003-06-27 21:31:46 +0000216 ptr = addr;
217 cnt = addr_len;
218 reading = 0;
Stefan Roesed07117e2007-02-20 10:27:08 +0100219 } else {
wdenk57b2d802003-06-27 21:31:46 +0000220 ptr = data;
221 cnt = data_len;
222 reading = cmd_type;
223 }
wdenkc6097192002-11-03 00:24:07 +0000224
Stefan Roesed07117e2007-02-20 10:27:08 +0100225 /* Clear Stop Complete Bit */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100226 out_8(&i2c->sts, IIC_STS_SCMP);
227
wdenk57b2d802003-06-27 21:31:46 +0000228 /* Check init */
Stefan Roesed07117e2007-02-20 10:27:08 +0100229 i = 10;
wdenk57b2d802003-06-27 21:31:46 +0000230 do {
231 /* Get status */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100232 status = in_8(&i2c->sts);
wdenk57b2d802003-06-27 21:31:46 +0000233 i--;
Stefan Roesed07117e2007-02-20 10:27:08 +0100234 } while ((status & IIC_STS_PT) && (i > 0));
wdenkc6097192002-11-03 00:24:07 +0000235
wdenk57b2d802003-06-27 21:31:46 +0000236 if (status & IIC_STS_PT) {
237 result = IIC_NOK_TOUT;
238 return(result);
239 }
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100240
Stefan Roesed07117e2007-02-20 10:27:08 +0100241 /* flush the Master/Slave Databuffers */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100242 out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) |
243 IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB);
244
Stefan Roesed07117e2007-02-20 10:27:08 +0100245 /* need to wait 4 OPB clocks? code below should take that long */
wdenkc6097192002-11-03 00:24:07 +0000246
wdenk57b2d802003-06-27 21:31:46 +0000247 /* 7-bit adressing */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100248 out_8(&i2c->hmadr, 0);
249 out_8(&i2c->lmadr, chip);
wdenkc6097192002-11-03 00:24:07 +0000250
wdenk57b2d802003-06-27 21:31:46 +0000251 tran = 0;
252 result = IIC_OK;
253 creg = 0;
wdenkc6097192002-11-03 00:24:07 +0000254
Stefan Roesed07117e2007-02-20 10:27:08 +0100255 while (tran != cnt && (result == IIC_OK)) {
wdenk57b2d802003-06-27 21:31:46 +0000256 int bc,j;
wdenkc6097192002-11-03 00:24:07 +0000257
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100258 /*
259 * Control register =
260 * Normal transfer, 7-bits adressing, Transfer up to
261 * bc bytes, Normal start, Transfer is a sequence of transfers
Stefan Roesed07117e2007-02-20 10:27:08 +0100262 */
wdenk57b2d802003-06-27 21:31:46 +0000263 creg |= IIC_CNTL_PT;
wdenkc6097192002-11-03 00:24:07 +0000264
Stefan Roesed07117e2007-02-20 10:27:08 +0100265 bc = (cnt - tran) > 4 ? 4 : cnt - tran;
266 creg |= (bc - 1) << 4;
267 /* if the real cmd type is write continue trans */
268 if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
wdenk57b2d802003-06-27 21:31:46 +0000269 creg |= IIC_CNTL_CHT;
wdenkc6097192002-11-03 00:24:07 +0000270
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100271 if (reading) {
wdenk57b2d802003-06-27 21:31:46 +0000272 creg |= IIC_CNTL_READ;
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100273 } else {
274 for(j = 0; j < bc; j++) {
wdenk57b2d802003-06-27 21:31:46 +0000275 /* Set buffer */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100276 out_8(&i2c->mdbuf, ptr[tran + j]);
277 }
278 }
279 out_8(&i2c->cntl, creg);
wdenkc6097192002-11-03 00:24:07 +0000280
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100281 /*
282 * Transfer is in progress
Stefan Roesed07117e2007-02-20 10:27:08 +0100283 * we have to wait for upto 5 bytes of data
284 * 1 byte chip address+r/w bit then bc bytes
285 * of data.
286 * udelay(10) is 1 bit time at 100khz
287 * Doubled for slop. 20 is too small.
288 */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100289 i = 2 * 5 * 8;
wdenk57b2d802003-06-27 21:31:46 +0000290 do {
291 /* Get status */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100292 status = in_8(&i2c->sts);
Stefan Roesed07117e2007-02-20 10:27:08 +0100293 udelay(10);
wdenk57b2d802003-06-27 21:31:46 +0000294 i--;
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100295 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) &&
296 (i > 0));
wdenkc6097192002-11-03 00:24:07 +0000297
wdenk57b2d802003-06-27 21:31:46 +0000298 if (status & IIC_STS_ERR) {
299 result = IIC_NOK;
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100300 status = in_8(&i2c->extsts);
wdenk57b2d802003-06-27 21:31:46 +0000301 /* Lost arbitration? */
302 if (status & IIC_EXTSTS_LA)
303 result = IIC_NOK_LA;
304 /* Incomplete transfer? */
305 if (status & IIC_EXTSTS_ICT)
306 result = IIC_NOK_ICT;
307 /* Transfer aborted? */
308 if (status & IIC_EXTSTS_XFRA)
309 result = IIC_NOK_XFRA;
310 } else if ( status & IIC_STS_PT) {
311 result = IIC_NOK_TOUT;
312 }
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100313
wdenk57b2d802003-06-27 21:31:46 +0000314 /* Command is reading => get buffer */
315 if ((reading) && (result == IIC_OK)) {
316 /* Are there data in buffer */
317 if (status & IIC_STS_MDBS) {
318 /*
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100319 * even if we have data we have to wait 4OPB
320 * clocks for it to hit the front of the FIFO,
321 * after that we can just read. We should check
322 * XFCNT here and if the FIFO is full there is
323 * no need to wait.
Stefan Roesed07117e2007-02-20 10:27:08 +0100324 */
325 udelay(1);
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100326 for (j = 0; j < bc; j++)
327 ptr[tran + j] = in_8(&i2c->mdbuf);
wdenk57b2d802003-06-27 21:31:46 +0000328 } else
329 result = IIC_NOK_DATA;
330 }
331 creg = 0;
Stefan Roesed07117e2007-02-20 10:27:08 +0100332 tran += bc;
333 if (ptr == addr && tran == cnt) {
wdenk57b2d802003-06-27 21:31:46 +0000334 ptr = data;
335 cnt = data_len;
336 tran = 0;
337 reading = cmd_type;
Stefan Roesed07117e2007-02-20 10:27:08 +0100338 if (reading)
wdenk57b2d802003-06-27 21:31:46 +0000339 creg = IIC_CNTL_RPST;
340 }
341 }
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100342 return result;
wdenkc6097192002-11-03 00:24:07 +0000343}
344
Stefan Roesed07117e2007-02-20 10:27:08 +0100345int i2c_probe(uchar chip)
wdenkc6097192002-11-03 00:24:07 +0000346{
347 uchar buf[1];
348
349 buf[0] = 0;
350
wdenk57b2d802003-06-27 21:31:46 +0000351 /*
352 * What is needed is to send the chip address and verify that the
353 * address was <ACK>ed (i.e. there was a chip at that address which
354 * drove the data line low).
355 */
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100356 return (i2c_transfer(1, chip << 1, 0, 0, buf, 1) != 0);
wdenkc6097192002-11-03 00:24:07 +0000357}
358
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100359static int ppc4xx_i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
360 int len, int read)
wdenkc6097192002-11-03 00:24:07 +0000361{
wdenk57b2d802003-06-27 21:31:46 +0000362 uchar xaddr[4];
363 int ret;
wdenkc6097192002-11-03 00:24:07 +0000364
Stefan Roesed07117e2007-02-20 10:27:08 +0100365 if (alen > 4) {
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100366 printf("I2C: addr len %d not supported\n", alen);
wdenkc6097192002-11-03 00:24:07 +0000367 return 1;
368 }
369
Stefan Roesed07117e2007-02-20 10:27:08 +0100370 if (alen > 0) {
wdenk57b2d802003-06-27 21:31:46 +0000371 xaddr[0] = (addr >> 24) & 0xFF;
372 xaddr[1] = (addr >> 16) & 0xFF;
373 xaddr[2] = (addr >> 8) & 0xFF;
374 xaddr[3] = addr & 0xFF;
375 }
wdenkc6097192002-11-03 00:24:07 +0000376
377
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200378#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
wdenkc6097192002-11-03 00:24:07 +0000379 /*
wdenk57b2d802003-06-27 21:31:46 +0000380 * EEPROM chips that implement "address overflow" are ones
381 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
382 * address and the extra bits end up in the "chip address"
383 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
384 * four 256 byte chips.
wdenkc6097192002-11-03 00:24:07 +0000385 *
wdenk57b2d802003-06-27 21:31:46 +0000386 * Note that we consider the length of the address field to
387 * still be one byte because the extra address bits are
388 * hidden in the chip address.
wdenkc6097192002-11-03 00:24:07 +0000389 */
Stefan Roesed07117e2007-02-20 10:27:08 +0100390 if (alen > 0)
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100391 chip |= ((addr >> (alen * 8)) &
392 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
wdenkc6097192002-11-03 00:24:07 +0000393#endif
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100394 if ((ret = i2c_transfer(read, chip << 1, &xaddr[4 - alen], alen,
395 buffer, len)) != 0) {
396 if (gd->have_console) {
397 printf("I2C %s: failed %d\n",
398 read ? "read" : "write", ret);
399 }
400
wdenk57b2d802003-06-27 21:31:46 +0000401 return 1;
402 }
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100403
wdenk57b2d802003-06-27 21:31:46 +0000404 return 0;
wdenkc6097192002-11-03 00:24:07 +0000405}
406
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100407int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
wdenkc6097192002-11-03 00:24:07 +0000408{
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100409 return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 1);
410}
wdenkc6097192002-11-03 00:24:07 +0000411
Stefan Roese77c1f1d2009-11-19 14:03:17 +0100412int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
413{
414 return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 0);
wdenkc6097192002-11-03 00:24:07 +0000415}
416
Stefan Roesed07117e2007-02-20 10:27:08 +0100417#if defined(CONFIG_I2C_MULTI_BUS)
418/*
419 * Functions for multiple I2C bus handling
420 */
421unsigned int i2c_get_bus_num(void)
422{
423 return i2c_bus_num;
424}
425
426int i2c_set_bus_num(unsigned int bus)
427{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200428 if (bus >= CONFIG_SYS_MAX_I2C_BUS)
Stefan Roesed07117e2007-02-20 10:27:08 +0100429 return -1;
430
431 i2c_bus_num = bus;
432
433 return 0;
434}
Matthias Fuchs62f07042007-03-08 16:23:11 +0100435#endif /* CONFIG_I2C_MULTI_BUS */
wdenkc6097192002-11-03 00:24:07 +0000436#endif /* CONFIG_HARD_I2C */