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git01.mediatek.com / filogic / uboot / 2ef216b3db112800303bcde02973e234b5e99a32 / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: b014ec626e290b088b4edd6cac7f031dde444005 [file] [log] [blame]
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
26/* Number of TLB CAM entries we have on FSL Book-E chips */
27#if defined(CONFIG_E500MC)
28#define CONFIG_SYS_NUM_TLBCAMS 64
29#elif defined(CONFIG_E500)
30#define CONFIG_SYS_NUM_TLBCAMS 16
31#endif
32
33#if defined(CONFIG_MPC8536)
34#define CONFIG_MAX_CPUS 1
35#define CONFIG_SYS_FSL_NUM_LAWS 12
36#define CONFIG_SYS_FSL_SEC_COMPAT 2
37
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]38#elif defined(CONFIG_MPC8540)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]39#define CONFIG_MAX_CPUS 1
40#define CONFIG_SYS_FSL_NUM_LAWS 8
41
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]42#elif defined(CONFIG_MPC8541)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]43#define CONFIG_MAX_CPUS 1
44#define CONFIG_SYS_FSL_NUM_LAWS 8
45#define CONFIG_SYS_FSL_SEC_COMPAT 2
46
47#elif defined(CONFIG_MPC8544)
48#define CONFIG_MAX_CPUS 1
49#define CONFIG_SYS_FSL_NUM_LAWS 10
50#define CONFIG_SYS_FSL_SEC_COMPAT 2
51
52#elif defined(CONFIG_MPC8548)
53#define CONFIG_MAX_CPUS 1
54#define CONFIG_SYS_FSL_NUM_LAWS 10
55#define CONFIG_SYS_FSL_SEC_COMPAT 2
56
57#elif defined(CONFIG_MPC8555)
58#define CONFIG_MAX_CPUS 1
59#define CONFIG_SYS_FSL_NUM_LAWS 8
60#define CONFIG_SYS_FSL_SEC_COMPAT 2
61
62#elif defined(CONFIG_MPC8560)
63#define CONFIG_MAX_CPUS 1
64#define CONFIG_SYS_FSL_NUM_LAWS 8
65
66#elif defined(CONFIG_MPC8568)
67#define CONFIG_MAX_CPUS 1
68#define CONFIG_SYS_FSL_NUM_LAWS 10
69#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]70#define QE_MURAM_SIZE 0x10000UL
71#define MAX_QE_RISC 2
72#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]73
74#elif defined(CONFIG_MPC8569)
75#define CONFIG_MAX_CPUS 1
76#define CONFIG_SYS_FSL_NUM_LAWS 10
77#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]78#define QE_MURAM_SIZE 0x20000UL
79#define MAX_QE_RISC 4
80#define QE_NUM_OF_SNUM 46
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]81
82#elif defined(CONFIG_MPC8572)
83#define CONFIG_MAX_CPUS 2
84#define CONFIG_SYS_FSL_NUM_LAWS 12
85#define CONFIG_SYS_FSL_SEC_COMPAT 2
York Sun9aa857b2011-01-25 21:51:27 -0800[diff] [blame]86#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sunc8fc9592011-01-25 22:05:49 -0800[diff] [blame]87#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]88
89#elif defined(CONFIG_P1010)
90#define CONFIG_MAX_CPUS 1
91#define CONFIG_SYS_FSL_NUM_LAWS 12
92#define CONFIG_TSECV2
93#define CONFIG_SYS_FSL_SEC_COMPAT 4
94
95#elif defined(CONFIG_P1011)
96#define CONFIG_MAX_CPUS 1
97#define CONFIG_SYS_FSL_NUM_LAWS 12
98#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]99#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]100#define CONFIG_SYS_FSL_SEC_COMPAT 2
101
102#elif defined(CONFIG_P1012)
103#define CONFIG_MAX_CPUS 1
104#define CONFIG_SYS_FSL_NUM_LAWS 12
105#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]106#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]107#define CONFIG_SYS_FSL_SEC_COMPAT 2
108
109#elif defined(CONFIG_P1013)
110#define CONFIG_MAX_CPUS 1
111#define CONFIG_SYS_FSL_NUM_LAWS 12
112#define CONFIG_TSECV2
113#define CONFIG_SYS_FSL_SEC_COMPAT 2
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]114#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
115#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
116#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]117
118#elif defined(CONFIG_P1014)
119#define CONFIG_MAX_CPUS 1
120#define CONFIG_SYS_FSL_NUM_LAWS 12
121#define CONFIG_TSECV2
122#define CONFIG_SYS_FSL_SEC_COMPAT 4
123
124#elif defined(CONFIG_P1020)
125#define CONFIG_MAX_CPUS 2
126#define CONFIG_SYS_FSL_NUM_LAWS 12
127#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]128#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]129#define CONFIG_SYS_FSL_SEC_COMPAT 2
130
131#elif defined(CONFIG_P1021)
132#define CONFIG_MAX_CPUS 2
133#define CONFIG_SYS_FSL_NUM_LAWS 12
134#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]135#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]136#define CONFIG_SYS_FSL_SEC_COMPAT 2
137
138#elif defined(CONFIG_P1022)
139#define CONFIG_MAX_CPUS 2
140#define CONFIG_SYS_FSL_NUM_LAWS 12
141#define CONFIG_TSECV2
142#define CONFIG_SYS_FSL_SEC_COMPAT 2
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]143#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
144#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
145#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]146
147#elif defined(CONFIG_P2010)
148#define CONFIG_MAX_CPUS 1
149#define CONFIG_SYS_FSL_NUM_LAWS 12
150#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]151#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]152#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]153
154#elif defined(CONFIG_P2020)
155#define CONFIG_MAX_CPUS 2
156#define CONFIG_SYS_FSL_NUM_LAWS 12
157#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]158#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]159#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]160
161#elif defined(CONFIG_PPC_P2040)
162#define CONFIG_MAX_CPUS 4
163#define CONFIG_SYS_FSL_NUM_LAWS 32
164#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]165#define CONFIG_SYS_NUM_FMAN 1
166#define CONFIG_SYS_NUM_FM1_DTSEC 5
167#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]168
169#elif defined(CONFIG_PPC_P3041)
170#define CONFIG_MAX_CPUS 4
171#define CONFIG_SYS_FSL_NUM_LAWS 32
172#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]173#define CONFIG_SYS_NUM_FMAN 1
174#define CONFIG_SYS_NUM_FM1_DTSEC 5
175#define CONFIG_SYS_NUM_FM1_10GEC 1
176#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]177
178#elif defined(CONFIG_PPC_P4040)
179#define CONFIG_MAX_CPUS 4
180#define CONFIG_SYS_FSL_NUM_LAWS 32
181#define CONFIG_SYS_FSL_SEC_COMPAT 4
182
183#elif defined(CONFIG_PPC_P4080)
184#define CONFIG_MAX_CPUS 8
185#define CONFIG_SYS_FSL_NUM_LAWS 32
186#define CONFIG_SYS_FSL_SEC_COMPAT 4
187#define CONFIG_SYS_NUM_FMAN 2
188#define CONFIG_SYS_NUM_FM1_DTSEC 4
189#define CONFIG_SYS_NUM_FM2_DTSEC 4
190#define CONFIG_SYS_NUM_FM1_10GEC 1
191#define CONFIG_SYS_NUM_FM2_10GEC 1
192#define CONFIG_NUM_DDR_CONTROLLERS 2
193#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
194#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun922f40f2011-01-10 12:03:01 +0000[diff] [blame]195#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]196#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
197#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
198#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
199#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
200#define CONFIG_SYS_P4080_ERRATUM_CPU22
201#define CONFIG_SYS_P4080_ERRATUM_SERDES8
202
203#elif defined(CONFIG_PPC_P5010)
204#define CONFIG_MAX_CPUS 1
205#define CONFIG_SYS_FSL_NUM_LAWS 32
206#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]207#define CONFIG_SYS_NUM_FMAN 1
208#define CONFIG_SYS_NUM_FM1_DTSEC 5
209#define CONFIG_SYS_NUM_FM1_10GEC 1
210#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]211
212#elif defined(CONFIG_PPC_P5020)
213#define CONFIG_MAX_CPUS 2
214#define CONFIG_SYS_FSL_NUM_LAWS 32
215#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]216#define CONFIG_SYS_NUM_FMAN 1
217#define CONFIG_SYS_NUM_FM1_DTSEC 5
218#define CONFIG_SYS_NUM_FM1_10GEC 1
219#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]220
221#else
222#error Processor type not defined for this platform
223#endif
224
225#endif /* _ASM_MPC85xx_CONFIG_H_ */