blob: 0981f9b3b1e0eff9aff8a10b690036f08c28d4f1 [file] [log] [blame]
developera37ad462018-11-15 10:07:50 +08001/*
2 * Copyright (C) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8/dts-v1/;
9#include "mt7629.dtsi"
10
11/ {
12 model = "MediaTek MT7629 RFB";
13 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
14
15 aliases {
developer68743392019-07-22 10:35:10 +080016 spi0 = &snfi;
developera37ad462018-11-15 10:07:50 +080017 };
18
19 chosen {
20 stdout-path = &uart0;
developera37ad462018-11-15 10:07:50 +080021 };
22};
23
developere43f3c72018-12-20 16:12:55 +080024&eth {
25 status = "okay";
26 mediatek,gmac-id = <1>;
27 phy-mode = "gmii";
28 phy-handle = <&phy0>;
29
30 phy0: ethernet-phy@0 {
31 reg = <0>;
32 };
33};
34
developera37ad462018-11-15 10:07:50 +080035&pinctrl {
developer68743392019-07-22 10:35:10 +080036 snfi_pins: snfi-pins {
developera37ad462018-11-15 10:07:50 +080037 mux {
38 function = "flash";
developer68743392019-07-22 10:35:10 +080039 groups = "snfi";
40 };
41 };
42
43 snor_pins: snor-pins {
44 mux {
45 function = "flash";
developera37ad462018-11-15 10:07:50 +080046 groups = "spi_nor";
47 };
48 };
49
50 uart0_pins: uart0-default {
51 mux {
52 function = "uart";
53 groups = "uart0_txd_rxd";
54 };
55 };
56
57 watchdog_pins: watchdog-default {
58 mux {
59 function = "watchdog";
60 groups = "watchdog";
61 };
62 };
63};
64
developer68743392019-07-22 10:35:10 +080065&snfi {
66 pinctrl-names = "default", "snfi";
67 pinctrl-0 = <&snor_pins>;
68 pinctrl-1 = <&snfi_pins>;
developera37ad462018-11-15 10:07:50 +080069 status = "okay";
70
71 spi-flash@0{
Neil Armstronga009fa72019-02-10 10:16:20 +000072 compatible = "jedec,spi-nor";
developera37ad462018-11-15 10:07:50 +080073 reg = <0>;
74 u-boot,dm-pre-reloc;
75 };
76};
77
78&uart0 {
79 pinctrl-names = "default";
80 pinctrl-0 = <&uart0_pins>;
81 status = "okay";
82};
83
84&watchdog {
85 pinctrl-names = "default";
86 pinctrl-0 = <&watchdog_pins>;
87 status = "okay";
88};