Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 2dc4caa7cde14e1304d0e91e307a430dc66eb7a9 / . / configs / stm32f769-disco_spl_defconfig
blob: 19d2c24abb50153e2a71e99d71df642b037251a0 [file] [log] [blame]
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]1CONFIG_ARM=y
Trevor Woerner2bcc1ed2020-05-06 08:02:42 -0400[diff] [blame]2CONFIG_ARCH_STM32=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x08008000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]4CONFIG_SYS_MALLOC_LEN=0x100000
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]5CONFIG_SYS_MALLOC_F_LEN=0xE00
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]6CONFIG_SPL_GPIO=y
7CONFIG_SPL_LIBCOMMON_SUPPORT=y
8CONFIG_SPL_LIBGENERIC_SUPPORT=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]9CONFIG_NR_DRAM_BANKS=1
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]10CONFIG_ENV_SIZE=0x2000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]11CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]12CONFIG_SPL_TEXT_BASE=0x8000000
Tom Rinice53ec82022-08-23 15:24:14 -0400[diff] [blame]13CONFIG_SYS_PROMPT="U-Boot > "
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]14CONFIG_SPL_SERIAL=y
15CONFIG_SPL_DRIVERS_MISC=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]16CONFIG_STM32F7=y
17CONFIG_TARGET_STM32F746_DISCO=y
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]18CONFIG_SPL=y
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]19CONFIG_SYS_LOAD_ADDR=0x8008000
Tom Rini2e340532022-05-23 13:56:21 -0400[diff] [blame]20CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]21CONFIG_DISTRO_DEFAULTS=y
Tom Rini4ddbade2022-05-25 12:16:03 -0400[diff] [blame]22CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
23CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]24CONFIG_BOOTDELAY=3
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]25CONFIG_AUTOBOOT_KEYED=y
26CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
27CONFIG_AUTOBOOT_STOP_STR=" "
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]28CONFIG_USE_BOOTARGS=y
29CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]30# CONFIG_DISPLAY_CPUINFO is not set
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]31CONFIG_SPL_PAD_TO=0x8000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]32CONFIG_SPL_NO_BSS_LIMIT=y
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]33CONFIG_SPL_BOARD_INIT=y
34CONFIG_SPL_SYS_MALLOC_SIMPLE=y
35CONFIG_SPL_MTD_SUPPORT=y
36CONFIG_SPL_XIP_SUPPORT=y
Tom Rini2c9d2b52022-05-27 22:06:52 -0400[diff] [blame]37CONFIG_SYS_SPL_ARGS_ADDR=0x81c0000
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]38CONFIG_SPL_DM_RESET=y
Tom Rinicbfa1392022-05-11 17:38:09 -0400[diff] [blame]39CONFIG_SYS_PBSIZE=1050
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]40CONFIG_CMD_GPT=y
41# CONFIG_RANDOM_UUID is not set
42CONFIG_CMD_MMC=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]43# CONFIG_CMD_SETEXPR is not set
44CONFIG_CMD_SNTP=y
45CONFIG_CMD_DNS=y
46CONFIG_CMD_LINK_LOCAL=y
47CONFIG_CMD_BMP=y
48CONFIG_CMD_CACHE=y
49CONFIG_CMD_TIMER=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]50# CONFIG_ISO_PARTITION is not set
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]51CONFIG_OF_CONTROL=y
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]52CONFIG_SPL_OF_CONTROL=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]53CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]54CONFIG_NET_RANDOM_ETHADDR=y
55CONFIG_NETCONSOLE=y
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]56CONFIG_SPL_DM=y
57CONFIG_SPL_DM_SEQ_ALIAS=y
58CONFIG_SPL_OF_TRANSLATE=y
59CONFIG_SPL_CLK=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]60CONFIG_ARM_PL180_MMCI=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]61CONFIG_MTD=y
Miquel Raynala903be42019-10-03 19:50:04 +0200[diff] [blame]62CONFIG_DM_MTD=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]63CONFIG_MTD_NOR_FLASH=y
Patrick Delaunay754ff3b2021-10-04 11:05:52 +0200[diff] [blame]64CONFIG_STM32_FLASH=y
Tom Rinid38112c2022-07-23 13:05:04 -0400[diff] [blame]65CONFIG_SYS_MAX_FLASH_SECT=8
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]66CONFIG_DM_SPI_FLASH=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]67CONFIG_SPI_FLASH_MACRONIX=y
68CONFIG_SPI_FLASH_STMICRO=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]69CONFIG_PHY_SMSC=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]70CONFIG_ETH_DESIGNWARE=y
Tom Rini7ac21a32022-06-15 12:03:43 -0400[diff] [blame]71CONFIG_DW_ALTDESCRIPTOR=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]72CONFIG_MII=y
73# CONFIG_PINCTRL_FULL is not set
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]74CONFIG_SPL_PINCTRL=y
Tom Rini16970382022-09-19 11:22:26 -0400[diff] [blame]75CONFIG_DM_REGULATOR=y
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]76CONFIG_SPL_RAM=y
77CONFIG_SPECIFY_CONSOLE_INDEX=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]78CONFIG_SPI=y
79CONFIG_DM_SPI=y
80CONFIG_STM32_QSPI=y
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]81CONFIG_SPL_TIMER=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]82CONFIG_DM_VIDEO=y
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]83CONFIG_BACKLIGHT_GPIO=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]84CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
85CONFIG_VIDEO_STM32=y
86CONFIG_VIDEO_STM32_DSI=y
87CONFIG_VIDEO_STM32_MAX_XRES=480
88CONFIG_VIDEO_STM32_MAX_YRES=800
Simon Glass2d7a7942020-08-11 11:23:35 -0600[diff] [blame]89CONFIG_SPLASH_SCREEN=y
90CONFIG_SPLASH_SCREEN_ALIGN=y
Patrick Delaunayc47fe772020-09-28 11:30:15 +0200[diff] [blame]91CONFIG_VIDEO_BMP_RLE8=y
Patrick Delaunayb1f17632020-09-28 11:30:16 +0200[diff] [blame]92CONFIG_BMP_16BPP=y
93CONFIG_BMP_24BPP=y
94CONFIG_BMP_32BPP=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]95CONFIG_OF_LIBFDT_OVERLAY=y