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git01.mediatek.com / filogic / uboot / 2cd2ff0384b630955aaee5415a6076e3f615a46b / . / arch / arm / dts / stm32mp15-pinctrl.dtsi
blob: 098153ee99a3a142e5b7c690dde0db7d31ade028 [file] [log] [blame]
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8&pinctrl {
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]9 adc1_ain_pins_a: adc1-ain-0 {
10 pins {
11 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */
12 <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */
13 <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
14 <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
15 <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1_INP13 */
16 <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1_INP15 */
17 };
18 };
19
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]20 adc1_in6_pins_a: adc1-in6-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]21 pins {
22 pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
23 };
24 };
25
26 adc12_ain_pins_a: adc12-ain-0 {
27 pins {
28 pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
29 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
30 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
31 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
32 };
33 };
34
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]35 adc12_ain_pins_b: adc12-ain-1 {
36 pins {
37 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
38 <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */
39 };
40 };
41
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]42 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
43 pins {
44 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
45 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
46 };
47 };
48
49 cec_pins_a: cec-0 {
50 pins {
51 pinmux = <STM32_PINMUX('A', 15, AF4)>;
52 bias-disable;
53 drive-open-drain;
54 slew-rate = <0>;
55 };
56 };
57
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]58 cec_sleep_pins_a: cec-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]59 pins {
60 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
61 };
62 };
63
64 cec_pins_b: cec-1 {
65 pins {
66 pinmux = <STM32_PINMUX('B', 6, AF5)>;
67 bias-disable;
68 drive-open-drain;
69 slew-rate = <0>;
70 };
71 };
72
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]73 cec_sleep_pins_b: cec-sleep-1 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]74 pins {
75 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
76 };
77 };
78
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]79 dac_ch1_pins_a: dac-ch1-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]80 pins {
81 pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
82 };
83 };
84
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]85 dac_ch2_pins_a: dac-ch2-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]86 pins {
87 pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
88 };
89 };
90
91 dcmi_pins_a: dcmi-0 {
92 pins {
93 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
94 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
95 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
96 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
97 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
98 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
99 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
100 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
101 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
102 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
103 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
104 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
105 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
106 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
107 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
108 bias-disable;
109 };
110 };
111
112 dcmi_sleep_pins_a: dcmi-sleep-0 {
113 pins {
114 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
115 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
116 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
117 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
118 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
119 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
120 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
121 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
122 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
123 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
124 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
125 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
126 <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
127 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
128 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
129 };
130 };
131
Patrick Delaunayb22fa9d2021-07-27 12:15:12 +0200[diff] [blame]132 dcmi_pins_b: dcmi-1 {
133 pins {
134 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
135 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
136 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
137 <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
138 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
139 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
140 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
141 <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
142 <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
143 <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
144 <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
145 bias-disable;
146 };
147 };
148
149 dcmi_sleep_pins_b: dcmi-sleep-1 {
150 pins {
151 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
152 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
153 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
154 <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
155 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
156 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
157 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
158 <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
159 <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
160 <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
161 <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
162 };
163 };
164
Patrick Delaunay75785d42022-09-07 13:42:23 +0200[diff] [blame]165 dcmi_pins_c: dcmi-2 {
166 pins {
167 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
168 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
169 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
170 <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
171 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
172 <STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */
173 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
174 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
175 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
176 <STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */
177 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
178 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
179 <STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */
180 bias-pull-up;
181 };
182 };
183
184 dcmi_sleep_pins_c: dcmi-sleep-2 {
185 pins {
186 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
187 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
188 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
189 <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
190 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
191 <STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */
192 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
193 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
194 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
195 <STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */
196 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
197 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
198 <STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */
199 };
200 };
201
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]202 ethernet0_rgmii_pins_a: rgmii-0 {
203 pins1 {
204 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
205 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
206 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
207 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
208 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
209 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
210 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
211 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
212 bias-disable;
213 drive-push-pull;
214 slew-rate = <2>;
215 };
216 pins2 {
217 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
218 bias-disable;
219 drive-push-pull;
220 slew-rate = <0>;
221 };
222 pins3 {
223 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
224 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
225 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
226 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
227 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
228 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
229 bias-disable;
230 };
231 };
232
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]233 ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]234 pins1 {
235 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
236 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
237 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
238 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
239 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
240 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
241 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
242 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
243 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
244 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
245 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
246 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
247 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
248 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
249 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
250 };
251 };
252
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]253 ethernet0_rgmii_pins_b: rgmii-1 {
254 pins1 {
255 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
256 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
257 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
258 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
259 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
260 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
261 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
262 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
263 bias-disable;
264 drive-push-pull;
265 slew-rate = <2>;
266 };
267 pins2 {
268 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
269 bias-disable;
270 drive-push-pull;
271 slew-rate = <0>;
272 };
273 pins3 {
274 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
275 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
276 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
277 <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
278 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
279 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
280 bias-disable;
281 };
282 };
283
284 ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 {
285 pins1 {
286 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
287 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
288 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
289 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
290 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
291 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
292 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
293 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
294 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
295 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
296 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
297 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
298 <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
299 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
300 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
301 };
302 };
303
Patrick Delaunay2b2d0b62020-07-06 13:26:51 +0200[diff] [blame]304 ethernet0_rgmii_pins_c: rgmii-2 {
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]305 pins1 {
306 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
307 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
308 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
309 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
310 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
311 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
312 <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */
313 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
314 bias-disable;
315 drive-push-pull;
316 slew-rate = <2>;
317 };
318 pins2 {
319 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
320 bias-disable;
321 drive-push-pull;
322 slew-rate = <0>;
323 };
324 pins3 {
325 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
326 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
327 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
328 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
329 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
330 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
331 bias-disable;
332 };
333 };
334
Patrick Delaunay2b2d0b62020-07-06 13:26:51 +0200[diff] [blame]335 ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 {
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]336 pins1 {
337 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
338 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
339 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
340 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
341 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
342 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
343 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
344 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
345 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
346 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
347 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
348 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
349 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
350 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
351 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
352 };
353 };
354
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]355 ethernet0_rgmii_pins_d: rgmii-3 {
356 pins1 {
357 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
358 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
359 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
360 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
361 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
362 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
363 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
364 bias-disable;
365 drive-push-pull;
366 slew-rate = <2>;
367 };
368 pins2 {
369 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
370 bias-disable;
371 drive-push-pull;
372 slew-rate = <0>;
373 };
374 pins3 {
375 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
376 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
377 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
378 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
379 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
380 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
381 bias-disable;
382 };
383 };
384
385 ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 {
386 pins1 {
387 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
388 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
389 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
390 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
391 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
392 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
393 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
394 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
395 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
396 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
397 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
398 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
399 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
400 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
401 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
402 };
403 };
404
405 ethernet0_rgmii_pins_e: rgmii-4 {
406 pins1 {
407 pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
408 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
409 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
410 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
411 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
412 <STM32_PINMUX('B', 11, AF11)>; /* ETH_RGMII_TX_CTL */
413 bias-disable;
414 drive-push-pull;
415 slew-rate = <2>;
416 };
417 pins2 {
418 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
419 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
420 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
421 <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
422 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
423 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
424 bias-disable;
425 };
426 };
427
428 ethernet0_rgmii_sleep_pins_e: rgmii-sleep-4 {
429 pins1 {
430 pinmux = <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
431 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
432 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
433 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
434 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
435 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
436 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
437 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
438 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
439 <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
440 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
441 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
442 };
443 };
444
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]445 ethernet0_rmii_pins_a: rmii-0 {
446 pins1 {
447 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
448 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
449 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
450 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
451 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
452 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
453 bias-disable;
454 drive-push-pull;
455 slew-rate = <2>;
456 };
457 pins2 {
458 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
459 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
460 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
461 bias-disable;
462 };
463 };
464
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]465 ethernet0_rmii_sleep_pins_a: rmii-sleep-0 {
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]466 pins1 {
467 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
468 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
469 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
470 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
471 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
472 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
473 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
474 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
475 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
476 };
477 };
478
Patrick Delaunay6f182192022-04-26 15:38:05 +0200[diff] [blame]479 ethernet0_rmii_pins_b: rmii-1 {
480 pins1 {
481 pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */
482 <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
483 <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
484 <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
485 bias-disable;
486 drive-push-pull;
487 slew-rate = <1>;
488 };
489 pins2 {
490 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
491 bias-disable;
492 drive-push-pull;
493 slew-rate = <0>;
494 };
495 pins3 {
496 pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */
497 <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
498 <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */
499 bias-disable;
500 };
501 pins4 {
502 pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */
503 };
504 };
505
506 ethernet0_rmii_sleep_pins_b: rmii-sleep-1 {
507 pins1 {
508 pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
509 <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */
510 <STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */
511 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */
512 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
513 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
514 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
515 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
516 <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */
517 };
518 };
519
Patrick Delaunaye25cbd42022-07-05 16:55:54 +0200[diff] [blame]520 ethernet0_rmii_pins_c: rmii-2 {
521 pins1 {
522 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
523 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
524 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
525 <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
526 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
527 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
528 bias-disable;
529 drive-push-pull;
530 slew-rate = <2>;
531 };
532 pins2 {
533 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
534 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
535 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
536 bias-disable;
537 };
538 };
539
540 ethernet0_rmii_sleep_pins_c: rmii-sleep-2 {
541 pins1 {
542 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
543 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
544 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
545 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
546 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
547 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
548 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
549 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
550 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
551 };
552 };
553
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]554 fmc_pins_a: fmc-0 {
555 pins1 {
556 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
557 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
558 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
559 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
560 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
561 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
562 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
563 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
564 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
565 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
566 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
567 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
568 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
569 bias-disable;
570 drive-push-pull;
571 slew-rate = <1>;
572 };
573 pins2 {
574 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
575 bias-pull-up;
576 };
577 };
578
579 fmc_sleep_pins_a: fmc-sleep-0 {
580 pins {
581 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
582 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
583 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
584 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
585 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
586 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
587 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
588 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
589 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
590 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
591 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
592 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
593 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
594 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
595 };
596 };
597
Patrick Delaunay6d397052021-01-11 12:33:36 +0100[diff] [blame]598 fmc_pins_b: fmc-1 {
599 pins {
600 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
601 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
602 <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
603 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
604 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
605 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
606 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
607 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
608 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
609 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
610 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
611 <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
612 <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
613 <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
614 <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
615 <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
616 <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
617 <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
618 <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
619 <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
620 <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
621 bias-disable;
622 drive-push-pull;
623 slew-rate = <3>;
624 };
625 };
626
627 fmc_sleep_pins_b: fmc-sleep-1 {
628 pins {
629 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
630 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
631 <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
632 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
633 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
634 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
635 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
636 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
637 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
638 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
639 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
640 <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
641 <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
642 <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
643 <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
644 <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
645 <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
646 <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
647 <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
648 <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
649 <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
650 };
651 };
652
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]653 i2c1_pins_a: i2c1-0 {
654 pins {
655 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
656 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
657 bias-disable;
658 drive-open-drain;
659 slew-rate = <0>;
660 };
661 };
662
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]663 i2c1_sleep_pins_a: i2c1-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]664 pins {
665 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
666 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
667 };
668 };
669
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]670 i2c1_pins_b: i2c1-1 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]671 pins {
672 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
673 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
674 bias-disable;
675 drive-open-drain;
676 slew-rate = <0>;
677 };
678 };
679
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]680 i2c1_sleep_pins_b: i2c1-sleep-1 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]681 pins {
682 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
683 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
684 };
685 };
686
687 i2c2_pins_a: i2c2-0 {
688 pins {
689 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
690 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
691 bias-disable;
692 drive-open-drain;
693 slew-rate = <0>;
694 };
695 };
696
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]697 i2c2_sleep_pins_a: i2c2-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]698 pins {
699 pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
700 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
701 };
702 };
703
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]704 i2c2_pins_b1: i2c2-1 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]705 pins {
706 pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
707 bias-disable;
708 drive-open-drain;
709 slew-rate = <0>;
710 };
711 };
712
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]713 i2c2_sleep_pins_b1: i2c2-sleep-1 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]714 pins {
715 pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
716 };
717 };
718
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]719 i2c2_pins_c: i2c2-2 {
Marek Vasutda779092020-05-26 04:30:21 +0200[diff] [blame]720 pins {
721 pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */
722 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
723 bias-disable;
724 drive-open-drain;
725 slew-rate = <0>;
726 };
727 };
728
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]729 i2c2_pins_sleep_c: i2c2-sleep-2 {
Marek Vasutda779092020-05-26 04:30:21 +0200[diff] [blame]730 pins {
731 pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */
732 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
733 };
734 };
735
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]736 i2c5_pins_a: i2c5-0 {
737 pins {
738 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
739 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
740 bias-disable;
741 drive-open-drain;
742 slew-rate = <0>;
743 };
744 };
745
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]746 i2c5_sleep_pins_a: i2c5-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]747 pins {
748 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
749 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
750
751 };
752 };
753
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]754 i2c5_pins_b: i2c5-1 {
755 pins {
756 pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */
757 <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */
758 bias-disable;
759 drive-open-drain;
760 slew-rate = <0>;
761 };
762 };
763
764 i2c5_sleep_pins_b: i2c5-sleep-1 {
765 pins {
766 pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */
767 <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */
768 };
769 };
770
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]771 i2s2_pins_a: i2s2-0 {
772 pins {
773 pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
774 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
775 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
776 slew-rate = <1>;
777 drive-push-pull;
778 bias-disable;
779 };
780 };
781
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]782 i2s2_sleep_pins_a: i2s2-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]783 pins {
784 pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
785 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
786 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
787 };
788 };
789
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]790 ltdc_pins_a: ltdc-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]791 pins {
792 pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
793 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
794 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
795 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
796 <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
797 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
798 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
799 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
800 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
801 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
802 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
803 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
804 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
805 <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
806 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
807 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
808 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
809 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
810 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
811 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
812 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
813 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
814 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
815 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
816 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
817 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
818 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
819 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
820 bias-disable;
821 drive-push-pull;
822 slew-rate = <1>;
823 };
824 };
825
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]826 ltdc_sleep_pins_a: ltdc-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]827 pins {
828 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
829 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
830 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
831 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
832 <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
833 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
834 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
835 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
836 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
837 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
838 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
839 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
840 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
841 <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
842 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
843 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
844 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
845 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
846 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
847 <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
848 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
849 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
850 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
851 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
852 <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
853 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
854 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
855 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
856 };
857 };
858
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]859 ltdc_pins_b: ltdc-1 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]860 pins {
861 pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
862 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
863 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
864 <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
865 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
866 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
867 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
868 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
869 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
870 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
871 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
872 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
873 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
874 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
875 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
876 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
877 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
878 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
879 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
880 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
881 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
882 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
883 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
884 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
885 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
886 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
887 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
888 <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
889 bias-disable;
890 drive-push-pull;
891 slew-rate = <1>;
892 };
893 };
894
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]895 ltdc_sleep_pins_b: ltdc-sleep-1 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]896 pins {
897 pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
898 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
899 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
900 <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
901 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
902 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
903 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
904 <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
905 <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
906 <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
907 <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
908 <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
909 <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
910 <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
911 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
912 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
913 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
914 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
915 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
916 <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
917 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
918 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
919 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
920 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
921 <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
922 <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
923 <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
924 <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
925 };
926 };
927
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]928 ltdc_pins_c: ltdc-2 {
929 pins1 {
930 pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */
931 <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */
932 <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */
933 <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */
934 <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */
935 <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */
936 <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */
937 <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */
938 <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */
939 <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */
940 <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */
941 <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */
942 <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
943 <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */
944 <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */
945 <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */
946 <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
947 <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */
948 <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */
949 <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
950 <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */
951 bias-disable;
952 drive-push-pull;
953 slew-rate = <0>;
954 };
955 pins2 {
956 pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */
957 bias-disable;
958 drive-push-pull;
959 slew-rate = <1>;
960 };
961 };
962
963 ltdc_sleep_pins_c: ltdc-sleep-2 {
964 pins1 {
965 pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */
966 <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */
967 <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */
968 <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */
969 <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */
970 <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */
971 <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */
972 <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */
973 <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */
974 <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */
975 <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */
976 <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */
977 <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */
978 <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */
979 <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */
980 <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */
981 <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */
982 <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */
983 <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */
984 <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */
985 <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */
986 <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */
987 };
988 };
989
990 ltdc_pins_d: ltdc-3 {
991 pins1 {
992 pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */
993 bias-disable;
994 drive-push-pull;
995 slew-rate = <3>;
996 };
997 pins2 {
998 pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
999 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
1000 <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */
1001 <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */
1002 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
1003 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
1004 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
1005 <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */
1006 <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */
1007 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
1008 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
1009 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
1010 <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */
1011 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
1012 <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */
1013 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
1014 <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */
1015 <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */
1016 <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */
1017 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
1018 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
1019 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
1020 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
1021 <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */
1022 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
1023 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
1024 <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */
1025 bias-disable;
1026 drive-push-pull;
1027 slew-rate = <2>;
1028 };
1029 };
1030
1031 ltdc_sleep_pins_d: ltdc-sleep-3 {
1032 pins {
1033 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
1034 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
1035 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
1036 <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */
1037 <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */
1038 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
1039 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
1040 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
1041 <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */
1042 <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */
1043 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
1044 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
1045 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
1046 <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */
1047 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
1048 <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */
1049 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
1050 <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */
1051 <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */
1052 <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */
1053 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
1054 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
1055 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
1056 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
1057 <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */
1058 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
1059 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
1060 <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */
1061 };
1062 };
1063
Patrick Delaunay75785d42022-09-07 13:42:23 +0200[diff] [blame]1064 mco1_pins_a: mco1-0 {
1065 pins {
1066 pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */
1067 bias-disable;
1068 drive-push-pull;
1069 slew-rate = <1>;
1070 };
1071 };
1072
1073 mco1_sleep_pins_a: mco1-sleep-0 {
1074 pins {
1075 pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */
1076 };
1077 };
1078
Patrick Delaunaye25cbd42022-07-05 16:55:54 +0200[diff] [blame]1079 mco2_pins_a: mco2-0 {
1080 pins {
1081 pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
1082 bias-disable;
1083 drive-push-pull;
1084 slew-rate = <2>;
1085 };
1086 };
1087
1088 mco2_sleep_pins_a: mco2-sleep-0 {
1089 pins {
1090 pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
1091 };
1092 };
1093
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1094 m_can1_pins_a: m-can1-0 {
1095 pins1 {
1096 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
1097 slew-rate = <1>;
1098 drive-push-pull;
1099 bias-disable;
1100 };
1101 pins2 {
1102 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
1103 bias-disable;
1104 };
1105 };
1106
1107 m_can1_sleep_pins_a: m_can1-sleep-0 {
1108 pins {
1109 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
1110 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
1111 };
1112 };
1113
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1114 m_can1_pins_b: m-can1-1 {
1115 pins1 {
1116 pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
1117 slew-rate = <1>;
1118 drive-push-pull;
1119 bias-disable;
1120 };
1121 pins2 {
1122 pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
1123 bias-disable;
1124 };
1125 };
1126
1127 m_can1_sleep_pins_b: m_can1-sleep-1 {
1128 pins {
1129 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
1130 <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
1131 };
1132 };
1133
Marek Vasutd76e0032022-06-13 11:55:19 +0200[diff] [blame]1134 m_can1_pins_c: m-can1-2 {
1135 pins1 {
1136 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
1137 slew-rate = <1>;
1138 drive-push-pull;
1139 bias-disable;
1140 };
1141 pins2 {
1142 pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
1143 bias-disable;
1144 };
1145 };
1146
1147 m_can1_sleep_pins_c: m_can1-sleep-2 {
1148 pins {
1149 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
1150 <STM32_PINMUX('H', 14, ANALOG)>; /* CAN1_RX */
1151 };
1152 };
1153
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1154 m_can2_pins_a: m-can2-0 {
1155 pins1 {
1156 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
1157 slew-rate = <1>;
1158 drive-push-pull;
1159 bias-disable;
1160 };
1161 pins2 {
1162 pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
1163 bias-disable;
1164 };
1165 };
1166
1167 m_can2_sleep_pins_a: m_can2-sleep-0 {
1168 pins {
1169 pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */
1170 <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */
1171 };
1172 };
1173
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1174 pwm1_pins_a: pwm1-0 {
1175 pins {
1176 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
1177 <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
1178 <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
1179 bias-pull-down;
1180 drive-push-pull;
1181 slew-rate = <0>;
1182 };
1183 };
1184
1185 pwm1_sleep_pins_a: pwm1-sleep-0 {
1186 pins {
1187 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
1188 <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
1189 <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
1190 };
1191 };
1192
Patrick Delaunay6f182192022-04-26 15:38:05 +0200[diff] [blame]1193 pwm1_pins_b: pwm1-1 {
1194 pins {
1195 pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */
1196 bias-pull-down;
1197 drive-push-pull;
1198 slew-rate = <0>;
1199 };
1200 };
1201
1202 pwm1_sleep_pins_b: pwm1-sleep-1 {
1203 pins {
1204 pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */
1205 };
1206 };
1207
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]1208 pwm1_pins_c: pwm1-2 {
1209 pins {
1210 pinmux = <STM32_PINMUX('E', 11, AF1)>; /* TIM1_CH2 */
1211 drive-push-pull;
1212 slew-rate = <0>;
1213 };
1214 };
1215
1216 pwm1_sleep_pins_c: pwm1-sleep-2 {
1217 pins {
1218 pinmux = <STM32_PINMUX('E', 11, ANALOG)>; /* TIM1_CH2 */
1219 };
1220 };
1221
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1222 pwm2_pins_a: pwm2-0 {
1223 pins {
1224 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
1225 bias-pull-down;
1226 drive-push-pull;
1227 slew-rate = <0>;
1228 };
1229 };
1230
1231 pwm2_sleep_pins_a: pwm2-sleep-0 {
1232 pins {
1233 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
1234 };
1235 };
1236
1237 pwm3_pins_a: pwm3-0 {
1238 pins {
1239 pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
1240 bias-pull-down;
1241 drive-push-pull;
1242 slew-rate = <0>;
1243 };
1244 };
1245
1246 pwm3_sleep_pins_a: pwm3-sleep-0 {
1247 pins {
1248 pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
1249 };
1250 };
1251
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1252 pwm3_pins_b: pwm3-1 {
1253 pins {
1254 pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
1255 bias-disable;
1256 drive-push-pull;
1257 slew-rate = <0>;
1258 };
1259 };
1260
1261 pwm3_sleep_pins_b: pwm3-sleep-1 {
1262 pins {
1263 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */
1264 };
1265 };
1266
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1267 pwm4_pins_a: pwm4-0 {
1268 pins {
1269 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
1270 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
1271 bias-pull-down;
1272 drive-push-pull;
1273 slew-rate = <0>;
1274 };
1275 };
1276
1277 pwm4_sleep_pins_a: pwm4-sleep-0 {
1278 pins {
1279 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
1280 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
1281 };
1282 };
1283
1284 pwm4_pins_b: pwm4-1 {
1285 pins {
1286 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
1287 bias-pull-down;
1288 drive-push-pull;
1289 slew-rate = <0>;
1290 };
1291 };
1292
1293 pwm4_sleep_pins_b: pwm4-sleep-1 {
1294 pins {
1295 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
1296 };
1297 };
1298
1299 pwm5_pins_a: pwm5-0 {
1300 pins {
1301 pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */
1302 bias-pull-down;
1303 drive-push-pull;
1304 slew-rate = <0>;
1305 };
1306 };
1307
1308 pwm5_sleep_pins_a: pwm5-sleep-0 {
1309 pins {
1310 pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */
1311 };
1312 };
1313
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1314 pwm5_pins_b: pwm5-1 {
1315 pins {
1316 pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */
1317 <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */
1318 <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */
1319 bias-disable;
1320 drive-push-pull;
1321 slew-rate = <0>;
1322 };
1323 };
1324
1325 pwm5_sleep_pins_b: pwm5-sleep-1 {
1326 pins {
1327 pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */
1328 <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */
1329 <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */
1330 };
1331 };
1332
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1333 pwm8_pins_a: pwm8-0 {
1334 pins {
1335 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
1336 bias-pull-down;
1337 drive-push-pull;
1338 slew-rate = <0>;
1339 };
1340 };
1341
1342 pwm8_sleep_pins_a: pwm8-sleep-0 {
1343 pins {
1344 pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
1345 };
1346 };
1347
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]1348 pwm8_pins_b: pwm8-1 {
1349 pins {
1350 pinmux = <STM32_PINMUX('I', 5, AF3)>, /* TIM8_CH1 */
1351 <STM32_PINMUX('I', 6, AF3)>, /* TIM8_CH2 */
1352 <STM32_PINMUX('I', 7, AF3)>, /* TIM8_CH3 */
1353 <STM32_PINMUX('C', 9, AF3)>; /* TIM8_CH4 */
1354 drive-push-pull;
1355 slew-rate = <0>;
1356 };
1357 };
1358
1359 pwm8_sleep_pins_b: pwm8-sleep-1 {
1360 pins {
1361 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* TIM8_CH1 */
1362 <STM32_PINMUX('I', 6, ANALOG)>, /* TIM8_CH2 */
1363 <STM32_PINMUX('I', 7, ANALOG)>, /* TIM8_CH3 */
1364 <STM32_PINMUX('C', 9, ANALOG)>; /* TIM8_CH4 */
1365 };
1366 };
1367
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1368 pwm12_pins_a: pwm12-0 {
1369 pins {
1370 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
1371 bias-pull-down;
1372 drive-push-pull;
1373 slew-rate = <0>;
1374 };
1375 };
1376
1377 pwm12_sleep_pins_a: pwm12-sleep-0 {
1378 pins {
1379 pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */
1380 };
1381 };
1382
1383 qspi_clk_pins_a: qspi-clk-0 {
1384 pins {
1385 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
1386 bias-disable;
1387 drive-push-pull;
1388 slew-rate = <3>;
1389 };
1390 };
1391
1392 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
1393 pins {
1394 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
1395 };
1396 };
1397
1398 qspi_bk1_pins_a: qspi-bk1-0 {
Patrick Delaunay7f2cba42023-04-24 16:21:10 +0200[diff] [blame]1399 pins {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1400 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
1401 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
1402 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
1403 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
1404 bias-disable;
1405 drive-push-pull;
1406 slew-rate = <1>;
1407 };
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1408 };
1409
1410 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
1411 pins {
1412 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
1413 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
1414 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
Patrick Delaunay7f2cba42023-04-24 16:21:10 +0200[diff] [blame]1415 <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1416 };
1417 };
1418
1419 qspi_bk2_pins_a: qspi-bk2-0 {
Patrick Delaunay7f2cba42023-04-24 16:21:10 +0200[diff] [blame]1420 pins {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1421 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
1422 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
1423 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
1424 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
1425 bias-disable;
1426 drive-push-pull;
1427 slew-rate = <1>;
1428 };
Patrick Delaunay7f2cba42023-04-24 16:21:10 +0200[diff] [blame]1429 };
1430
1431 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
1432 pins {
1433 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
1434 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
1435 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
1436 <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */
1437 };
1438 };
1439
1440 qspi_cs1_pins_a: qspi-cs1-0 {
1441 pins {
1442 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
1443 bias-pull-up;
1444 drive-push-pull;
1445 slew-rate = <1>;
1446 };
1447 };
1448
1449 qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
1450 pins {
1451 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
1452 };
1453 };
1454
1455 qspi_cs2_pins_a: qspi-cs2-0 {
1456 pins {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1457 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
1458 bias-pull-up;
1459 drive-push-pull;
1460 slew-rate = <1>;
1461 };
1462 };
1463
Patrick Delaunay7f2cba42023-04-24 16:21:10 +0200[diff] [blame]1464 qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1465 pins {
Patrick Delaunay7f2cba42023-04-24 16:21:10 +0200[diff] [blame]1466 pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1467 };
1468 };
1469
1470 sai2a_pins_a: sai2a-0 {
1471 pins {
1472 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
1473 <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
1474 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
1475 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
1476 slew-rate = <0>;
1477 drive-push-pull;
1478 bias-disable;
1479 };
1480 };
1481
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1482 sai2a_sleep_pins_a: sai2a-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1483 pins {
1484 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
1485 <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
1486 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
1487 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
1488 };
1489 };
1490
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1491 sai2a_pins_b: sai2a-1 {
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]1492 pins1 {
1493 pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
1494 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
1495 <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */
1496 slew-rate = <0>;
1497 drive-push-pull;
1498 bias-disable;
1499 };
1500 };
1501
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1502 sai2a_sleep_pins_b: sai2a-sleep-1 {
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]1503 pins {
1504 pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
1505 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
1506 <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */
1507 };
1508 };
1509
Patrick Delaunay37868aa2021-12-17 16:30:22 +0100[diff] [blame]1510 sai2a_pins_c: sai2a-2 {
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1511 pins {
1512 pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */
1513 <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */
1514 <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */
1515 slew-rate = <0>;
1516 drive-push-pull;
1517 bias-disable;
1518 };
1519 };
1520
Patrick Delaunay37868aa2021-12-17 16:30:22 +0100[diff] [blame]1521 sai2a_sleep_pins_c: sai2a-sleep-2 {
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1522 pins {
1523 pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */
1524 <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */
1525 <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */
1526 };
1527 };
1528
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1529 sai2b_pins_a: sai2b-0 {
1530 pins1 {
1531 pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
1532 <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
1533 <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
1534 slew-rate = <0>;
1535 drive-push-pull;
1536 bias-disable;
1537 };
1538 pins2 {
1539 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1540 bias-disable;
1541 };
1542 };
1543
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1544 sai2b_sleep_pins_a: sai2b-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1545 pins {
1546 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
1547 <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
1548 <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
1549 <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
1550 };
1551 };
1552
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1553 sai2b_pins_b: sai2b-1 {
1554 pins {
1555 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1556 bias-disable;
1557 };
1558 };
1559
1560 sai2b_sleep_pins_b: sai2b-sleep-1 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1561 pins {
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1562 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
1563 };
1564 };
1565
Patrick Delaunay37868aa2021-12-17 16:30:22 +0100[diff] [blame]1566 sai2b_pins_c: sai2b-2 {
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1567 pins1 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1568 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1569 bias-disable;
1570 };
1571 };
1572
Patrick Delaunay37868aa2021-12-17 16:30:22 +0100[diff] [blame]1573 sai2b_sleep_pins_c: sai2b-sleep-2 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1574 pins {
1575 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
1576 };
1577 };
1578
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]1579 sai2b_pins_d: sai2b-3 {
1580 pins1 {
1581 pinmux = <STM32_PINMUX('H', 2, AF10)>, /* SAI2_SCK_B */
1582 <STM32_PINMUX('C', 0, AF8)>, /* SAI2_FS_B */
1583 <STM32_PINMUX('H', 3, AF10)>; /* SAI2_MCLK_B */
1584 slew-rate = <0>;
1585 drive-push-pull;
1586 bias-disable;
1587 };
1588 pins2 {
1589 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1590 bias-disable;
1591 };
1592 };
1593
1594 sai2b_sleep_pins_d: sai2b-sleep-3 {
1595 pins1 {
1596 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* SAI2_SCK_B */
1597 <STM32_PINMUX('C', 0, ANALOG)>, /* SAI2_FS_B */
1598 <STM32_PINMUX('H', 3, ANALOG)>, /* SAI2_MCLK_B */
1599 <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
1600 };
1601 };
1602
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1603 sai4a_pins_a: sai4a-0 {
1604 pins {
1605 pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
1606 slew-rate = <0>;
1607 drive-push-pull;
1608 bias-disable;
1609 };
1610 };
1611
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1612 sai4a_sleep_pins_a: sai4a-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1613 pins {
1614 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
1615 };
1616 };
1617
1618 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
1619 pins1 {
1620 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
1621 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1622 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
1623 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
1624 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1625 slew-rate = <1>;
1626 drive-push-pull;
1627 bias-disable;
1628 };
1629 pins2 {
1630 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
1631 slew-rate = <2>;
1632 drive-push-pull;
1633 bias-disable;
1634 };
1635 };
1636
1637 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
1638 pins1 {
1639 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
1640 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1641 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
1642 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
1643 slew-rate = <1>;
1644 drive-push-pull;
1645 bias-disable;
1646 };
1647 pins2 {
1648 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
1649 slew-rate = <2>;
1650 drive-push-pull;
1651 bias-disable;
1652 };
1653 pins3 {
1654 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1655 slew-rate = <1>;
1656 drive-open-drain;
1657 bias-disable;
1658 };
1659 };
1660
Patrick Delaunaye48a0d42021-06-29 12:01:07 +0200[diff] [blame]1661 sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
1662 pins1 {
1663 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
1664 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1665 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
1666 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
1667 slew-rate = <1>;
1668 drive-push-pull;
1669 bias-disable;
1670 };
1671 };
1672
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1673 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
1674 pins {
1675 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
1676 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
1677 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
1678 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
1679 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
1680 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
1681 };
1682 };
1683
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]1684 sdmmc1_b4_pins_b: sdmmc1-b4-1 {
1685 pins1 {
1686 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
1687 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1688 <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
1689 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
1690 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1691 slew-rate = <1>;
1692 drive-push-pull;
1693 bias-disable;
1694 };
1695 pins2 {
1696 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
1697 slew-rate = <2>;
1698 drive-push-pull;
1699 bias-disable;
1700 };
1701 };
1702
1703 sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 {
1704 pins1 {
1705 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
1706 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1707 <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
1708 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
1709 slew-rate = <1>;
1710 drive-push-pull;
1711 bias-disable;
1712 };
1713 pins2 {
1714 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
1715 slew-rate = <2>;
1716 drive-push-pull;
1717 bias-disable;
1718 };
1719 pins3 {
1720 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1721 slew-rate = <1>;
1722 drive-open-drain;
1723 bias-disable;
1724 };
1725 };
1726
1727 sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 {
1728 pins {
1729 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
1730 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
1731 <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC1_D2 */
1732 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
1733 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
1734 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
1735 };
1736 };
1737
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1738 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
1739 pins1 {
1740 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
1741 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
1742 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1743 slew-rate = <1>;
1744 drive-push-pull;
1745 bias-pull-up;
1746 };
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]1747 pins2 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1748 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
1749 bias-pull-up;
1750 };
1751 };
1752
Patrick Delaunaye48a0d42021-06-29 12:01:07 +0200[diff] [blame]1753 sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 {
1754 pins1 {
1755 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
1756 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
1757 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1758 slew-rate = <1>;
1759 drive-push-pull;
1760 bias-pull-up;
1761 };
1762 };
1763
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1764 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
1765 pins {
1766 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
1767 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
1768 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
1769 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
1770 };
1771 };
1772
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]1773 sdmmc1_dir_pins_b: sdmmc1-dir-1 {
1774 pins1 {
1775 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1776 <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]1777 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1778 slew-rate = <1>;
1779 drive-push-pull;
1780 bias-pull-up;
1781 };
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]1782 pins2 {
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]1783 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
1784 bias-pull-up;
1785 };
1786 };
1787
1788 sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
1789 pins {
1790 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1791 <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */
1792 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
1793 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]1794 };
1795 };
1796
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1797 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
1798 pins1 {
1799 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
1800 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
1801 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
1802 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
1803 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
1804 slew-rate = <1>;
1805 drive-push-pull;
1806 bias-pull-up;
1807 };
1808 pins2 {
1809 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
1810 slew-rate = <2>;
1811 drive-push-pull;
1812 bias-pull-up;
1813 };
1814 };
1815
1816 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
1817 pins1 {
1818 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
1819 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
1820 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
1821 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
1822 slew-rate = <1>;
1823 drive-push-pull;
1824 bias-pull-up;
1825 };
1826 pins2 {
1827 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
1828 slew-rate = <2>;
1829 drive-push-pull;
1830 bias-pull-up;
1831 };
1832 pins3 {
1833 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
1834 slew-rate = <1>;
1835 drive-open-drain;
1836 bias-pull-up;
1837 };
1838 };
1839
1840 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
1841 pins {
1842 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
1843 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
1844 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
1845 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
1846 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
1847 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
1848 };
1849 };
1850
1851 sdmmc2_b4_pins_b: sdmmc2-b4-1 {
1852 pins1 {
1853 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
1854 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
1855 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
1856 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
1857 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
1858 slew-rate = <1>;
1859 drive-push-pull;
1860 bias-disable;
1861 };
1862 pins2 {
1863 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
1864 slew-rate = <2>;
1865 drive-push-pull;
1866 bias-disable;
1867 };
1868 };
1869
1870 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
1871 pins1 {
1872 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
1873 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
1874 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
1875 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
1876 slew-rate = <1>;
1877 drive-push-pull;
1878 bias-disable;
1879 };
1880 pins2 {
1881 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
1882 slew-rate = <2>;
1883 drive-push-pull;
1884 bias-disable;
1885 };
1886 pins3 {
1887 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
1888 slew-rate = <1>;
1889 drive-open-drain;
1890 bias-disable;
1891 };
1892 };
1893
1894 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
1895 pins {
1896 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1897 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1898 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
1899 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
1900 slew-rate = <1>;
1901 drive-push-pull;
1902 bias-pull-up;
1903 };
1904 };
1905
1906 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
1907 pins {
1908 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1909 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1910 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
1911 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
1912 };
1913 };
1914
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]1915 sdmmc2_d47_pins_b: sdmmc2-d47-1 {
1916 pins {
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1917 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1918 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1919 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
1920 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
1921 slew-rate = <1>;
1922 drive-push-pull;
1923 bias-disable;
1924 };
1925 };
1926
1927 sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
1928 pins {
1929 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1930 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1931 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
1932 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
1933 };
1934 };
1935
1936 sdmmc2_d47_pins_c: sdmmc2-d47-2 {
1937 pins {
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]1938 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1939 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
1940 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
1941 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
1942 slew-rate = <1>;
1943 drive-push-pull;
1944 bias-pull-up;
1945 };
1946 };
1947
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]1948 sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 {
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]1949 pins {
1950 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1951 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
1952 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
1953 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
1954 };
1955 };
1956
Patrick Delaunay6d397052021-01-11 12:33:36 +0100[diff] [blame]1957 sdmmc2_d47_pins_d: sdmmc2-d47-3 {
1958 pins {
1959 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1960 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1961 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
1962 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
1963 };
1964 };
1965
1966 sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {
1967 pins {
1968 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1969 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1970 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
1971 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
1972 };
1973 };
1974
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]1975 sdmmc2_d47_pins_e: sdmmc2-d47-4 {
1976 pins {
1977 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1978 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1979 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
1980 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
1981 slew-rate = <1>;
1982 drive-push-pull;
1983 bias-pull-up;
1984 };
1985 };
1986
1987 sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 {
1988 pins {
1989 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1990 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1991 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
1992 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
1993 };
1994 };
1995
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1996 sdmmc3_b4_pins_a: sdmmc3-b4-0 {
1997 pins1 {
1998 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1999 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
2000 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
2001 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
2002 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
2003 slew-rate = <1>;
2004 drive-push-pull;
2005 bias-pull-up;
2006 };
2007 pins2 {
2008 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
2009 slew-rate = <2>;
2010 drive-push-pull;
2011 bias-pull-up;
2012 };
2013 };
2014
2015 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
2016 pins1 {
2017 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
2018 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
2019 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
2020 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
2021 slew-rate = <1>;
2022 drive-push-pull;
2023 bias-pull-up;
2024 };
2025 pins2 {
2026 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
2027 slew-rate = <2>;
2028 drive-push-pull;
2029 bias-pull-up;
2030 };
2031 pins3 {
2032 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
2033 slew-rate = <1>;
2034 drive-open-drain;
2035 bias-pull-up;
2036 };
2037 };
2038
2039 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
2040 pins {
2041 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
2042 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
2043 <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
2044 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
2045 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
2046 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
2047 };
2048 };
2049
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]2050 sdmmc3_b4_pins_b: sdmmc3-b4-1 {
2051 pins1 {
2052 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
2053 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
2054 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
2055 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
2056 <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
2057 slew-rate = <1>;
2058 drive-push-pull;
2059 bias-pull-up;
2060 };
2061 pins2 {
2062 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
2063 slew-rate = <2>;
2064 drive-push-pull;
2065 bias-pull-up;
2066 };
2067 };
2068
2069 sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 {
2070 pins1 {
2071 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
2072 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
2073 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
2074 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
2075 slew-rate = <1>;
2076 drive-push-pull;
2077 bias-pull-up;
2078 };
2079 pins2 {
2080 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
2081 slew-rate = <2>;
2082 drive-push-pull;
2083 bias-pull-up;
2084 };
2085 pins3 {
2086 pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */
2087 slew-rate = <1>;
2088 drive-open-drain;
2089 bias-pull-up;
2090 };
2091 };
2092
2093 sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 {
2094 pins {
2095 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
2096 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
2097 <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
2098 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
2099 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
2100 <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
2101 };
2102 };
2103
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2104 spdifrx_pins_a: spdifrx-0 {
2105 pins {
2106 pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
2107 bias-disable;
2108 };
2109 };
2110
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]2111 spdifrx_sleep_pins_a: spdifrx-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2112 pins {
2113 pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
2114 };
2115 };
2116
Patrick Delaunay4597d262023-07-10 10:38:45 +0200[diff] [blame]2117 spi1_pins_b: spi1-1 {
2118 pins1 {
2119 pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
2120 <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
2121 bias-disable;
2122 drive-push-pull;
2123 slew-rate = <1>;
2124 };
2125
2126 pins2 {
2127 pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
2128 bias-disable;
2129 };
2130 };
2131
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2132 spi2_pins_a: spi2-0 {
2133 pins1 {
Patrick Delaunay75785d42022-09-07 13:42:23 +0200[diff] [blame]2134 pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
2135 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2136 bias-disable;
2137 drive-push-pull;
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]2138 slew-rate = <1>;
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2139 };
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]2140
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2141 pins2 {
Patrick Delaunay75785d42022-09-07 13:42:23 +0200[diff] [blame]2142 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2143 bias-disable;
2144 };
2145 };
2146
Marek Vasut75f5e9c2022-06-13 11:55:20 +0200[diff] [blame]2147 spi2_pins_b: spi2-1 {
2148 pins1 {
Patrick Delaunay75785d42022-09-07 13:42:23 +0200[diff] [blame]2149 pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
2150 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
Marek Vasut75f5e9c2022-06-13 11:55:20 +0200[diff] [blame]2151 bias-disable;
2152 drive-push-pull;
2153 slew-rate = <1>;
2154 };
2155
2156 pins2 {
Patrick Delaunay75785d42022-09-07 13:42:23 +0200[diff] [blame]2157 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
Marek Vasut75f5e9c2022-06-13 11:55:20 +0200[diff] [blame]2158 bias-disable;
2159 };
2160 };
2161
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]2162 spi2_pins_c: spi2-2 {
2163 pins1 {
2164 pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
2165 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
2166 bias-disable;
2167 drive-push-pull;
2168 };
2169
2170 pins2 {
2171 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
2172 bias-pull-down;
2173 };
2174 };
2175
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2176 spi4_pins_a: spi4-0 {
2177 pins {
2178 pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
2179 <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
2180 bias-disable;
2181 drive-push-pull;
2182 slew-rate = <1>;
2183 };
2184 pins2 {
2185 pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
2186 bias-disable;
2187 };
2188 };
2189
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]2190 spi5_pins_a: spi5-0 {
2191 pins1 {
2192 pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */
2193 <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
2194 bias-disable;
2195 drive-push-pull;
2196 slew-rate = <1>;
2197 };
2198
2199 pins2 {
2200 pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */
2201 bias-disable;
2202 };
2203 };
2204
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2205 stusb1600_pins_a: stusb1600-0 {
Patrick Delaunay6d397052021-01-11 12:33:36 +0100[diff] [blame]2206 pins {
Patrick Delaunayb3f8d832022-01-31 16:07:54 +0100[diff] [blame]2207 pinmux = <STM32_PINMUX('I', 11, GPIO)>;
Patrick Delaunay6d397052021-01-11 12:33:36 +0100[diff] [blame]2208 bias-pull-up;
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2209 };
2210 };
2211
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2212 uart4_pins_a: uart4-0 {
2213 pins1 {
2214 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
2215 bias-disable;
2216 drive-push-pull;
2217 slew-rate = <0>;
2218 };
2219 pins2 {
2220 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
2221 bias-disable;
2222 };
2223 };
2224
2225 uart4_idle_pins_a: uart4-idle-0 {
Patrick Delaunayb3f8d832022-01-31 16:07:54 +0100[diff] [blame]2226 pins1 {
2227 pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
2228 };
2229 pins2 {
2230 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
2231 bias-disable;
2232 };
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2233 };
2234
2235 uart4_sleep_pins_a: uart4-sleep-0 {
Patrick Delaunayb3f8d832022-01-31 16:07:54 +0100[diff] [blame]2236 pins {
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2237 pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
2238 <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
Patrick Delaunayb3f8d832022-01-31 16:07:54 +0100[diff] [blame]2239 };
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2240 };
2241
2242 uart4_pins_b: uart4-1 {
2243 pins1 {
2244 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
2245 bias-disable;
2246 drive-push-pull;
2247 slew-rate = <0>;
2248 };
2249 pins2 {
2250 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
2251 bias-disable;
2252 };
2253 };
2254
2255 uart4_pins_c: uart4-2 {
2256 pins1 {
2257 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
2258 bias-disable;
2259 drive-push-pull;
2260 slew-rate = <0>;
2261 };
2262 pins2 {
2263 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
2264 bias-disable;
2265 };
2266 };
2267
Marek Vasut8c35f982022-06-13 11:55:17 +0200[diff] [blame]2268 uart4_pins_d: uart4-3 {
2269 pins1 {
2270 pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */
2271 bias-disable;
2272 drive-push-pull;
2273 slew-rate = <0>;
2274 };
2275 pins2 {
2276 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
2277 bias-disable;
2278 };
2279 };
2280
2281 uart4_idle_pins_d: uart4-idle-3 {
2282 pins1 {
2283 pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */
2284 };
2285 pins2 {
2286 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
2287 bias-disable;
2288 };
2289 };
2290
2291 uart4_sleep_pins_d: uart4-sleep-3 {
2292 pins {
2293 pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */
2294 <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
2295 };
2296 };
2297
Marek Vasut17e5e562022-06-13 11:55:18 +0200[diff] [blame]2298 uart5_pins_a: uart5-0 {
2299 pins1 {
2300 pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */
2301 bias-disable;
2302 drive-push-pull;
2303 slew-rate = <0>;
2304 };
2305 pins2 {
2306 pinmux = <STM32_PINMUX('B', 5, AF12)>; /* UART5_RX */
2307 bias-disable;
2308 };
2309 };
2310
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2311 uart7_pins_a: uart7-0 {
2312 pins1 {
2313 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
2314 bias-disable;
2315 drive-push-pull;
2316 slew-rate = <0>;
2317 };
2318 pins2 {
2319 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */
2320 <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */
2321 <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
2322 bias-disable;
2323 };
2324 };
2325
2326 uart7_pins_b: uart7-1 {
2327 pins1 {
2328 pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
2329 bias-disable;
2330 drive-push-pull;
2331 slew-rate = <0>;
2332 };
2333 pins2 {
2334 pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
2335 bias-disable;
2336 };
2337 };
2338
2339 uart7_pins_c: uart7-2 {
2340 pins1 {
2341 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
2342 bias-disable;
2343 drive-push-pull;
2344 slew-rate = <0>;
2345 };
2346 pins2 {
2347 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
Patrick Delaunayb3f8d832022-01-31 16:07:54 +0100[diff] [blame]2348 bias-pull-up;
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2349 };
2350 };
2351
2352 uart7_idle_pins_c: uart7-idle-2 {
2353 pins1 {
2354 pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */
2355 };
2356 pins2 {
2357 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
Patrick Delaunayb3f8d832022-01-31 16:07:54 +0100[diff] [blame]2358 bias-pull-up;
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2359 };
2360 };
2361
2362 uart7_sleep_pins_c: uart7-sleep-2 {
2363 pins {
2364 pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */
2365 <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */
2366 };
2367 };
2368
2369 uart8_pins_a: uart8-0 {
2370 pins1 {
2371 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
2372 bias-disable;
2373 drive-push-pull;
2374 slew-rate = <0>;
2375 };
2376 pins2 {
2377 pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
2378 bias-disable;
2379 };
2380 };
2381
Patrick Delaunay6d397052021-01-11 12:33:36 +0100[diff] [blame]2382 uart8_rtscts_pins_a: uart8rtscts-0 {
2383 pins {
2384 pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */
2385 <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */
2386 bias-disable;
2387 };
2388 };
2389
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]2390 usart1_pins_a: usart1-0 {
2391 pins1 {
2392 pinmux = <STM32_PINMUX('A', 12, AF7)>; /* USART1_RTS */
2393 bias-disable;
2394 drive-push-pull;
2395 slew-rate = <0>;
2396 };
2397 pins2 {
2398 pinmux = <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
2399 bias-disable;
2400 };
2401 };
2402
2403 usart1_idle_pins_a: usart1-idle-0 {
2404 pins1 {
2405 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
2406 <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
2407 };
2408 };
2409
2410 usart1_sleep_pins_a: usart1-sleep-0 {
2411 pins {
2412 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
2413 <STM32_PINMUX('A', 11, ANALOG)>; /* USART1_CTS_NSS */
2414 };
2415 };
2416
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]2417 usart2_pins_a: usart2-0 {
2418 pins1 {
2419 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
2420 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
2421 bias-disable;
2422 drive-push-pull;
2423 slew-rate = <0>;
2424 };
2425 pins2 {
2426 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
2427 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
2428 bias-disable;
2429 };
2430 };
2431
2432 usart2_sleep_pins_a: usart2-sleep-0 {
2433 pins {
2434 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
2435 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
2436 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
2437 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
2438 };
2439 };
2440
2441 usart2_pins_b: usart2-1 {
2442 pins1 {
2443 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
2444 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
2445 bias-disable;
2446 drive-push-pull;
2447 slew-rate = <0>;
2448 };
2449 pins2 {
2450 pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */
2451 <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */
2452 bias-disable;
2453 };
2454 };
2455
2456 usart2_sleep_pins_b: usart2-sleep-1 {
2457 pins {
2458 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
2459 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
2460 <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */
2461 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
2462 };
2463 };
2464
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2465 usart2_pins_c: usart2-2 {
2466 pins1 {
2467 pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
2468 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
2469 bias-disable;
2470 drive-push-pull;
Patrick Delaunay4597d262023-07-10 10:38:45 +0200[diff] [blame]2471 slew-rate = <0>;
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2472 };
2473 pins2 {
2474 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
2475 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
2476 bias-disable;
2477 };
2478 };
2479
2480 usart2_idle_pins_c: usart2-idle-2 {
2481 pins1 {
2482 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2483 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
2484 };
2485 pins2 {
Patrick Delaunaye48a0d42021-06-29 12:01:07 +0200[diff] [blame]2486 pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
2487 bias-disable;
2488 drive-push-pull;
Patrick Delaunay4597d262023-07-10 10:38:45 +0200[diff] [blame]2489 slew-rate = <0>;
Patrick Delaunaye48a0d42021-06-29 12:01:07 +0200[diff] [blame]2490 };
2491 pins3 {
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2492 pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
2493 bias-disable;
2494 };
2495 };
2496
2497 usart2_sleep_pins_c: usart2-sleep-2 {
2498 pins {
2499 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
2500 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
2501 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
2502 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
2503 };
2504 };
2505
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]2506 usart3_pins_a: usart3-0 {
2507 pins1 {
2508 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
2509 bias-disable;
2510 drive-push-pull;
2511 slew-rate = <0>;
2512 };
2513 pins2 {
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2514 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
2515 bias-disable;
2516 };
2517 };
2518
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]2519 usart3_idle_pins_a: usart3-idle-0 {
2520 pins1 {
2521 pinmux = <STM32_PINMUX('B', 10, ANALOG)>; /* USART3_TX */
2522 };
2523 pins2 {
2524 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
2525 bias-disable;
2526 };
2527 };
2528
2529 usart3_sleep_pins_a: usart3-sleep-0 {
2530 pins {
2531 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
2532 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
2533 };
2534 };
2535
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2536 usart3_pins_b: usart3-1 {
2537 pins1 {
2538 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
2539 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
2540 bias-disable;
2541 drive-push-pull;
2542 slew-rate = <0>;
2543 };
2544 pins2 {
2545 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
2546 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
Patrick Delaunayb3f8d832022-01-31 16:07:54 +0100[diff] [blame]2547 bias-pull-up;
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2548 };
2549 };
2550
2551 usart3_idle_pins_b: usart3-idle-1 {
2552 pins1 {
2553 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2554 <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
2555 };
2556 pins2 {
Patrick Delaunaye48a0d42021-06-29 12:01:07 +0200[diff] [blame]2557 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
2558 bias-disable;
2559 drive-push-pull;
2560 slew-rate = <0>;
2561 };
2562 pins3 {
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2563 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
Patrick Delaunayb3f8d832022-01-31 16:07:54 +0100[diff] [blame]2564 bias-pull-up;
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2565 };
2566 };
2567
2568 usart3_sleep_pins_b: usart3-sleep-1 {
2569 pins {
2570 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
2571 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
2572 <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */
2573 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
2574 };
2575 };
2576
2577 usart3_pins_c: usart3-2 {
2578 pins1 {
2579 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
2580 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
2581 bias-disable;
2582 drive-push-pull;
2583 slew-rate = <0>;
2584 };
2585 pins2 {
2586 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
2587 <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
Patrick Delaunayb3f8d832022-01-31 16:07:54 +0100[diff] [blame]2588 bias-pull-up;
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2589 };
2590 };
2591
2592 usart3_idle_pins_c: usart3-idle-2 {
2593 pins1 {
2594 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2595 <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
2596 };
2597 pins2 {
Patrick Delaunaye48a0d42021-06-29 12:01:07 +0200[diff] [blame]2598 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
2599 bias-disable;
2600 drive-push-pull;
2601 slew-rate = <0>;
2602 };
2603 pins3 {
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]2604 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
Patrick Delaunayb3f8d832022-01-31 16:07:54 +0100[diff] [blame]2605 bias-pull-up;
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]2606 };
2607 };
2608
Patrick Delaunay551efca2020-09-16 10:01:32 +0200[diff] [blame]2609 usart3_sleep_pins_c: usart3-sleep-2 {
2610 pins {
2611 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
2612 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
2613 <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */
2614 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
2615 };
2616 };
2617
Patrick Delaunay6f182192022-04-26 15:38:05 +0200[diff] [blame]2618 usart3_pins_d: usart3-3 {
2619 pins1 {
2620 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
2621 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
2622 bias-disable;
2623 drive-push-pull;
2624 slew-rate = <0>;
2625 };
2626 pins2 {
2627 pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */
2628 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
2629 bias-disable;
2630 };
2631 };
2632
2633 usart3_idle_pins_d: usart3-idle-3 {
2634 pins1 {
2635 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
2636 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
2637 <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
2638 };
2639 pins2 {
2640 pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */
2641 bias-disable;
2642 };
2643 };
2644
2645 usart3_sleep_pins_d: usart3-sleep-3 {
2646 pins {
2647 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
2648 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
2649 <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
2650 <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */
2651 };
2652 };
2653
Marek Vasutadbb8302022-06-13 11:55:16 +0200[diff] [blame]2654 usart3_pins_e: usart3-4 {
2655 pins1 {
2656 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
2657 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
2658 bias-disable;
2659 drive-push-pull;
2660 slew-rate = <0>;
2661 };
2662 pins2 {
2663 pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */
2664 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
2665 bias-pull-up;
2666 };
2667 };
2668
2669 usart3_idle_pins_e: usart3-idle-4 {
2670 pins1 {
2671 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
2672 <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
2673 };
2674 pins2 {
2675 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
2676 bias-disable;
2677 drive-push-pull;
2678 slew-rate = <0>;
2679 };
2680 pins3 {
2681 pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
2682 bias-pull-up;
2683 };
2684 };
2685
2686 usart3_sleep_pins_e: usart3-sleep-4 {
2687 pins {
2688 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
2689 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
2690 <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
2691 <STM32_PINMUX('B', 11, ANALOG)>; /* USART3_RX */
2692 };
2693 };
2694
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]2695 usart3_pins_f: usart3-5 {
2696 pins1 {
2697 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
2698 <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS */
2699 bias-disable;
2700 drive-push-pull;
2701 slew-rate = <0>;
2702 };
2703 pins2 {
2704 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
2705 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
2706 bias-disable;
2707 };
2708 };
2709
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]2710 usbotg_hs_pins_a: usbotg-hs-0 {
2711 pins {
2712 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
2713 };
2714 };
2715
2716 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
2717 pins {
2718 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
2719 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2720 };
2721 };
2722};
2723
2724&pinctrl_z {
2725 i2c2_pins_b2: i2c2-0 {
2726 pins {
2727 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
2728 bias-disable;
2729 drive-open-drain;
2730 slew-rate = <0>;
2731 };
2732 };
2733
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]2734 i2c2_sleep_pins_b2: i2c2-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2735 pins {
2736 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
2737 };
2738 };
2739
2740 i2c4_pins_a: i2c4-0 {
2741 pins {
2742 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
2743 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
2744 bias-disable;
2745 drive-open-drain;
2746 slew-rate = <0>;
2747 };
2748 };
2749
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame]2750 i2c4_sleep_pins_a: i2c4-sleep-0 {
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2751 pins {
2752 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
2753 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
2754 };
2755 };
2756
Patrick Delaunaye48a0d42021-06-29 12:01:07 +0200[diff] [blame]2757 i2c6_pins_a: i2c6-0 {
2758 pins {
2759 pinmux = <STM32_PINMUX('Z', 6, AF2)>, /* I2C6_SCL */
2760 <STM32_PINMUX('Z', 7, AF2)>; /* I2C6_SDA */
2761 bias-disable;
2762 drive-open-drain;
2763 slew-rate = <0>;
2764 };
2765 };
2766
2767 i2c6_sleep_pins_a: i2c6-sleep-0 {
2768 pins {
2769 pinmux = <STM32_PINMUX('Z', 6, ANALOG)>, /* I2C6_SCL */
2770 <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C6_SDA */
2771 };
2772 };
2773
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2774 spi1_pins_a: spi1-0 {
2775 pins1 {
2776 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
2777 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
2778 bias-disable;
2779 drive-push-pull;
2780 slew-rate = <1>;
2781 };
2782
2783 pins2 {
2784 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
2785 bias-disable;
Patrice Chotard02d88c02023-09-26 17:09:18 +0200[diff] [blame]2786 };
2787 };
2788
2789 spi1_sleep_pins_a: spi1-sleep-0 {
2790 pins {
2791 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
2792 <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
2793 <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
2794 };
2795 };
2796
2797 usart1_pins_b: usart1-1 {
2798 pins1 {
2799 pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */
2800 bias-disable;
2801 drive-push-pull;
2802 slew-rate = <0>;
2803 };
2804 pins2 {
2805 pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
2806 bias-disable;
2807 };
2808 };
2809
2810 usart1_idle_pins_b: usart1-idle-1 {
2811 pins1 {
2812 pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* USART1_TX */
2813 };
2814 pins2 {
2815 pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
2816 bias-disable;
2817 };
2818 };
2819
2820 usart1_sleep_pins_b: usart1-sleep-1 {
2821 pins {
2822 pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */
2823 <STM32_PINMUX('Z', 6, ANALOG)>; /* USART1_RX */
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2824 };
2825 };
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]2826};