arm: dts: stm32mp15: alignment with v5.18
Device tree alignment with Linux kernel v5.18-rc2:
- ARM: dts: stm32: Add support for the emtrion emSBC-Argon
(only the pincontrol part)
- ARM: dts: stm32: Drop duplicate status okay from DHCOM gpioc node
- ARM: dts: stm32: add st,stm32-sdmmc2 compatible on stm32mp151
- ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15
- ARM: dts: stm32: use exti 19 as main interrupt to support RTC wakeup on
stm32mp157
- ARM: dts: stm32: add DMA configuration to UART nodes on stm32mp151
- ARM: dts: stm32: keep uart4 behavior on *
- ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index 6161f59..f0d66d8 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -338,6 +338,47 @@
};
};
+ ethernet0_rmii_pins_b: rmii-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */
+ <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
+ <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */
+ <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */
+ bias-disable;
+ };
+ pins4 {
+ pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */
+ };
+ };
+
+ ethernet0_rmii_sleep_pins_b: rmii-sleep-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
+ <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */
+ <STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
+ <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */
+ };
+ };
+
fmc_pins_a: fmc-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
@@ -927,6 +968,21 @@
};
};
+ pwm1_pins_b: pwm1-1 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm1_sleep_pins_b: pwm1-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */
+ };
+ };
+
pwm2_pins_a: pwm2-0 {
pins {
pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
@@ -2042,6 +2098,42 @@
};
};
+ usart3_pins_d: usart3-3 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */
+ <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart3_idle_pins_d: usart3-idle-3 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+ <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */
+ bias-disable;
+ };
+ };
+
+ usart3_sleep_pins_d: usart3-sleep-3 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+ <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
+ <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */
+ };
+ };
+
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */