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git01.mediatek.com / filogic / uboot / 2bd82cfb27ed2311498b732c35b3bc7a3e411180 / . / arch / arm / dts / s5pc100-pinctrl.dtsi
blob: 290f4cfd03a2185f6fed5aac88b4ff351bcf4227 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Simon Glass5d6927a2014-10-20 19:48:33 -0600[diff] [blame]2/*
3 * U-Boot additions to enable a generic Exynos GPIO driver
4 *
5 * Copyright (c) 2014 Google, Inc
Simon Glass5d6927a2014-10-20 19:48:33 -0600[diff] [blame]6 */
7
8/ {
9 pinctrl@e0300000 {
10 gpa0: gpa0 {
11 gpio-controller;
12 #gpio-cells = <2>;
13 };
14
15 gpa1: gpa1 {
16 gpio-controller;
17 #gpio-cells = <2>;
18 };
19
20 gpb: gpb {
21 gpio-controller;
22 #gpio-cells = <2>;
23 };
24
25 gpc: gpc {
26 gpio-controller;
27 #gpio-cells = <2>;
28 };
29
30 gpd: gpd {
31 gpio-controller;
32 #gpio-cells = <2>;
33 };
34
35 gpe0: gpe0 {
36 gpio-controller;
37 #gpio-cells = <2>;
38 };
39
40 gpe1: gpe1 {
41 gpio-controller;
42 #gpio-cells = <2>;
43 };
44
45 gpf0: gpf0 {
46 gpio-controller;
47 #gpio-cells = <2>;
48 };
49
50 gpf1: gpf1 {
51 gpio-controller;
52 #gpio-cells = <2>;
53 };
54
55 gpf2: gpf2 {
56 gpio-controller;
57 #gpio-cells = <2>;
58 };
59
60 gpf3: gpf3 {
61 gpio-controller;
62 #gpio-cells = <2>;
63 };
64
65 gpg0: gpg0 {
66 gpio-controller;
67 #gpio-cells = <2>;
68 };
69
70 gpg1: gpg1 {
71 gpio-controller;
72 #gpio-cells = <2>;
73 };
74
75 gpg2: gpg2 {
76 gpio-controller;
77 #gpio-cells = <2>;
78 };
79
80 gpg3: gpg3 {
81 gpio-controller;
82 #gpio-cells = <2>;
83 };
84
85 gpi: gpi {
86 gpio-controller;
87 #gpio-cells = <2>;
88 };
89
90 gpj0: gpj0 {
91 gpio-controller;
92 #gpio-cells = <2>;
93 };
94
95 gpj1: gpj1 {
96 gpio-controller;
97 #gpio-cells = <2>;
98 };
99
100 gpj2: gpj2 {
101 gpio-controller;
102 #gpio-cells = <2>;
103 };
104
105 gpj3: gpj3 {
106 gpio-controller;
107 #gpio-cells = <2>;
108 };
109
110 gpj4: gpj4 {
111 gpio-controller;
112 #gpio-cells = <2>;
113 };
114
115 gpk0: gpk0 {
116 gpio-controller;
117 #gpio-cells = <2>;
118 };
119
120 gpk1: gpk1 {
121 gpio-controller;
122 #gpio-cells = <2>;
123 };
124
125 gpk2: gpk2 {
126 gpio-controller;
127 #gpio-cells = <2>;
128 };
129
130 gpk3: gpk3 {
131 gpio-controller;
132 #gpio-cells = <2>;
133 };
134
135 gpl0: gpl0 {
136 gpio-controller;
137 #gpio-cells = <2>;
138 };
139
140 gpl1: gpl1 {
141 gpio-controller;
142 #gpio-cells = <2>;
143 };
144
145 gpl2: gpl2 {
146 gpio-controller;
147 #gpio-cells = <2>;
148 };
149
150 gpl3: gpl3 {
151 gpio-controller;
152 #gpio-cells = <2>;
153 };
154
155 gpl4: gpl4 {
156 gpio-controller;
157 #gpio-cells = <2>;
158 };
159
160 gph0: gph0 {
161 gpio-controller;
162 #gpio-cells = <2>;
163 };
164
165 gph1: gph1 {
166 gpio-controller;
167 #gpio-cells = <2>;
168 };
169
170 gph2: gph2 {
171 gpio-controller;
172 #gpio-cells = <2>;
173 };
174
175 gph3: gph3 {
176 gpio-controller;
177 #gpio-cells = <2>;
178 };
179
180 };
181};