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git01.mediatek.com / filogic / uboot / 5d6927a429c24093494c5e68b19527bb3af12fab / . / arch / arm / dts / s5pc100-pinctrl.dtsi
blob: bd9f97c97ba8a12ad87f6b6cb3e0abfad93c0b94 [file] [log] [blame]
Simon Glass5d6927a2014-10-20 19:48:33 -0600[diff] [blame^]1/*
2 * U-Boot additions to enable a generic Exynos GPIO driver
3 *
4 * Copyright (c) 2014 Google, Inc
5 */
6
7/ {
8 pinctrl@e0300000 {
9 gpa0: gpa0 {
10 gpio-controller;
11 #gpio-cells = <2>;
12 };
13
14 gpa1: gpa1 {
15 gpio-controller;
16 #gpio-cells = <2>;
17 };
18
19 gpb: gpb {
20 gpio-controller;
21 #gpio-cells = <2>;
22 };
23
24 gpc: gpc {
25 gpio-controller;
26 #gpio-cells = <2>;
27 };
28
29 gpd: gpd {
30 gpio-controller;
31 #gpio-cells = <2>;
32 };
33
34 gpe0: gpe0 {
35 gpio-controller;
36 #gpio-cells = <2>;
37 };
38
39 gpe1: gpe1 {
40 gpio-controller;
41 #gpio-cells = <2>;
42 };
43
44 gpf0: gpf0 {
45 gpio-controller;
46 #gpio-cells = <2>;
47 };
48
49 gpf1: gpf1 {
50 gpio-controller;
51 #gpio-cells = <2>;
52 };
53
54 gpf2: gpf2 {
55 gpio-controller;
56 #gpio-cells = <2>;
57 };
58
59 gpf3: gpf3 {
60 gpio-controller;
61 #gpio-cells = <2>;
62 };
63
64 gpg0: gpg0 {
65 gpio-controller;
66 #gpio-cells = <2>;
67 };
68
69 gpg1: gpg1 {
70 gpio-controller;
71 #gpio-cells = <2>;
72 };
73
74 gpg2: gpg2 {
75 gpio-controller;
76 #gpio-cells = <2>;
77 };
78
79 gpg3: gpg3 {
80 gpio-controller;
81 #gpio-cells = <2>;
82 };
83
84 gpi: gpi {
85 gpio-controller;
86 #gpio-cells = <2>;
87 };
88
89 gpj0: gpj0 {
90 gpio-controller;
91 #gpio-cells = <2>;
92 };
93
94 gpj1: gpj1 {
95 gpio-controller;
96 #gpio-cells = <2>;
97 };
98
99 gpj2: gpj2 {
100 gpio-controller;
101 #gpio-cells = <2>;
102 };
103
104 gpj3: gpj3 {
105 gpio-controller;
106 #gpio-cells = <2>;
107 };
108
109 gpj4: gpj4 {
110 gpio-controller;
111 #gpio-cells = <2>;
112 };
113
114 gpk0: gpk0 {
115 gpio-controller;
116 #gpio-cells = <2>;
117 };
118
119 gpk1: gpk1 {
120 gpio-controller;
121 #gpio-cells = <2>;
122 };
123
124 gpk2: gpk2 {
125 gpio-controller;
126 #gpio-cells = <2>;
127 };
128
129 gpk3: gpk3 {
130 gpio-controller;
131 #gpio-cells = <2>;
132 };
133
134 gpl0: gpl0 {
135 gpio-controller;
136 #gpio-cells = <2>;
137 };
138
139 gpl1: gpl1 {
140 gpio-controller;
141 #gpio-cells = <2>;
142 };
143
144 gpl2: gpl2 {
145 gpio-controller;
146 #gpio-cells = <2>;
147 };
148
149 gpl3: gpl3 {
150 gpio-controller;
151 #gpio-cells = <2>;
152 };
153
154 gpl4: gpl4 {
155 gpio-controller;
156 #gpio-cells = <2>;
157 };
158
159 gph0: gph0 {
160 gpio-controller;
161 #gpio-cells = <2>;
162 };
163
164 gph1: gph1 {
165 gpio-controller;
166 #gpio-cells = <2>;
167 };
168
169 gph2: gph2 {
170 gpio-controller;
171 #gpio-cells = <2>;
172 };
173
174 gph3: gph3 {
175 gpio-controller;
176 #gpio-cells = <2>;
177 };
178
179 };
180};