Yanhong Wang | 5a85d05 | 2023-03-29 11:42:13 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2022 Starfive, Inc. |
| 4 | * Author: Yanhong Wang <yanhong.wang@starfivetech.com> |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef __CLK_STARFIVE_H |
| 9 | #define __CLK_STARFIVE_H |
| 10 | |
| 11 | enum starfive_pll_type { |
| 12 | PLL0 = 0, |
| 13 | PLL1, |
| 14 | PLL2, |
| 15 | PLL_MAX = PLL2 |
| 16 | }; |
| 17 | |
| 18 | struct starfive_pllx_rate { |
| 19 | u64 rate; |
| 20 | u32 prediv; |
| 21 | u32 fbdiv; |
| 22 | u32 frac; |
| 23 | }; |
| 24 | |
| 25 | struct starfive_pllx_offset { |
| 26 | u32 pd; |
| 27 | u32 prediv; |
| 28 | u32 fbdiv; |
| 29 | u32 frac; |
| 30 | u32 postdiv1; |
| 31 | u32 dacpd; |
| 32 | u32 dsmpd; |
| 33 | u32 pd_mask; |
| 34 | u32 prediv_mask; |
| 35 | u32 fbdiv_mask; |
| 36 | u32 frac_mask; |
| 37 | u32 postdiv1_mask; |
| 38 | u32 dacpd_mask; |
| 39 | u32 dsmpd_mask; |
| 40 | }; |
| 41 | |
| 42 | struct starfive_pllx_clk { |
| 43 | enum starfive_pll_type type; |
| 44 | const struct starfive_pllx_offset *offset; |
| 45 | const struct starfive_pllx_rate *rate_table; |
| 46 | int rate_count; |
| 47 | int flags; |
| 48 | }; |
| 49 | |
| 50 | extern struct starfive_pllx_clk starfive_jh7110_pll0; |
| 51 | extern struct starfive_pllx_clk starfive_jh7110_pll1; |
| 52 | extern struct starfive_pllx_clk starfive_jh7110_pll2; |
| 53 | |
| 54 | struct clk *starfive_jh7110_pll(const char *name, const char *parent_name, |
| 55 | void __iomem *base, void __iomem *sysreg, |
| 56 | const struct starfive_pllx_clk *pll_clk); |
| 57 | #endif |