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Stelian Pop0bf5cad2008-05-08 18:52:25 +02001/*
2 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Pop0bf5cad2008-05-08 18:52:25 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * Configuation settings for the AT91SAM9RLEK board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Xu, Hong0c0fb212011-08-01 03:56:53 +000030#include <asm/hardware.h>
31
32#define CONFIG_SYS_TEXT_BASE 0x21F00000
Jens Scharsig128ecd02010-02-03 22:45:42 +010033
Stelian Pop0bf5cad2008-05-08 18:52:25 +020034/* ARM asynchronous clock */
Xu, Hong0c0fb212011-08-01 03:56:53 +000035#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
36#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
37#define CONFIG_SYS_HZ 1000
Stelian Pop0bf5cad2008-05-08 18:52:25 +020038
Xu, Hong0c0fb212011-08-01 03:56:53 +000039#define CONFIG_AT91SAM9RLEK 1 /* It's an AT91SAM9RLEK Board */
40
Jean-Christophe PLAGNIOL-VILLARD23164f12009-04-16 21:30:44 +020041#define CONFIG_ARCH_CPU_INIT
Xu, Hong0c0fb212011-08-01 03:56:53 +000042#define CONFIG_SKIP_LOWLEVEL_INIT
43#define CONFIG_BOARD_EARLY_INIT_F
Stelian Pop0bf5cad2008-05-08 18:52:25 +020044
Xu, Hong0c0fb212011-08-01 03:56:53 +000045#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
46#define CONFIG_SETUP_MEMORY_TAGS 1
47#define CONFIG_INITRD_TAG 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +020048
Xu, Hong0c0fb212011-08-01 03:56:53 +000049#define CONFIG_DISPLAY_CPUINFO
50
Nicolas Ferree4f36232013-02-20 00:16:24 +000051#define CONFIG_CMD_BOOTZ
Nicolas Ferre6ddbdb12013-02-20 00:16:23 +000052#define CONFIG_OF_LIBFDT
53
Xu, Hong0c0fb212011-08-01 03:56:53 +000054#define CONFIG_ATMEL_LEGACY
55#define CONFIG_AT91_GPIO 1
56#define CONFIG_AT91_GPIO_PULLUP 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +020057
58/*
59 * Hardware drivers
60 */
Xu, Hong0c0fb212011-08-01 03:56:53 +000061
62/* serial console */
63#define CONFIG_ATMEL_USART
64#define CONFIG_USART_BASE ATMEL_BASE_DBGU
65#define CONFIG_USART_ID ATMEL_ID_SYS
66#define CONFIG_BAUDRATE 115200
Stelian Pop0bf5cad2008-05-08 18:52:25 +020067
Stelian Popcea5c532008-05-08 14:52:32 +020068/* LCD */
69#define CONFIG_LCD 1
70#define LCD_BPP LCD_COLOR8
71#define CONFIG_LCD_LOGO 1
72#undef LCD_TEST_PATTERN
73#define CONFIG_LCD_INFO 1
74#define CONFIG_LCD_INFO_BELOW_LOGO 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000075#define CONFIG_SYS_WHITE_ON_BLACK 1
Stelian Popcea5c532008-05-08 14:52:32 +020076#define CONFIG_ATMEL_LCD 1
77#define CONFIG_ATMEL_LCD_RGB565 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000078/* Let board_init_f handle the framebuffer allocation */
79#undef CONFIG_FB_ADDR
80#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
81
Stelian Popcea5c532008-05-08 14:52:32 +020082
Jean-Christophe PLAGNIOL-VILLARD476d10e2009-03-21 21:08:00 +010083/* LED */
84#define CONFIG_AT91_LED
85#define CONFIG_RED_LED AT91_PIN_PD14 /* this is the power led */
86#define CONFIG_GREEN_LED AT91_PIN_PD15 /* this is the user1 led */
87#define CONFIG_YELLOW_LED AT91_PIN_PD16 /* this is the user2 led */
88
Stelian Pop0bf5cad2008-05-08 18:52:25 +020089#define CONFIG_BOOTDELAY 3
90
Stelian Pop0bf5cad2008-05-08 18:52:25 +020091/*
92 * Command line configuration.
93 */
94#include <config_cmd_default.h>
95#undef CONFIG_CMD_BDI
Stelian Pop0bf5cad2008-05-08 18:52:25 +020096#undef CONFIG_CMD_FPGA
Wolfgang Denk85c25df2009-04-01 23:34:12 +020097#undef CONFIG_CMD_IMI
Stelian Pop0bf5cad2008-05-08 18:52:25 +020098#undef CONFIG_CMD_IMLS
Wolfgang Denk85c25df2009-04-01 23:34:12 +020099#undef CONFIG_CMD_LOADS
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200100#undef CONFIG_CMD_NET
Xu, Hong0c0fb212011-08-01 03:56:53 +0000101#undef CONFIG_CMD_NFS
Wolfgang Denk85c25df2009-04-01 23:34:12 +0200102#undef CONFIG_CMD_SOURCE
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200103#undef CONFIG_CMD_USB
104
Xu, Hong0c0fb212011-08-01 03:56:53 +0000105#define CONFIG_CMD_NAND 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200106
107/* SDRAM */
108#define CONFIG_NR_DRAM_BANKS 1
Xu, Hong0c0fb212011-08-01 03:56:53 +0000109#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
110#define CONFIG_SYS_SDRAM_SIZE 0x04000000
111
112#define CONFIG_SYS_INIT_SP_ADDR \
113 (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200114
115/* DataFlash */
Jean-Christophe PLAGNIOL-VILLARDe5437ac2009-03-27 23:26:44 +0100116#define CONFIG_ATMEL_DATAFLASH_SPI
Xu, Hong0c0fb212011-08-01 03:56:53 +0000117#define CONFIG_HAS_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200118#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
119#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
120#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
Xu, Hong0c0fb212011-08-01 03:56:53 +0000121#define AT91_SPI_CLK 15000000
122#define DATAFLASH_TCSS (0x1a << 16)
123#define DATAFLASH_TCHS (0x1 << 24)
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200124
125/* NOR flash - not present */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126#define CONFIG_SYS_NO_FLASH 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200127
128/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100129#ifdef CONFIG_CMD_NAND
130#define CONFIG_NAND_ATMEL
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_MAX_NAND_DEVICE 1
Xu, Hong0c0fb212011-08-01 03:56:53 +0000132#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_NAND_DBW_8 1
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100134/* our ALE is AD21 */
135#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
136/* our CLE is AD22 */
137#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
138#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
139#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
Wolfgang Denk1f797742009-07-18 21:52:24 +0200140
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100141#endif
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200142
143/* Ethernet - not present */
144
145/* USB - not supported */
146
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200148
Xu, Hong0c0fb212011-08-01 03:56:53 +0000149#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#define CONFIG_SYS_MEMTEST_END 0x23e00000
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200151
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#ifdef CONFIG_SYS_USE_DATAFLASH
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200153
154/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Jean-Christophe PLAGNIOL-VILLARD2b14d2b2008-09-10 22:47:58 +0200155#define CONFIG_ENV_IS_IN_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200156#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200157#define CONFIG_ENV_OFFSET 0x4200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200159#define CONFIG_ENV_SIZE 0x4200
Alexandre Belloni9ef19ba2012-07-02 04:26:58 +0000160#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200161#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
162 "root=/dev/mtdblock0 " \
Albin Tonnerreeaa6db22009-07-22 18:30:03 +0200163 "mtdparts=atmel_nand:-(root) "\
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200164 "rw rootfstype=jffs2"
165
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166#else /* CONFIG_SYS_USE_NANDFLASH */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200167
168/* bootstrap + u-boot + env + linux in nandflash */
Xu, Hong0c0fb212011-08-01 03:56:53 +0000169#define CONFIG_ENV_IS_IN_NAND 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200170#define CONFIG_ENV_OFFSET 0x60000
171#define CONFIG_ENV_OFFSET_REDUND 0x80000
172#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200173#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
174#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
175 "root=/dev/mtdblock5 " \
Albin Tonnerreeaa6db22009-07-22 18:30:03 +0200176 "mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200177 "rw rootfstype=jffs2"
178
179#endif
180
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200181#define CONFIG_SYS_PROMPT "U-Boot> "
182#define CONFIG_SYS_CBSIZE 256
183#define CONFIG_SYS_MAXARGS 16
184#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
185#define CONFIG_SYS_LONGHELP 1
Xu, Hong0c0fb212011-08-01 03:56:53 +0000186#define CONFIG_CMDLINE_EDITING 1
Alexandre Belloni9ef19ba2012-07-02 04:26:58 +0000187#define CONFIG_AUTO_COMPLETE
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200188
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200189/*
190 * Size of malloc() pool
191 */
Xu, Hong0c0fb212011-08-01 03:56:53 +0000192#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200193
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200194#endif