| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| Dmitry Lifshitz | c3ad3a0 | 2014-05-19 12:50:54 +0300 | [diff] [blame] | 2 | /* |
| 3 | * Pinmux configuration for Compulab CM-T54 board |
| 4 | * |
| 5 | * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ |
| 6 | * |
| 7 | * Author: Dmitry Lifshitz <lifshitz@compulab.co.il> |
| Dmitry Lifshitz | c3ad3a0 | 2014-05-19 12:50:54 +0300 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef _CM_T54_MUX_DATA_H |
| 11 | #define _CM_T54_MUX_DATA_H |
| 12 | |
| 13 | #include <asm/arch/mux_omap5.h> |
| 14 | #include <asm/arch/sys_proto.h> |
| 15 | |
| 16 | const struct pad_conf_entry core_padconf_array_essential[] = { |
| 17 | /* MMC1 - SD CARD */ |
| 18 | {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */ |
| 19 | {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */ |
| 20 | {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0 */ |
| 21 | {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1 */ |
| 22 | {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2 */ |
| 23 | {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3 */ |
| 24 | |
| 25 | /* SD CARD CD and WP GPIOs*/ |
| 26 | {TIMER5_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_228 */ |
| 27 | {TIMER6_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_229 */ |
| 28 | |
| 29 | /* MMC2 - eMMC */ |
| 30 | {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */ |
| 31 | {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */ |
| 32 | {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */ |
| 33 | {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */ |
| 34 | {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */ |
| 35 | {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */ |
| 36 | {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */ |
| 37 | {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */ |
| 38 | {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */ |
| 39 | {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */ |
| 40 | |
| 41 | /* UART4 */ |
| 42 | {I2C5_SCL, (PTU | IEN | M2)}, /* UART4_RX */ |
| 43 | {I2C5_SDA, (M2)}, /* UART4_TX */ |
| 44 | |
| 45 | /* Led */ |
| 46 | {HSI2_CAFLAG, (PTU | M6)}, /* GPIO3_80 */ |
| 47 | |
| 48 | /* I2C1 */ |
| 49 | {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ |
| 50 | {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ |
| 51 | |
| 52 | /* USBB2, USBB3 */ |
| 53 | {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ |
| 54 | {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ |
| 55 | {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE */ |
| 56 | {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ |
| 57 | |
| 58 | /* USB Hub and USB Eth reset GPIOs */ |
| 59 | {HSI2_CAREADY, (PTD | M6)}, /* GPIO3_76 */ |
| 60 | {HSI2_ACDATA, (PTD | M6)}, /* GPIO3_83 */ |
| 61 | |
| 62 | /* I2C4 */ |
| 63 | {I2C4_SCL, (PTU | IEN | M0)}, /* I2C4_SCL */ |
| 64 | {I2C4_SDA, (PTU | IEN | M0)}, /* I2C4_SDA */ |
| 65 | }; |
| 66 | |
| 67 | const struct pad_conf_entry wkup_padconf_array_essential[] = { |
| 68 | {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */ |
| 69 | {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */ |
| 70 | {SYS_32K, (IEN | M0)}, /* SYS_32K */ |
| 71 | |
| 72 | /* USB Hub clock */ |
| 73 | {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */ |
| 74 | }; |
| 75 | |
| 76 | /* |
| Paul Kocialkowski | a00b1e5 | 2016-02-27 19:18:56 +0100 | [diff] [blame] | 77 | * Routine: set_muxconf_regs |
| Dmitry Lifshitz | c3ad3a0 | 2014-05-19 12:50:54 +0300 | [diff] [blame] | 78 | * Description: setup board pinmux configuration. |
| 79 | */ |
| Paul Kocialkowski | a00b1e5 | 2016-02-27 19:18:56 +0100 | [diff] [blame] | 80 | void set_muxconf_regs(void) |
| Dmitry Lifshitz | c3ad3a0 | 2014-05-19 12:50:54 +0300 | [diff] [blame] | 81 | { |
| 82 | do_set_mux((*ctrl)->control_padconf_core_base, |
| 83 | core_padconf_array_essential, |
| 84 | sizeof(core_padconf_array_essential) / |
| 85 | sizeof(struct pad_conf_entry)); |
| 86 | |
| 87 | do_set_mux((*ctrl)->control_padconf_wkup_base, |
| 88 | wkup_padconf_array_essential, |
| 89 | sizeof(wkup_padconf_array_essential) / |
| 90 | sizeof(struct pad_conf_entry)); |
| 91 | } |
| 92 | |
| 93 | #endif /* _CM_T54_MUX_DATA_H */ |