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git01.mediatek.com / filogic / uboot / 2a00cc9b5d9a7fe8601989a02ee81e62eec360a5 / . / arch / arm / dts / tegra114-dalmore.dts
blob: 18bcb75fafa09f65d061bb27e0074e78bc3ca76a [file] [log] [blame]
Tom Warrenf11e89f2013-01-28 13:32:11 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]3#include "tegra114.dtsi"
Tom Warrenf11e89f2013-01-28 13:32:11 +0000[diff] [blame]4
5/ {
6 model = "NVIDIA Dalmore";
7 compatible = "nvidia,dalmore", "nvidia,tegra114";
8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uartd;
11 };
12
Tom Warren9b22f832013-03-11 17:07:21 -0700[diff] [blame]13 aliases {
14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c400";
17 i2c3 = "/i2c@7000c500";
18 i2c4 = "/i2c@7000c700";
Stephen Warrend55aadc2016-09-13 10:45:43 -0600[diff] [blame]19 mmc0 = "/sdhci@78000600";
20 mmc1 = "/sdhci@78000400";
Stephen Warren82c80b22016-02-15 10:34:04 -0700[diff] [blame]21 usb0 = "/usb@7d000000";
22 usb1 = "/usb@7d008000";
Tom Warren9b22f832013-03-11 17:07:21 -0700[diff] [blame]23 };
24
Tom Warrenf11e89f2013-01-28 13:32:11 +0000[diff] [blame]25 memory {
26 device_type = "memory";
27 reg = <0x80000000 0x80000000>;
28 };
Tom Warren36092ff2013-02-08 07:25:31 +0000[diff] [blame]29
30 i2c@7000c000 {
31 status = "okay";
32 clock-frequency = <100000>;
33 };
34
35 i2c@7000c400 {
36 status = "okay";
37 clock-frequency = <100000>;
38 };
39
40 i2c@7000c500 {
41 status = "okay";
42 clock-frequency = <100000>;
43 };
44
45 i2c@7000c700 {
46 status = "okay";
47 clock-frequency = <100000>;
48 };
49
50 i2c@7000d000 {
51 status = "okay";
52 clock-frequency = <400000>;
53 };
Allen Martinfc1df282013-03-16 18:58:12 +0000[diff] [blame]54
55 spi@7000da00 {
56 status = "okay";
57 spi-max-frequency = <25000000>;
58 };
Tom Warrenbe479a82013-03-18 14:46:46 -0700[diff] [blame]59
60 sdhci@78000400 {
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]61 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
Tom Warrenbe479a82013-03-18 14:46:46 -0700[diff] [blame]62 bus-width = <4>;
63 status = "okay";
64 };
65
66 sdhci@78000600 {
67 bus-width = <8>;
68 status = "okay";
Tom Warren1c77f022016-09-13 10:45:42 -0600[diff] [blame]69 non-removable;
Tom Warrenbe479a82013-03-18 14:46:46 -0700[diff] [blame]70 };
Jim Lindfed30e2013-06-21 19:05:46 +0800[diff] [blame]71
Stephen Warren82c80b22016-02-15 10:34:04 -0700[diff] [blame]72 usb@7d000000 {
73 status = "okay";
74 dr_mode = "otg";
75 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
76 };
77
Jim Lindfed30e2013-06-21 19:05:46 +0800[diff] [blame]78 usb@7d008000 {
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]79 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
Jim Lindfed30e2013-06-21 19:05:46 +0800[diff] [blame]80 status = "okay";
81 };
Stephen Warren8148b9f2016-09-13 10:45:52 -0600[diff] [blame]82
83 clocks {
84 compatible = "simple-bus";
85 #address-cells = <1>;
86 #size-cells = <0>;
87
88 clk32k_in: clock@0 {
89 compatible = "fixed-clock";
90 reg=<0>;
91 #clock-cells = <0>;
92 clock-frequency = <32768>;
93 };
94 };
Tom Warrenf11e89f2013-01-28 13:32:11 +0000[diff] [blame]95};
Simon Glass2a00cc92017-06-12 06:22:01 -0600[diff] [blame^]96
97&uartd {
98 status = "okay";
99};