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git01.mediatek.com / filogic / uboot / 29d23ec56dd038b776a626068b518bd5c2120748 / . / arch / x86 / cpu / ivybridge / early_init.c
blob: eb8f6139fe9a0d704ddd6a6c5e5a8e57a6be01de [file] [log] [blame]
Simon Glass30580fc2014-11-12 22:42:23 -0700[diff] [blame]1/*
2 * From Coreboot
3 *
4 * Copyright (C) 2007-2010 coresystems GmbH
5 * Copyright (C) 2011 Google Inc
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <asm/io.h>
12#include <asm/pci.h>
13#include <asm/arch/pch.h>
14#include <asm/arch/sandybridge.h>
15
16static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev)
17{
18 /* Setting up Southbridge. In the northbridge code. */
19 debug("Setting up static southbridge registers\n");
20 pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
21
22 pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
23 pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
24
25 debug("Disabling watchdog reboot\n");
26 setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
27 outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
28
29 /* Set up all hardcoded northbridge BARs */
30 debug("Setting up static registers\n");
31 pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1);
32 pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
33 pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1);
34 pci_write_config32(pch_dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
35 /* 64MB - busses 0-63 */
36 pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
37 pci_write_config32(pch_dev, PCIEXBAR + 4,
38 (0LL + DEFAULT_PCIEXBAR) >> 32);
39 pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1);
40 pci_write_config32(pch_dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
41
42 /* Set C0000-FFFFF to access RAM on both reads and writes */
43 pci_write_config8(pch_dev, PAM0, 0x30);
44 pci_write_config8(pch_dev, PAM1, 0x33);
45 pci_write_config8(pch_dev, PAM2, 0x33);
46 pci_write_config8(pch_dev, PAM3, 0x33);
47 pci_write_config8(pch_dev, PAM4, 0x33);
48 pci_write_config8(pch_dev, PAM5, 0x33);
49 pci_write_config8(pch_dev, PAM6, 0x33);
50}
51
52static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
53{
54 u32 reg32;
55 u16 reg16;
56 u8 reg8;
57
58 reg16 = pci_read_config16(video_dev, PCI_DEVICE_ID);
59 switch (reg16) {
60 case 0x0102: /* GT1 Desktop */
61 case 0x0106: /* GT1 Mobile */
62 case 0x010a: /* GT1 Server */
63 case 0x0112: /* GT2 Desktop */
64 case 0x0116: /* GT2 Mobile */
65 case 0x0122: /* GT2 Desktop >=1.3GHz */
66 case 0x0126: /* GT2 Mobile >=1.3GHz */
67 case 0x0156: /* IvyBridge */
68 case 0x0166: /* IvyBridge */
69 break;
70 default:
71 debug("Graphics not supported by this CPU/chipset\n");
72 return;
73 }
74
75 debug("Initialising Graphics\n");
76
77 /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
78 reg16 = pci_read_config16(pch_dev, GGC);
79 reg16 &= ~0x00f8;
80 reg16 |= 1 << 3;
81 /* Program GTT memory by setting GGC[9:8] = 2MB */
82 reg16 &= ~0x0300;
83 reg16 |= 2 << 8;
84 /* Enable VGA decode */
85 reg16 &= ~0x0002;
86 pci_write_config16(pch_dev, GGC, reg16);
87
88 /* Enable 256MB aperture */
89 reg8 = pci_read_config8(video_dev, MSAC);
90 reg8 &= ~0x06;
91 reg8 |= 0x02;
92 pci_write_config8(video_dev, MSAC, reg8);
93
94 /* Erratum workarounds */
95 reg32 = readl(MCHBAR_REG(0x5f00));
96 reg32 |= (1 << 9) | (1 << 10);
97 writel(reg32, MCHBAR_REG(0x5f00));
98
99 /* Enable SA Clock Gating */
100 reg32 = readl(MCHBAR_REG(0x5f00));
101 writel(reg32 | 1, MCHBAR_REG(0x5f00));
102
103 /* GPU RC6 workaround for sighting 366252 */
104 reg32 = readl(MCHBAR_REG(0x5d14));
105 reg32 |= (1 << 31);
106 writel(reg32, MCHBAR_REG(0x5d14));
107
108 /* VLW */
109 reg32 = readl(MCHBAR_REG(0x6120));
110 reg32 &= ~(1 << 0);
111 writel(reg32, MCHBAR_REG(0x6120));
112
113 reg32 = readl(MCHBAR_REG(0x5418));
114 reg32 |= (1 << 4) | (1 << 5);
115 writel(reg32, MCHBAR_REG(0x5418));
116}
117
118void sandybridge_early_init(int chipset_type)
119{
120 pci_dev_t pch_dev = PCH_DEV;
121 pci_dev_t video_dev = PCH_VIDEO_DEV;
122 pci_dev_t lpc_dev = PCH_LPC_DEV;
123 u32 capid0_a;
124 u8 reg8;
125
126 /* Device ID Override Enable should be done very early */
127 capid0_a = pci_read_config32(pch_dev, 0xe4);
128 if (capid0_a & (1 << 10)) {
129 reg8 = pci_read_config8(pch_dev, 0xf3);
130 reg8 &= ~7; /* Clear 2:0 */
131
132 if (chipset_type == SANDYBRIDGE_MOBILE)
133 reg8 |= 1; /* Set bit 0 */
134
135 pci_write_config8(pch_dev, 0xf3, reg8);
136 }
137
138 /* Setup all BARs required for early PCIe and raminit */
139 sandybridge_setup_bars(pch_dev, lpc_dev);
140
141 /* Device Enable */
142 pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
143
144 sandybridge_setup_graphics(pch_dev, video_dev);
145}