blob: 55f4c963608a08194a12301bcd960b604cb50604 [file] [log] [blame]
York Sun7b08d212014-06-23 15:15:56 -07001/*
2 * Copyright (C) 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS2_COMMON_H
8#define __LS2_COMMON_H
9
10#define CONFIG_SYS_GENERIC_BOARD
11
12#define CONFIG_REMAKE_ELF
13#define CONFIG_FSL_LSCH3
14#define CONFIG_LS2085A
15#define CONFIG_GICV3
Bhupesh Sharmaa0c00ff2015-01-06 13:11:21 -080016#define CONFIG_FSL_TZPC_BP147
York Sun7b08d212014-06-23 15:15:56 -070017
18/* Link Definitions */
York Sunc4da12e2014-09-08 12:20:02 -070019#define CONFIG_SYS_TEXT_BASE 0x30001000
York Sun7b08d212014-06-23 15:15:56 -070020
Prabhakar Kushwaha962b2de2014-07-16 09:21:12 +053021#ifdef CONFIG_EMU
York Sun7b08d212014-06-23 15:15:56 -070022#define CONFIG_SYS_NO_FLASH
Prabhakar Kushwaha962b2de2014-07-16 09:21:12 +053023#endif
York Sun7b08d212014-06-23 15:15:56 -070024
25#define CONFIG_SUPPORT_RAW_INITRD
26
27#define CONFIG_SKIP_LOWLEVEL_INIT
28#define CONFIG_BOARD_EARLY_INIT_F 1
29
York Sun7b08d212014-06-23 15:15:56 -070030/* Flat Device Tree Definitions */
31#define CONFIG_OF_LIBFDT
32#define CONFIG_OF_BOARD_SETUP
33
34/* new uImage format support */
35#define CONFIG_FIT
36#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
37
38#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
39#ifndef CONFIG_SYS_FSL_DDR4
40#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
41#define CONFIG_SYS_DDR_RAW_TIMING
42#endif
43#define CONFIG_DIMM_SLOTS_PER_CTLR 1
44#define CONFIG_CHIP_SELECTS_PER_CTRL 4
45
46#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
47
York Sun7b08d212014-06-23 15:15:56 -070048#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
49#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
50#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
51#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
York Sunc7a0e302014-08-13 10:21:05 -070052#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
53
York Sun290a83a2014-09-08 12:20:01 -070054/*
55 * SMP Definitinos
56 */
57#define CPU_RELEASE_ADDR secondary_boot_func
58
York Sunc7a0e302014-08-13 10:21:05 -070059#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
60#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
61/*
62 * DDR controller use 0 as the base address for binding.
63 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
64 */
65#define CONFIG_SYS_DP_DDR_BASE_PHY 0
66#define CONFIG_DP_DDR_CTRL 2
67#define CONFIG_DP_DDR_NUM_CTRLS 1
68#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
York Sun7b08d212014-06-23 15:15:56 -070069
70/* Generic Timer Definitions */
71#define COUNTER_FREQUENCY 12000000 /* 12MHz */
72
73/* Size of malloc() pool */
74#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
75
76/* I2C */
77#define CONFIG_CMD_I2C
78#define CONFIG_SYS_I2C
79#define CONFIG_SYS_I2C_MXC
80#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
81#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
82
83/* Serial Port */
84#define CONFIG_CONS_INDEX 2
85#define CONFIG_SYS_NS16550
86#define CONFIG_SYS_NS16550_SERIAL
87#define CONFIG_SYS_NS16550_REG_SIZE 1
88#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
89
90#define CONFIG_BAUDRATE 115200
91#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
92
93/* IFC */
94#define CONFIG_FSL_IFC
95#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
96#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
97/*
98 * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
99 * address 0. But this region is limited to 256MB. To accommodate bigger NOR
100 * flash and other devices, we will map CS0 to 0x580000000 after relocation.
101 * CONFIG_SYS_FLASH_BASE has the final address (core view)
102 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
103 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
104 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
105 */
106#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
107#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
108#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
109
110/*
111 * NOR Flash Timing Params
112 */
113#define CONFIG_SYS_NOR0_CSPR \
114 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
115 CSPR_PORT_SIZE_16 | \
116 CSPR_MSEL_NOR | \
117 CSPR_V)
118#define CONFIG_SYS_NOR0_CSPR_EARLY \
119 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
120 CSPR_PORT_SIZE_16 | \
121 CSPR_MSEL_NOR | \
122 CSPR_V)
123#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
124#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
125 FTIM0_NOR_TEADC(0x1) | \
126 FTIM0_NOR_TEAHC(0x1))
127#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
128 FTIM1_NOR_TRAD_NOR(0x1))
129#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
130 FTIM2_NOR_TCH(0x0) | \
131 FTIM2_NOR_TWP(0x1))
132#define CONFIG_SYS_NOR_FTIM3 0x04000000
133#define CONFIG_SYS_IFC_CCR 0x01000000
134
Prabhakar Kushwaha962b2de2014-07-16 09:21:12 +0530135#ifndef CONFIG_SYS_NO_FLASH
136#define CONFIG_FLASH_CFI_DRIVER
137#define CONFIG_SYS_FLASH_CFI
138#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
139#define CONFIG_SYS_FLASH_QUIET_TEST
140#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
141
142#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
143#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
144#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
145#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
146
147#define CONFIG_SYS_FLASH_EMPTY_INFO
148#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
149#endif
150
151#define CONFIG_NAND_FSL_IFC
152#define CONFIG_SYS_NAND_MAX_ECCPOS 256
153#define CONFIG_SYS_NAND_MAX_OOBFREE 2
154#define CONFIG_SYS_NAND_BASE 0x520000000
155#define CONFIG_SYS_NAND_BASE_PHYS 0x20000000
156
157#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
158#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
159 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
160 | CSPR_MSEL_NAND /* MSEL = NAND */ \
161 | CSPR_V)
162#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
163
164#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
165 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
166 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
167 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
168 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
169 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
170 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
171
172#define CONFIG_SYS_NAND_ONFI_DETECTION
173
174/* ONFI NAND Flash mode0 Timing Params */
175#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
176 FTIM0_NAND_TWP(0x18) | \
177 FTIM0_NAND_TWCHT(0x07) | \
178 FTIM0_NAND_TWH(0x0a))
179#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
180 FTIM1_NAND_TWBE(0x39) | \
181 FTIM1_NAND_TRR(0x0e) | \
182 FTIM1_NAND_TRP(0x18))
183#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
184 FTIM2_NAND_TREH(0x0a) | \
185 FTIM2_NAND_TWHRE(0x1e))
186#define CONFIG_SYS_NAND_FTIM3 0x0
187
188#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
189#define CONFIG_SYS_MAX_NAND_DEVICE 1
190#define CONFIG_MTD_NAND_VERIFY_WRITE
191#define CONFIG_CMD_NAND
192
193#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
194
York Sun7b08d212014-06-23 15:15:56 -0700195#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
196#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
197#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
198#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
199#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
200#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
201#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
202#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
203#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
204
205/* MC firmware */
206#define CONFIG_FSL_MC_ENET
207#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
208#define CONFIG_SYS_LS_MC_FW_IN_NOR
209#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL
210/* TODO Actual FW length needs to be determined at runtime from FW header */
211#define CONFIG_SYS_LS_MC_FW_LENGTH (4U * 1024 * 1024)
212#define CONFIG_SYS_LS_MC_DPL_IN_NOR
213#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
214/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
215#define CONFIG_SYS_LS_MC_DPL_LENGTH 4096
216#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000
217
218/* Carve the MC private DRAM block from the end of DRAM */
219#ifdef CONFIG_FSL_MC_ENET
220#define CONFIG_SYS_MEM_TOP_HIDE mc_get_dram_block_size()
221#endif
222
223/* Command line configuration */
224#define CONFIG_CMD_CACHE
225#define CONFIG_CMD_BDI
226#define CONFIG_CMD_DHCP
227#define CONFIG_CMD_ENV
228#define CONFIG_CMD_FLASH
229#define CONFIG_CMD_IMI
230#define CONFIG_CMD_MEMORY
231#define CONFIG_CMD_MII
232#define CONFIG_CMD_NET
233#define CONFIG_CMD_PING
234#define CONFIG_CMD_SAVEENV
235#define CONFIG_CMD_RUN
236#define CONFIG_CMD_BOOTD
237#define CONFIG_CMD_ECHO
238#define CONFIG_CMD_SOURCE
239#define CONFIG_CMD_FAT
240#define CONFIG_DOS_PARTITION
241
242/* Miscellaneous configurable options */
243#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
York Sun290a83a2014-09-08 12:20:01 -0700244#define CONFIG_ARCH_EARLY_INIT_R
York Sun7b08d212014-06-23 15:15:56 -0700245
246/* Physical Memory Map */
247/* fixme: these need to be checked against the board */
248#define CONFIG_CHIP_SELECTS_PER_CTRL 4
York Sun0080f222015-01-06 13:18:54 -0800249#define CONFIG_SYS_CLK_FREQ 100000000
250#define CONFIG_DDR_CLK_FREQ 133333333
York Sun7b08d212014-06-23 15:15:56 -0700251
252
York Sunc7a0e302014-08-13 10:21:05 -0700253#define CONFIG_NR_DRAM_BANKS 3
York Sun7b08d212014-06-23 15:15:56 -0700254
York Sun7b08d212014-06-23 15:15:56 -0700255#define CONFIG_HWCONFIG
256#define HWCONFIG_BUFFER_SIZE 128
257
258#define CONFIG_DISPLAY_CPUINFO
259
260/* Initial environment variables */
261#define CONFIG_EXTRA_ENV_SETTINGS \
262 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
263 "loadaddr=0x80100000\0" \
264 "kernel_addr=0x100000\0" \
265 "ramdisk_addr=0x800000\0" \
266 "ramdisk_size=0x2000000\0" \
267 "fdt_high=0xffffffffffffffff\0" \
268 "initrd_high=0xffffffffffffffff\0" \
269 "kernel_start=0x581200000\0" \
Stuart Yoderd4792d82015-01-06 13:18:57 -0800270 "kernel_load=0xa0000000\0" \
York Sun7b08d212014-06-23 15:15:56 -0700271 "kernel_size=0x1000000\0" \
272 "console=ttyAMA0,38400n8\0"
273
Arnab Basu77d31652015-01-06 13:18:56 -0800274#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
275 "earlycon=uart8250,mmio,0x21c0600,115200 " \
276 "default_hugepagesz=2m hugepagesz=2m " \
277 "hugepages=16"
York Sun7b08d212014-06-23 15:15:56 -0700278#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
279 "$kernel_size && bootm $kernel_load"
280#define CONFIG_BOOTDELAY 1
281
282/* Store environment at top of flash */
283#define CONFIG_ENV_IS_NOWHERE 1
284#define CONFIG_ENV_SIZE 0x1000
285
286/* Monitor Command Prompt */
287#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
288#define CONFIG_SYS_PROMPT "> "
289#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
290 sizeof(CONFIG_SYS_PROMPT) + 16)
291#define CONFIG_SYS_HUSH_PARSER
292#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
293#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
294#define CONFIG_SYS_LONGHELP
295#define CONFIG_CMDLINE_EDITING 1
296#define CONFIG_SYS_MAXARGS 64 /* max command args */
297
298#ifndef __ASSEMBLY__
299unsigned long mc_get_dram_block_size(void);
300#endif
301
302#endif /* __LS2_COMMON_H */