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git01.mediatek.com / filogic / uboot / 28a60327a657ec8cf3d17e010fde516c4d82961b / . / arch / arm / dts / s5pc100-pinctrl.dtsi
blob: 975386969e16ec3c0342da39e3e289fcf9fc4872 [file] [log] [blame]
Simon Glass5d6927a2014-10-20 19:48:33 -0600[diff] [blame]1/*
2 * U-Boot additions to enable a generic Exynos GPIO driver
3 *
4 * Copyright (c) 2014 Google, Inc
Simon Glass28a60322015-04-13 11:19:07 -0600[diff] [blame^]5 *
6 * SPDX-License-Identifier: GPL-2.0+
Simon Glass5d6927a2014-10-20 19:48:33 -0600[diff] [blame]7 */
8
9/ {
10 pinctrl@e0300000 {
11 gpa0: gpa0 {
12 gpio-controller;
13 #gpio-cells = <2>;
14 };
15
16 gpa1: gpa1 {
17 gpio-controller;
18 #gpio-cells = <2>;
19 };
20
21 gpb: gpb {
22 gpio-controller;
23 #gpio-cells = <2>;
24 };
25
26 gpc: gpc {
27 gpio-controller;
28 #gpio-cells = <2>;
29 };
30
31 gpd: gpd {
32 gpio-controller;
33 #gpio-cells = <2>;
34 };
35
36 gpe0: gpe0 {
37 gpio-controller;
38 #gpio-cells = <2>;
39 };
40
41 gpe1: gpe1 {
42 gpio-controller;
43 #gpio-cells = <2>;
44 };
45
46 gpf0: gpf0 {
47 gpio-controller;
48 #gpio-cells = <2>;
49 };
50
51 gpf1: gpf1 {
52 gpio-controller;
53 #gpio-cells = <2>;
54 };
55
56 gpf2: gpf2 {
57 gpio-controller;
58 #gpio-cells = <2>;
59 };
60
61 gpf3: gpf3 {
62 gpio-controller;
63 #gpio-cells = <2>;
64 };
65
66 gpg0: gpg0 {
67 gpio-controller;
68 #gpio-cells = <2>;
69 };
70
71 gpg1: gpg1 {
72 gpio-controller;
73 #gpio-cells = <2>;
74 };
75
76 gpg2: gpg2 {
77 gpio-controller;
78 #gpio-cells = <2>;
79 };
80
81 gpg3: gpg3 {
82 gpio-controller;
83 #gpio-cells = <2>;
84 };
85
86 gpi: gpi {
87 gpio-controller;
88 #gpio-cells = <2>;
89 };
90
91 gpj0: gpj0 {
92 gpio-controller;
93 #gpio-cells = <2>;
94 };
95
96 gpj1: gpj1 {
97 gpio-controller;
98 #gpio-cells = <2>;
99 };
100
101 gpj2: gpj2 {
102 gpio-controller;
103 #gpio-cells = <2>;
104 };
105
106 gpj3: gpj3 {
107 gpio-controller;
108 #gpio-cells = <2>;
109 };
110
111 gpj4: gpj4 {
112 gpio-controller;
113 #gpio-cells = <2>;
114 };
115
116 gpk0: gpk0 {
117 gpio-controller;
118 #gpio-cells = <2>;
119 };
120
121 gpk1: gpk1 {
122 gpio-controller;
123 #gpio-cells = <2>;
124 };
125
126 gpk2: gpk2 {
127 gpio-controller;
128 #gpio-cells = <2>;
129 };
130
131 gpk3: gpk3 {
132 gpio-controller;
133 #gpio-cells = <2>;
134 };
135
136 gpl0: gpl0 {
137 gpio-controller;
138 #gpio-cells = <2>;
139 };
140
141 gpl1: gpl1 {
142 gpio-controller;
143 #gpio-cells = <2>;
144 };
145
146 gpl2: gpl2 {
147 gpio-controller;
148 #gpio-cells = <2>;
149 };
150
151 gpl3: gpl3 {
152 gpio-controller;
153 #gpio-cells = <2>;
154 };
155
156 gpl4: gpl4 {
157 gpio-controller;
158 #gpio-cells = <2>;
159 };
160
161 gph0: gph0 {
162 gpio-controller;
163 #gpio-cells = <2>;
164 };
165
166 gph1: gph1 {
167 gpio-controller;
168 #gpio-cells = <2>;
169 };
170
171 gph2: gph2 {
172 gpio-controller;
173 #gpio-cells = <2>;
174 };
175
176 gph3: gph3 {
177 gpio-controller;
178 #gpio-cells = <2>;
179 };
180
181 };
182};