Marek Vasut | 0e8dcb7 | 2021-04-25 21:10:40 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 2 | /* |
| 3 | * R-Car Gen3 Clock Pulse Generator |
| 4 | * |
Marek Vasut | 0e8dcb7 | 2021-04-25 21:10:40 +0200 | [diff] [blame] | 5 | * Copyright (C) 2015-2018 Glider bvba |
| 6 | * Copyright (C) 2018 Renesas Electronics Corp. |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 7 | * |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ |
| 11 | #define __CLK_RENESAS_RCAR_GEN3_CPG_H__ |
| 12 | |
| 13 | enum rcar_gen3_clk_types { |
| 14 | CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, |
| 15 | CLK_TYPE_GEN3_PLL0, |
| 16 | CLK_TYPE_GEN3_PLL1, |
| 17 | CLK_TYPE_GEN3_PLL2, |
| 18 | CLK_TYPE_GEN3_PLL3, |
| 19 | CLK_TYPE_GEN3_PLL4, |
Hai Pham | 0985e0e | 2023-01-26 21:01:49 +0100 | [diff] [blame] | 20 | CLK_TYPE_GEN3_SDH, |
Hai Pham | 6811b57 | 2023-01-26 21:06:06 +0100 | [diff] [blame] | 21 | CLK_TYPE_R8A77970_SD0H, |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 22 | CLK_TYPE_GEN3_SD, |
Hai Pham | 6811b57 | 2023-01-26 21:06:06 +0100 | [diff] [blame] | 23 | CLK_TYPE_R8A77970_SD0, |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 24 | CLK_TYPE_GEN3_R, |
Marek Vasut | 7841483 | 2019-03-04 21:38:10 +0100 | [diff] [blame] | 25 | CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ |
| 26 | CLK_TYPE_GEN3_Z, |
Marek Vasut | e1418a0 | 2023-12-03 14:15:13 +0100 | [diff] [blame] | 27 | CLK_TYPE_GEN3_ZG, |
Marek Vasut | 7841483 | 2019-03-04 21:38:10 +0100 | [diff] [blame] | 28 | CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ |
| 29 | CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ |
| 30 | CLK_TYPE_GEN3_RPCSRC, |
Marek Vasut | d1ff7e0 | 2023-01-26 21:01:55 +0100 | [diff] [blame] | 31 | CLK_TYPE_GEN3_D3_RPCSRC, |
Marek Vasut | 0e8dcb7 | 2021-04-25 21:10:40 +0200 | [diff] [blame] | 32 | CLK_TYPE_GEN3_E3_RPCSRC, |
Marek Vasut | 7841483 | 2019-03-04 21:38:10 +0100 | [diff] [blame] | 33 | CLK_TYPE_GEN3_RPC, |
| 34 | CLK_TYPE_GEN3_RPCD2, |
Hai Pham | 86d59f3 | 2020-08-11 10:46:34 +0700 | [diff] [blame] | 35 | |
Marek Vasut | 569acef | 2023-01-26 21:01:56 +0100 | [diff] [blame] | 36 | CLK_TYPE_GEN4_MAIN, |
| 37 | CLK_TYPE_GEN4_PLL1, |
Marek Vasut | ba2c7d2 | 2023-02-28 22:34:38 +0100 | [diff] [blame] | 38 | CLK_TYPE_GEN4_PLL2, |
| 39 | CLK_TYPE_GEN4_PLL2X_3X, /* R8A779A0 only */ |
| 40 | CLK_TYPE_GEN4_PLL3, |
Marek Vasut | 569acef | 2023-01-26 21:01:56 +0100 | [diff] [blame] | 41 | CLK_TYPE_GEN4_PLL5, |
Marek Vasut | ba2c7d2 | 2023-02-28 22:34:38 +0100 | [diff] [blame] | 42 | CLK_TYPE_GEN4_PLL4, |
| 43 | CLK_TYPE_GEN4_PLL6, |
Hai Pham | 2802869 | 2024-01-28 16:52:01 +0100 | [diff] [blame^] | 44 | CLK_TYPE_GEN4_PLL7, |
Marek Vasut | ba2c7d2 | 2023-02-28 22:34:38 +0100 | [diff] [blame] | 45 | CLK_TYPE_GEN4_SDSRC, |
Marek Vasut | 569acef | 2023-01-26 21:01:56 +0100 | [diff] [blame] | 46 | CLK_TYPE_GEN4_SDH, |
| 47 | CLK_TYPE_GEN4_SD, |
| 48 | CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */ |
| 49 | CLK_TYPE_GEN4_Z, |
| 50 | CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */ |
| 51 | CLK_TYPE_GEN4_RPCSRC, |
| 52 | CLK_TYPE_GEN4_RPC, |
| 53 | CLK_TYPE_GEN4_RPCD2, |
Marek Vasut | 7841483 | 2019-03-04 21:38:10 +0100 | [diff] [blame] | 54 | |
| 55 | /* SoC specific definitions start here */ |
| 56 | CLK_TYPE_GEN3_SOC_BASE, |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 57 | }; |
| 58 | |
Hai Pham | 0985e0e | 2023-01-26 21:01:49 +0100 | [diff] [blame] | 59 | #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ |
| 60 | DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset) |
| 61 | |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 62 | #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ |
| 63 | DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) |
Marek Vasut | 7841483 | 2019-03-04 21:38:10 +0100 | [diff] [blame] | 64 | |
Marek Vasut | 7841483 | 2019-03-04 21:38:10 +0100 | [diff] [blame] | 65 | #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ |
| 66 | DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ |
| 67 | (_parent0) << 16 | (_parent1), \ |
| 68 | .div = (_div0) << 16 | (_div1), .offset = _md) |
| 69 | |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 70 | #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ |
| 71 | _div_clean) \ |
Marek Vasut | 7841483 | 2019-03-04 21:38:10 +0100 | [diff] [blame] | 72 | DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \ |
| 73 | _parent_clean, _div_clean) |
| 74 | |
| 75 | #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ |
| 76 | DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div) |
| 77 | |
| 78 | #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ |
| 79 | DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ |
| 80 | (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) |
| 81 | |
Adam Ford | 06c4f9b | 2020-06-30 09:30:08 -0500 | [diff] [blame] | 82 | #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ |
| 83 | DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 84 | |
Marek Vasut | d1ff7e0 | 2023-01-26 21:01:55 +0100 | [diff] [blame] | 85 | #define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \ |
| 86 | DEF_BASE(_name, _id, CLK_TYPE_GEN3_D3_RPCSRC, \ |
| 87 | (_parent0) << 16 | (_parent1), .div = 5) |
| 88 | |
Marek Vasut | 0e8dcb7 | 2021-04-25 21:10:40 +0200 | [diff] [blame] | 89 | #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ |
| 90 | DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \ |
| 91 | (_parent0) << 16 | (_parent1), .div = 8) |
| 92 | |
Marek Vasut | 569acef | 2023-01-26 21:01:56 +0100 | [diff] [blame] | 93 | #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ |
| 94 | DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset) |
| 95 | |
| 96 | #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ |
| 97 | DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset) |
| 98 | |
| 99 | #define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ |
| 100 | DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \ |
| 101 | (_parent0) << 16 | (_parent1), \ |
| 102 | .div = (_div0) << 16 | (_div1), .offset = _md) |
| 103 | |
| 104 | #define DEF_GEN4_OSC(_name, _id, _parent, _div) \ |
| 105 | DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div) |
| 106 | |
| 107 | #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ |
| 108 | DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) |
| 109 | |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 110 | struct rcar_gen3_cpg_pll_config { |
| 111 | u8 extal_div; |
| 112 | u8 pll1_mult; |
| 113 | u8 pll1_div; |
| 114 | u8 pll3_mult; |
| 115 | u8 pll3_div; |
Marek Vasut | 7841483 | 2019-03-04 21:38:10 +0100 | [diff] [blame] | 116 | u8 osc_prediv; |
Marek Vasut | ba2c7d2 | 2023-02-28 22:34:38 +0100 | [diff] [blame] | 117 | }; |
| 118 | |
| 119 | struct rcar_gen4_cpg_pll_config { |
| 120 | u8 extal_div; |
| 121 | u8 pll1_mult; |
| 122 | u8 pll1_div; |
| 123 | u8 pll2_mult; |
| 124 | u8 pll2_div; |
| 125 | u8 pll3_mult; |
| 126 | u8 pll3_div; |
| 127 | u8 pll4_mult; |
| 128 | u8 pll4_div; |
Marek Vasut | 0fbb8a7 | 2021-04-27 19:52:53 +0200 | [diff] [blame] | 129 | u8 pll5_mult; |
| 130 | u8 pll5_div; |
Marek Vasut | ba2c7d2 | 2023-02-28 22:34:38 +0100 | [diff] [blame] | 131 | u8 pll6_mult; |
| 132 | u8 pll6_div; |
| 133 | u8 osc_prediv; |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 134 | }; |
| 135 | |
Marek Vasut | 814217e | 2021-04-25 21:53:05 +0200 | [diff] [blame] | 136 | #define CPG_RST_MODEMR 0x060 |
Marek Vasut | ba2c7d2 | 2023-02-28 22:34:38 +0100 | [diff] [blame] | 137 | #define CPG_RST_MODEMR0 0x000 |
Marek Vasut | 814217e | 2021-04-25 21:53:05 +0200 | [diff] [blame] | 138 | |
Hai Pham | 4dae076 | 2023-01-29 02:50:22 +0100 | [diff] [blame] | 139 | #define CPG_SDCKCR_STPnHCK BIT(9) |
| 140 | #define CPG_SDCKCR_STPnCK BIT(8) |
| 141 | #define CPG_SDCKCR_SRCFC_MASK GENMASK(4, 2) |
| 142 | #define CPG_SDCKCR_FC_MASK GENMASK(1, 0) |
Hai Pham | 6811b57 | 2023-01-26 21:06:06 +0100 | [diff] [blame] | 143 | /* V3M specifics */ |
| 144 | #define CPG_SDCKCR_SDHFC_MASK GENMASK(11, 8) |
| 145 | #define CPG_SDCKCR_SD0FC_MASK GENMASK(7, 4) |
Hai Pham | 4dae076 | 2023-01-29 02:50:22 +0100 | [diff] [blame] | 146 | |
Marek Vasut | 7841483 | 2019-03-04 21:38:10 +0100 | [diff] [blame] | 147 | #define CPG_RPCCKCR 0x238 |
Hai Pham | e83700a | 2023-01-26 21:06:03 +0100 | [diff] [blame] | 148 | #define CPG_RPCCKCR_DIV_POST_MASK GENMASK(4, 3) |
| 149 | #define CPG_RPCCKCR_DIV_PRE_MASK GENMASK(2, 0) |
| 150 | |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 151 | #define CPG_RCKCR 0x240 |
| 152 | |
| 153 | struct gen3_clk_priv { |
| 154 | void __iomem *base; |
| 155 | struct cpg_mssr_info *info; |
| 156 | struct clk clk_extal; |
| 157 | struct clk clk_extalr; |
Marek Vasut | ea8505e | 2023-02-28 07:25:11 +0100 | [diff] [blame] | 158 | u32 cpg_mode; |
Marek Vasut | ba2c7d2 | 2023-02-28 22:34:38 +0100 | [diff] [blame] | 159 | union { |
| 160 | const struct rcar_gen3_cpg_pll_config *gen3_cpg_pll_config; |
| 161 | const struct rcar_gen4_cpg_pll_config *gen4_cpg_pll_config; |
| 162 | }; |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 163 | }; |
| 164 | |
Marek Vasut | f6b3202 | 2023-01-26 21:02:03 +0100 | [diff] [blame] | 165 | int gen3_cpg_bind(struct udevice *parent); |
Marek Vasut | 7ef12c2 | 2018-01-08 17:09:45 +0100 | [diff] [blame] | 166 | |
| 167 | extern const struct clk_ops gen3_clk_ops; |
| 168 | |
| 169 | #endif |