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git01.mediatek.com / filogic / uboot / 27e3891cdd24b9fa98ca6d571b0a2ea8f411830f / . / arch / arm / mach-socfpga / wrap_sdram_config.c
blob: 8fb808a3340e6d0a3ffe3f58ac6b6c45fd9a6069 [file] [log] [blame]
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]1/*
2 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <errno.h>
9#include <asm/arch/sdram.h>
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]10
Marek Vasut372f70d2015-08-10 21:21:07 +0200[diff] [blame]11/* Board-specific header. */
12#include <qts/sdram_config.h>
Marek Vasut3384e742015-08-02 17:15:19 +0200[diff] [blame]13
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]14static const struct socfpga_sdram_config sdram_config = {
15 .ctrl_cfg =
16 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
17 SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
18 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
19 SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
20 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
21 SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
22 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
23 SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
24 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
25 SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
26 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
27 SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
28 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
29 SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
30 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
31 SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
32 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
33 SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
34 .dram_timing1 =
35 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
36 SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
37 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
38 SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
39 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
40 SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
41 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
42 SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
43 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
44 SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
45 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
46 SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
47 .dram_timing2 =
48 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
49 SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
50 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
51 SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
52 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
53 SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
54 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
55 SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
56 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
57 SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
58 .dram_timing3 =
59 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
60 SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
61 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
62 SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
63 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
64 SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
65 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
66 SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
67 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
68 SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
69 .dram_timing4 =
70 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
71 SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
72 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
73 SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
74 .lowpwr_timing =
75 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
76 SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
77 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
78 SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
79 .dram_odt =
80 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
81 SDR_CTRLGRP_DRAMODT_READ_LSB) |
82 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
83 SDR_CTRLGRP_DRAMODT_WRITE_LSB),
Chin Liang See3ea59512016-09-21 10:25:56 +0800[diff] [blame]84 .extratime1 =
85 (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
86 SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
87 (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
88 SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
89(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
90 SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]91 .dram_addrw =
92 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
93 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
94 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
95 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
96 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
97 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
98 ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
99 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
100 .dram_if_width =
101 (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
102 SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
103 .dram_dev_width =
104 (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
105 SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
106 .dram_intr =
107 (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
108 SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
109 .lowpwr_eq =
110 (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
111 SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
112 .static_cfg =
113 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
114 SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
115 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
116 SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
117 .ctrl_width =
118 (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
119 SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
120 .cport_width =
121 (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
122 SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
123 .cport_wmap =
124 (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
125 SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
126 .cport_rmap =
127 (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
128 SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
129 .rfifo_cmap =
130 (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
131 SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
132 .wfifo_cmap =
133 (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
134 SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
135 .cport_rdwr =
136 (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
137 SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
138 .port_cfg =
139 (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
140 SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
141 .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
142 .fifo_cfg =
143 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
144 SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
145 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
146 SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
147 .mp_priority =
148 (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
149 SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
150 .mp_weight0 =
151 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
152 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
153 .mp_weight1 =
154 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
155 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
156 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
157 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
158 .mp_weight2 =
159 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
160 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
161 .mp_weight3 =
162 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
163 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
164 .mp_pacing0 =
165 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
166 SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
167 .mp_pacing1 =
168 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
169 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
170 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
171 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
172 .mp_pacing2 =
173 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
174 SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
175 .mp_pacing3 =
176 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
177 SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
178 .mp_threshold0 =
179 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
180 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
181 .mp_threshold1 =
182 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
183 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
184 .mp_threshold2 =
185 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
186 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
187 .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
188};
189
Marek Vasut39b620e2015-08-02 18:12:08 +0200[diff] [blame]190static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
191 .activate_0_and_1 = RW_MGR_ACTIVATE_0_AND_1,
192 .activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1,
193 .activate_0_and_1_wait2 = RW_MGR_ACTIVATE_0_AND_1_WAIT2,
194 .activate_1 = RW_MGR_ACTIVATE_1,
195 .clear_dqs_enable = RW_MGR_CLEAR_DQS_ENABLE,
196 .guaranteed_read = RW_MGR_GUARANTEED_READ,
197 .guaranteed_read_cont = RW_MGR_GUARANTEED_READ_CONT,
198 .guaranteed_write = RW_MGR_GUARANTEED_WRITE,
199 .guaranteed_write_wait0 = RW_MGR_GUARANTEED_WRITE_WAIT0,
200 .guaranteed_write_wait1 = RW_MGR_GUARANTEED_WRITE_WAIT1,
201 .guaranteed_write_wait2 = RW_MGR_GUARANTEED_WRITE_WAIT2,
202 .guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3,
203 .idle = RW_MGR_IDLE,
204 .idle_loop1 = RW_MGR_IDLE_LOOP1,
205 .idle_loop2 = RW_MGR_IDLE_LOOP2,
206 .init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
207 .init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0,
208 .lfsr_wr_rd_bank_0 = RW_MGR_LFSR_WR_RD_BANK_0,
209 .lfsr_wr_rd_bank_0_data = RW_MGR_LFSR_WR_RD_BANK_0_DATA,
210 .lfsr_wr_rd_bank_0_dqs = RW_MGR_LFSR_WR_RD_BANK_0_DQS,
211 .lfsr_wr_rd_bank_0_nop = RW_MGR_LFSR_WR_RD_BANK_0_NOP,
212 .lfsr_wr_rd_bank_0_wait = RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
213 .lfsr_wr_rd_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
214 .lfsr_wr_rd_dm_bank_0 = RW_MGR_LFSR_WR_RD_DM_BANK_0,
215 .lfsr_wr_rd_dm_bank_0_data = RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
216 .lfsr_wr_rd_dm_bank_0_dqs = RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
217 .lfsr_wr_rd_dm_bank_0_nop = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
218 .lfsr_wr_rd_dm_bank_0_wait = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
219 .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
220 .mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET,
221 .mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR,
222 .mrs0_user = RW_MGR_MRS0_USER,
223 .mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR,
224 .mrs1 = RW_MGR_MRS1,
225 .mrs1_mirr = RW_MGR_MRS1_MIRR,
226 .mrs2 = RW_MGR_MRS2,
227 .mrs2_mirr = RW_MGR_MRS2_MIRR,
228 .mrs3 = RW_MGR_MRS3,
229 .mrs3_mirr = RW_MGR_MRS3_MIRR,
230 .precharge_all = RW_MGR_PRECHARGE_ALL,
231 .read_b2b = RW_MGR_READ_B2B,
232 .read_b2b_wait1 = RW_MGR_READ_B2B_WAIT1,
233 .read_b2b_wait2 = RW_MGR_READ_B2B_WAIT2,
234 .refresh_all = RW_MGR_REFRESH_ALL,
235 .rreturn = RW_MGR_RETURN,
236 .sgle_read = RW_MGR_SGLE_READ,
237 .zqcl = RW_MGR_ZQCL,
238
239 .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
240 .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING,
241 .mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH,
242 .mem_data_width = RW_MGR_MEM_DATA_WIDTH,
243 .mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS,
244 .mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS,
245 .mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH,
246 .mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
247 .mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
248 .mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS,
249 .mem_virtual_groups_per_read_dqs =
250 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
251 .mem_virtual_groups_per_write_dqs =
252 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
253};
254
Marek Vasut3bf92042015-08-02 19:00:23 +0200[diff] [blame]255struct socfpga_sdram_io_config io_config = {
256 .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP,
257 .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
258 .delay_per_opa_tap = IO_DELAY_PER_OPA_TAP,
259 .dll_chain_length = IO_DLL_CHAIN_LENGTH,
260 .dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX,
261 .dqs_en_delay_max = IO_DQS_EN_DELAY_MAX,
262 .dqs_en_delay_offset = IO_DQS_EN_DELAY_OFFSET,
263 .dqs_en_phase_max = IO_DQS_EN_PHASE_MAX,
264 .dqs_in_delay_max = IO_DQS_IN_DELAY_MAX,
265 .dqs_in_reserve = IO_DQS_IN_RESERVE,
266 .dqs_out_reserve = IO_DQS_OUT_RESERVE,
267 .io_in_delay_max = IO_IO_IN_DELAY_MAX,
268 .io_out1_delay_max = IO_IO_OUT1_DELAY_MAX,
269 .io_out2_delay_max = IO_IO_OUT2_DELAY_MAX,
270 .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
271};
272
Marek Vasutf00a6ea2015-08-02 19:18:47 +0200[diff] [blame]273struct socfpga_sdram_misc_config misc_config = {
274 .afi_rate_ratio = AFI_RATE_RATIO,
275 .calib_lfifo_offset = CALIB_LFIFO_OFFSET,
276 .calib_vfifo_offset = CALIB_VFIFO_OFFSET,
277 .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
278 .max_latency_count_width = MAX_LATENCY_COUNT_WIDTH,
279 .read_valid_fifo_size = READ_VALID_FIFO_SIZE,
280 .reg_file_init_seq_signature = REG_FILE_INIT_SEQ_SIGNATURE,
281 .tinit_cntr0_val = TINIT_CNTR0_VAL,
282 .tinit_cntr1_val = TINIT_CNTR1_VAL,
283 .tinit_cntr2_val = TINIT_CNTR2_VAL,
284 .treset_cntr0_val = TRESET_CNTR0_VAL,
285 .treset_cntr1_val = TRESET_CNTR1_VAL,
286 .treset_cntr2_val = TRESET_CNTR2_VAL,
287};
288
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]289const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
290{
291 return &sdram_config;
292}
Marek Vasut3384e742015-08-02 17:15:19 +0200[diff] [blame]293
294void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem)
295{
296 *init = ac_rom_init;
297 *nelem = ARRAY_SIZE(ac_rom_init);
298}
299
300void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
301{
302 *init = inst_rom_init;
303 *nelem = ARRAY_SIZE(inst_rom_init);
304}
Marek Vasut39b620e2015-08-02 18:12:08 +0200[diff] [blame]305
306const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
307{
308 return &rw_mgr_config;
309}
Marek Vasut3bf92042015-08-02 19:00:23 +0200[diff] [blame]310
311const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
312{
313 return &io_config;
314}
Marek Vasutf00a6ea2015-08-02 19:18:47 +0200[diff] [blame]315
316const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void)
317{
318 return &misc_config;
319}