blob: e4d0967c14c2f32b7e5068dd5af17c25380b8a82 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +09002/*
3 * Copyright (C) 2007,2008
4 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +09005 */
6
7#include <common.h>
8#include <ide.h>
Simon Glassa7b51302019-11-14 12:57:46 -07009#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060010#include <net.h>
Nobuhiro Iwamatsu4b366be2008-09-11 17:28:18 +090011#include <netdev.h>
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090012#include <asm/processor.h>
Nobuhiro Iwamatsu51fe0b22008-06-17 16:27:44 +090013#include <asm/io.h>
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090014
15int checkboard(void)
16{
17 puts("BOARD: Renesas Solutions R2D Plus\n");
18 return 0;
19}
20
21int board_init(void)
22{
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090023 return 0;
24}
25
26int board_late_init(void)
27{
28 return 0;
29}
30
Nobuhiro Iwamatsu51fe0b22008-06-17 16:27:44 +090031#define FPGA_BASE 0xA4000000
32#define FPGA_CFCTL (FPGA_BASE + 0x04)
33#define CFCTL_EN (0x432)
34#define FPGA_CFPOW (FPGA_BASE + 0x06)
35#define CFPOW_ON (0x02)
36#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
37#define CFCDINTCLR_EN (0x01)
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090038
Nobuhiro Iwamatsu51fe0b22008-06-17 16:27:44 +090039void ide_set_reset(int idereset)
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090040{
41 /* if reset = 1 IDE reset will be asserted */
Nobuhiro Iwamatsu51fe0b22008-06-17 16:27:44 +090042 if (idereset) {
43 outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */
44 outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
45 outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090046 }
47}
48
Ben Warren65b86232008-08-31 21:41:08 -070049int board_eth_init(bd_t *bis)
50{
51 return pci_eth_init(bis);
52}