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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +02002/*
3 * (C) Copyright 2017 Linaro
4 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +02005 */
6
Simon Glassfb6f4822020-02-03 07:36:17 -07007#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -07008#include <cpu_func.h>
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +02009#include <dm.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -070010#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060011#include <asm/cache.h>
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +020012#include <asm/io.h>
13#include <dm/platform_data/serial_pl01x.h>
14#include <asm/arch/hi3798cv200.h>
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +020015#include <asm/armv8/mmu.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19static struct mm_region poplar_mem_map[] = {
20 {
21 .virt = 0x0UL,
22 .phys = 0x0UL,
23 .size = 0x80000000UL,
24 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
25 PTE_BLOCK_INNER_SHARE
26 }, {
27 .virt = 0x80000000UL,
28 .phys = 0x80000000UL,
29 .size = 0x80000000UL,
30 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
31 PTE_BLOCK_NON_SHARE |
32 PTE_BLOCK_PXN | PTE_BLOCK_UXN
33 }, {
34 0,
35 }
36};
37
38struct mm_region *mem_map = poplar_mem_map;
39
Shawn Guo9bbb50d2018-12-12 15:24:44 +080040#if !CONFIG_IS_ENABLED(OF_CONTROL)
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +020041static const struct pl01x_serial_platdata serial_platdata = {
42 .base = REG_BASE_UART0,
43 .type = TYPE_PL010,
44 .clock = 75000000,
45};
46
47U_BOOT_DEVICE(poplar_serial) = {
48 .name = "serial_pl01x",
49 .platdata = &serial_platdata,
50};
Shawn Guo9bbb50d2018-12-12 15:24:44 +080051#endif
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +020052
53int checkboard(void)
54{
55 puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
56
57 return 0;
58}
59
60void reset_cpu(ulong addr)
61{
62 psci_system_reset();
63}
64
65int dram_init(void)
66{
67 gd->ram_size = get_ram_size(NULL, 0x80000000);
68
69 return 0;
70}
71
72/*
73 * Some linux kernel versions don't use memory before its load address, so to
74 * be generic we just pretend it isn't there. In previous uboot versions we
75 * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
76 * could persist in memory and be left alone by the kernel.
77 *
78 * That led to a problem when mapping memory in older kernels. That PSCI code
79 * now lies in memory below the kernel load offset; it therefore won't be
80 * touched by the kernel, and by not specially reserving it we avoid the mapping
81 * problem as well.
82 *
83 */
84#define KERNEL_TEXT_OFFSET 0x00080000
85
86int dram_init_banksize(void)
87{
88 gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
89 gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
90
91 return 0;
92}
93
94static void usb2_phy_config(void)
95{
96 const u32 config[] = {
97 /* close EOP pre-emphasis. open data pre-emphasis */
98 0xa1001c,
99 /* Rcomp = 150mW, increase DC level */
100 0xa00607,
101 /* keep Rcomp working */
102 0xa10700,
103 /* Icomp = 212mW, increase current drive */
104 0xa00aab,
105 /* EMI fix: rx_active not stay 1 when error packets received */
106 0xa11140,
107 /* Comp mode select */
108 0xa11041,
109 /* adjust eye diagram */
110 0xa0098c,
111 /* adjust eye diagram */
112 0xa10a0a,
113 };
114 int i;
115
116 for (i = 0; i < ARRAY_SIZE(config); i++) {
117 writel(config[i], PERI_CTRL_USB0);
118 clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
119 udelay(20);
120 }
121}
122
123static void usb2_phy_init(void)
124{
125 /* reset usb2 controller bus/utmi/roothub */
126 setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
127 USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
128 udelay(200);
129
130 /* reset usb2 phy por/utmi */
131 setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
132 udelay(200);
133
134 /* open usb2 ref clk */
135 setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
136 udelay(300);
137
138 /* cancel usb2 power on reset */
139 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
140 udelay(500);
141
142 usb2_phy_config();
143
144 /* cancel usb2 port reset, wait comp circuit stable */
145 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
146 mdelay(10);
147
148 /* open usb2 controller clk */
149 setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
150 USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
151 USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
152 udelay(200);
153
154 /* cancel usb2 control reset */
155 clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
156 USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
157 udelay(200);
158}
159
Shawn Guo0f56fde2018-12-18 17:52:06 +0800160#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
Simon Glass0af6e2d2019-08-01 09:46:52 -0600161#include <env.h>
Shawn Guo0f56fde2018-12-18 17:52:06 +0800162#include <usb.h>
163#include <usb/dwc2_udc.h>
164#include <g_dnl.h>
165
166static struct dwc2_plat_otg_data poplar_otg_data = {
167 .regs_otg = HIOTG_BASE_ADDR
168};
169
170static void set_usb_to_device(void)
171{
172 setbits_le32(PERI_CTRL_USB3, USB2_2P_CHIPID);
173}
174
175int board_usb_init(int index, enum usb_init_type init)
176{
177 set_usb_to_device();
178 return dwc2_udc_probe(&poplar_otg_data);
179}
180
181int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
182{
183 if (!env_get("serial#"))
184 g_dnl_set_serialnumber("0123456789POPLAR");
185 return 0;
186}
187#endif
188
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +0200189int board_init(void)
190{
191 usb2_phy_init();
192
193 return 0;
194}
195