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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +02002/*
3 * (C) Copyright 2017 Linaro
4 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +02005 */
6
Simon Glassafb02152019-12-28 10:45:01 -07007#include <cpu_func.h>
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +02008#include <dm.h>
9#include <common.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -070010#include <init.h>
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +020011#include <asm/io.h>
12#include <dm/platform_data/serial_pl01x.h>
13#include <asm/arch/hi3798cv200.h>
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +020014#include <asm/armv8/mmu.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18static struct mm_region poplar_mem_map[] = {
19 {
20 .virt = 0x0UL,
21 .phys = 0x0UL,
22 .size = 0x80000000UL,
23 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
24 PTE_BLOCK_INNER_SHARE
25 }, {
26 .virt = 0x80000000UL,
27 .phys = 0x80000000UL,
28 .size = 0x80000000UL,
29 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
30 PTE_BLOCK_NON_SHARE |
31 PTE_BLOCK_PXN | PTE_BLOCK_UXN
32 }, {
33 0,
34 }
35};
36
37struct mm_region *mem_map = poplar_mem_map;
38
Shawn Guo9bbb50d2018-12-12 15:24:44 +080039#if !CONFIG_IS_ENABLED(OF_CONTROL)
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +020040static const struct pl01x_serial_platdata serial_platdata = {
41 .base = REG_BASE_UART0,
42 .type = TYPE_PL010,
43 .clock = 75000000,
44};
45
46U_BOOT_DEVICE(poplar_serial) = {
47 .name = "serial_pl01x",
48 .platdata = &serial_platdata,
49};
Shawn Guo9bbb50d2018-12-12 15:24:44 +080050#endif
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +020051
52int checkboard(void)
53{
54 puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
55
56 return 0;
57}
58
59void reset_cpu(ulong addr)
60{
61 psci_system_reset();
62}
63
64int dram_init(void)
65{
66 gd->ram_size = get_ram_size(NULL, 0x80000000);
67
68 return 0;
69}
70
71/*
72 * Some linux kernel versions don't use memory before its load address, so to
73 * be generic we just pretend it isn't there. In previous uboot versions we
74 * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
75 * could persist in memory and be left alone by the kernel.
76 *
77 * That led to a problem when mapping memory in older kernels. That PSCI code
78 * now lies in memory below the kernel load offset; it therefore won't be
79 * touched by the kernel, and by not specially reserving it we avoid the mapping
80 * problem as well.
81 *
82 */
83#define KERNEL_TEXT_OFFSET 0x00080000
84
85int dram_init_banksize(void)
86{
87 gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
88 gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
89
90 return 0;
91}
92
93static void usb2_phy_config(void)
94{
95 const u32 config[] = {
96 /* close EOP pre-emphasis. open data pre-emphasis */
97 0xa1001c,
98 /* Rcomp = 150mW, increase DC level */
99 0xa00607,
100 /* keep Rcomp working */
101 0xa10700,
102 /* Icomp = 212mW, increase current drive */
103 0xa00aab,
104 /* EMI fix: rx_active not stay 1 when error packets received */
105 0xa11140,
106 /* Comp mode select */
107 0xa11041,
108 /* adjust eye diagram */
109 0xa0098c,
110 /* adjust eye diagram */
111 0xa10a0a,
112 };
113 int i;
114
115 for (i = 0; i < ARRAY_SIZE(config); i++) {
116 writel(config[i], PERI_CTRL_USB0);
117 clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
118 udelay(20);
119 }
120}
121
122static void usb2_phy_init(void)
123{
124 /* reset usb2 controller bus/utmi/roothub */
125 setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
126 USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
127 udelay(200);
128
129 /* reset usb2 phy por/utmi */
130 setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
131 udelay(200);
132
133 /* open usb2 ref clk */
134 setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
135 udelay(300);
136
137 /* cancel usb2 power on reset */
138 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
139 udelay(500);
140
141 usb2_phy_config();
142
143 /* cancel usb2 port reset, wait comp circuit stable */
144 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
145 mdelay(10);
146
147 /* open usb2 controller clk */
148 setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
149 USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
150 USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
151 udelay(200);
152
153 /* cancel usb2 control reset */
154 clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
155 USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
156 udelay(200);
157}
158
Shawn Guo0f56fde2018-12-18 17:52:06 +0800159#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
Simon Glass0af6e2d2019-08-01 09:46:52 -0600160#include <env.h>
Shawn Guo0f56fde2018-12-18 17:52:06 +0800161#include <usb.h>
162#include <usb/dwc2_udc.h>
163#include <g_dnl.h>
164
165static struct dwc2_plat_otg_data poplar_otg_data = {
166 .regs_otg = HIOTG_BASE_ADDR
167};
168
169static void set_usb_to_device(void)
170{
171 setbits_le32(PERI_CTRL_USB3, USB2_2P_CHIPID);
172}
173
174int board_usb_init(int index, enum usb_init_type init)
175{
176 set_usb_to_device();
177 return dwc2_udc_probe(&poplar_otg_data);
178}
179
180int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
181{
182 if (!env_get("serial#"))
183 g_dnl_set_serialnumber("0123456789POPLAR");
184 return 0;
185}
186#endif
187
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +0200188int board_init(void)
189{
190 usb2_phy_init();
191
192 return 0;
193}
194