blob: bd052b903d381075ce06997a565c92103b69e40c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ilya Yanok89847ef2010-07-07 20:16:13 +04002/*
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
Ilya Yanok89847ef2010-07-07 20:16:13 +04005 */
6
7#include <common.h>
8#include <hwconfig.h>
9#include <i2c.h>
Simon Glass18afe102019-11-14 12:57:47 -070010#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060011#include <net.h>
Ira W. Snyder429a1f92012-09-12 14:17:32 -070012#include <spi.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090013#include <linux/libfdt.h>
Ilya Yanok89847ef2010-07-07 20:16:13 +040014#include <fdt_support.h>
15#include <pci.h>
16#include <mpc83xx.h>
17#include <vsc7385.h>
18#include <netdev.h>
Ira W. Snyder0377b562012-09-12 14:17:35 -070019#include <fsl_esdhc.h>
Ilya Yanok89847ef2010-07-07 20:16:13 +040020#include <asm/io.h>
21#include <asm/fsl_serdes.h>
22#include <asm/fsl_mpc83xx_serdes.h>
23
Ira W. Snyder429a1f92012-09-12 14:17:32 -070024/*
25 * The following are used to control the SPI chip selects for the SPI command.
26 */
27#ifdef CONFIG_MPC8XXX_SPI
28
29#define SPI_CS_MASK 0x00400000
30
31int spi_cs_is_valid(unsigned int bus, unsigned int cs)
32{
33 return bus == 0 && cs == 0;
34}
35
36void spi_cs_activate(struct spi_slave *slave)
37{
38 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
39
40 /* active low */
41 clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
42}
43
44void spi_cs_deactivate(struct spi_slave *slave)
45{
46 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
47
48 /* inactive high */
49 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
50}
51#endif /* CONFIG_MPC8XXX_SPI */
52
Ira W. Snyder0377b562012-09-12 14:17:35 -070053#ifdef CONFIG_FSL_ESDHC
54int board_mmc_init(bd_t *bd)
55{
56 return fsl_esdhc_mmc_init(bd);
57}
58#endif
59
Ilya Yanok89847ef2010-07-07 20:16:13 +040060static u8 read_board_info(void)
61{
62 u8 val8;
63 i2c_set_bus_num(0);
64
65 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
66 return val8;
67 else
68 return 0;
69}
70
71int checkboard(void)
72{
73 static const char * const rev_str[] = {
74 "1.0",
75 "<reserved>",
76 "<reserved>",
77 "<reserved>",
78 "<unknown>",
79 };
80 u8 info;
81 int i;
82
83 info = read_board_info();
84 i = (!info) ? 4 : info & 0x03;
85
86 printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
87
88 return 0;
89}
90
91static struct pci_region pcie_regions_0[] = {
92 {
93 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
94 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
95 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
96 .flags = PCI_REGION_MEM,
97 },
98 {
99 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
100 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
101 .size = CONFIG_SYS_PCIE1_IO_SIZE,
102 .flags = PCI_REGION_IO,
103 },
104};
105
106void pci_init_board(void)
107{
108 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
109 sysconf83xx_t *sysconf = &immr->sysconf;
Ilya Yanok89847ef2010-07-07 20:16:13 +0400110 law83xx_t *pcie_law = sysconf->pcielaw;
111 struct pci_region *pcie_reg[] = { pcie_regions_0 };
112
113 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
114 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
115
Ilya Yanok89847ef2010-07-07 20:16:13 +0400116 /* Deassert the resets in the control register */
117 out_be32(&sysconf->pecr1, 0xE0008000);
118 udelay(2000);
119
120 /* Configure PCI Express Local Access Windows */
121 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
122 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
123
Peter Tysere2283322010-09-14 19:13:50 -0500124 mpc83xx_pcie_init(1, pcie_reg);
Ilya Yanok89847ef2010-07-07 20:16:13 +0400125}
126/*
127 * Miscellaneous late-boot configurations
128 *
129 * If a VSC7385 microcode image is present, then upload it.
130*/
131int misc_init_r(void)
132{
Ira W. Snyder429a1f92012-09-12 14:17:32 -0700133#ifdef CONFIG_MPC8XXX_SPI
134 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
135 sysconf83xx_t *sysconf = &immr->sysconf;
136
137 /*
138 * Set proper bits in SICRH to allow SPI on header J8
139 *
140 * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
141 * switch. The pinmux configuration does not have a fine enough
142 * granularity to support both simultaneously.
143 */
144 clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
145 puts("WARNING: SPI enabled, TSEC2 support is broken\n");
146
147 /* Set header J8 SPI chip select output, disabled */
148 setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
149 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
150#endif
151
Ilya Yanok89847ef2010-07-07 20:16:13 +0400152#ifdef CONFIG_VSC7385_IMAGE
153 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
154 CONFIG_VSC7385_IMAGE_SIZE)) {
155 puts("Failure uploading VSC7385 microcode.\n");
156 return 1;
157 }
158#endif
159
160 return 0;
161}
162#if defined(CONFIG_OF_BOARD_SETUP)
Simon Glass2aec3cc2014-10-23 18:58:47 -0600163int ft_board_setup(void *blob, bd_t *bd)
Ilya Yanok89847ef2010-07-07 20:16:13 +0400164{
165 ft_cpu_setup(blob, bd);
Sriram Dash9fd465c2016-09-16 17:12:15 +0530166 fsl_fdt_fixup_dr_usb(blob, bd);
Ira W. Snyder0377b562012-09-12 14:17:35 -0700167 fdt_fixup_esdhc(blob, bd);
Simon Glass2aec3cc2014-10-23 18:58:47 -0600168
169 return 0;
Ilya Yanok89847ef2010-07-07 20:16:13 +0400170}
171#endif
172
173int board_eth_init(bd_t *bis)
174{
175 int rv, num_if = 0;
176
177 /* Initialize TSECs first */
Ilya Yanokdbdc1052010-09-17 23:41:49 +0200178 rv = cpu_eth_init(bis);
179 if (rv >= 0)
Ilya Yanok89847ef2010-07-07 20:16:13 +0400180 num_if += rv;
181 else
182 printf("ERROR: failed to initialize TSECs.\n");
183
Ilya Yanokdbdc1052010-09-17 23:41:49 +0200184 rv = pci_eth_init(bis);
185 if (rv >= 0)
Ilya Yanok89847ef2010-07-07 20:16:13 +0400186 num_if += rv;
187 else
188 printf("ERROR: failed to initialize PCI Ethernet.\n");
189
190 return num_if;
191}