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git01.mediatek.com / filogic / uboot / 270a6f6f01ff6310791a03de0e1aa1891d510fae / . / arch / arm / mach-omap2 / lowlevel_init.S
blob: 8ce12c8e9ae9c561f6ed56798c65bb23f24cb814 [file] [log] [blame]
Minkyu Kangae6f0c62009-07-20 11:40:01 +0900[diff] [blame]1/*
Steve Sakoman1ad21582010-06-08 13:07:46 -0700[diff] [blame]2 * Board specific setup info
3 *
4 * (C) Copyright 2010
5 * Texas Instruments, <www.ti.com>
6 *
7 * Author :
8 * Aneesh V <aneesh@ti.com>
Minkyu Kangae6f0c62009-07-20 11:40:01 +0900[diff] [blame]9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]10 * SPDX-License-Identifier: GPL-2.0+
Minkyu Kangae6f0c62009-07-20 11:40:01 +0900[diff] [blame]11 */
12
Tom Rini8eb48ff2013-03-14 11:15:25 +0000[diff] [blame]13#include <config.h>
Sricharan9310ff72011-11-15 09:49:55 -0500[diff] [blame]14#include <asm/arch/omap.h>
SRICHARAN R3f30b0a2013-04-24 00:41:24 +0000[diff] [blame]15#include <asm/omap_common.h>
Joel A Fernandesb55759e2012-09-18 04:30:51 +0000[diff] [blame]16#include <asm/arch/spl.h>
Aneesh Vfd8798b2012-03-08 07:20:18 +0000[diff] [blame]17#include <linux/linkage.h>
Sricharan308fe922011-11-15 09:50:03 -0500[diff] [blame]18
Daniel Allred2cff3e72016-06-27 09:19:17 -0500[diff] [blame]19.arch_extension sec
20
Paul Kocialkowskid5b76242015-07-15 16:02:19 +0200[diff] [blame]21#ifdef CONFIG_SPL
Aneesh Vfd8798b2012-03-08 07:20:18 +0000[diff] [blame]22ENTRY(save_boot_params)
SRICHARAN R3f30b0a2013-04-24 00:41:24 +0000[diff] [blame]23 ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
Sricharan308fe922011-11-15 09:50:03 -0500[diff] [blame]24 str r0, [r1]
Simon Glass47197fe2015-02-07 10:47:28 -0700[diff] [blame]25 b save_boot_params_ret
Aneesh Vfd8798b2012-03-08 07:20:18 +0000[diff] [blame]26ENDPROC(save_boot_params)
Keerthy82d0e232016-09-14 10:43:33 +0530[diff] [blame]27
28#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE)
29ENTRY(switch_to_hypervisor)
30
31/*
32 * Switch to hypervisor mode
33 */
34 adr r0, save_sp
35 str sp, [r0]
36 adr r1, restore_from_hyp
37 ldr r0, =0x102
38 b omap_smc1
39restore_from_hyp:
40 adr r0, save_sp
41 ldr sp, [r0]
42 MRC p15, 4, R0, c1, c0, 0
43 ldr r1, =0X1004 @Set cache enable bits for hypervisor mode
44 orr r0, r0, r1
45 MCR p15, 4, R0, c1, c0, 0
46 b switch_to_hypervisor_ret
47save_sp:
48 .word 0x0
49ENDPROC(switch_to_hypervisor)
50#endif
Nishanth Menona816cc32015-03-09 17:12:05 -0500[diff] [blame]51#endif
Sricharan308fe922011-11-15 09:50:03 -0500[diff] [blame]52
Nishanth Menon19e1fdf2015-03-09 17:12:03 -0500[diff] [blame]53ENTRY(omap_smc1)
Daniel Allred2cff3e72016-06-27 09:19:17 -0500[diff] [blame]54 push {r4-r12, lr} @ save registers - ROM code may pollute
Aneesh Ve3405bd2011-06-16 23:30:52 +0000[diff] [blame]55 @ our registers
Daniel Allred2cff3e72016-06-27 09:19:17 -0500[diff] [blame]56 mov r12, r0 @ Service
57 mov r0, r1 @ Argument
Nishanth Menon19e1fdf2015-03-09 17:12:03 -0500[diff] [blame]58
Daniel Allred2cff3e72016-06-27 09:19:17 -0500[diff] [blame]59 dsb
60 dmb
61 smc 0 @ SMC #0 to enter monitor mode
62 @ call ROM Code API for the service requested
63 pop {r4-r12, pc}
Nishanth Menon19e1fdf2015-03-09 17:12:03 -0500[diff] [blame]64ENDPROC(omap_smc1)
Daniel Allred2cff3e72016-06-27 09:19:17 -0500[diff] [blame]65
66ENTRY(omap_smc_sec)
67 push {r4-r12, lr} @ save registers - ROM code may pollute
68 @ our registers
69 mov r6, #0xFF @ Indicate new Task call
70 mov r12, #0x00 @ Secure Service ID in R12
71
72 dsb
73 dmb
74 smc 0 @ SMC #0 to enter monitor mode
75
76 b omap_smc_sec_end @ exit at end of the service execution
77 nop
78
79 @ In case of IRQ happening in Secure, then ARM will branch here.
80 @ At that moment, IRQ will be pending and ARM will jump to Non Secure
81 @ IRQ handler
82 mov r12, #0xFE
83
84 dsb
85 dmb
86 smc 0 @ SMC #0 to enter monitor mode
87
88omap_smc_sec_end:
89 pop {r4-r12, pc}
90ENDPROC(omap_smc_sec)