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git01.mediatek.com / filogic / uboot / 2cff3e7825951acd3ed07db62b95ab6c7f3fecaf / . / arch / arm / cpu / armv7 / omap-common / lowlevel_init.S
blob: 66a3b3d26c950a48f29e19cab4681eff98f9e766 [file] [log] [blame]
Minkyu Kangae6f0c62009-07-20 11:40:01 +0900[diff] [blame]1/*
Steve Sakoman1ad21582010-06-08 13:07:46 -0700[diff] [blame]2 * Board specific setup info
3 *
4 * (C) Copyright 2010
5 * Texas Instruments, <www.ti.com>
6 *
7 * Author :
8 * Aneesh V <aneesh@ti.com>
Minkyu Kangae6f0c62009-07-20 11:40:01 +0900[diff] [blame]9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]10 * SPDX-License-Identifier: GPL-2.0+
Minkyu Kangae6f0c62009-07-20 11:40:01 +0900[diff] [blame]11 */
12
Tom Rini8eb48ff2013-03-14 11:15:25 +0000[diff] [blame]13#include <config.h>
Sricharan9310ff72011-11-15 09:49:55 -0500[diff] [blame]14#include <asm/arch/omap.h>
SRICHARAN R3f30b0a2013-04-24 00:41:24 +0000[diff] [blame]15#include <asm/omap_common.h>
Joel A Fernandesb55759e2012-09-18 04:30:51 +0000[diff] [blame]16#include <asm/arch/spl.h>
Aneesh Vfd8798b2012-03-08 07:20:18 +0000[diff] [blame]17#include <linux/linkage.h>
Sricharan308fe922011-11-15 09:50:03 -0500[diff] [blame]18
Daniel Allred2cff3e72016-06-27 09:19:17 -0500[diff] [blame^]19.arch_extension sec
20
Paul Kocialkowskid5b76242015-07-15 16:02:19 +0200[diff] [blame]21#ifdef CONFIG_SPL
Aneesh Vfd8798b2012-03-08 07:20:18 +0000[diff] [blame]22ENTRY(save_boot_params)
SRICHARAN R3f30b0a2013-04-24 00:41:24 +0000[diff] [blame]23 ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
Sricharan308fe922011-11-15 09:50:03 -0500[diff] [blame]24 str r0, [r1]
Simon Glass47197fe2015-02-07 10:47:28 -0700[diff] [blame]25 b save_boot_params_ret
Aneesh Vfd8798b2012-03-08 07:20:18 +0000[diff] [blame]26ENDPROC(save_boot_params)
Nishanth Menona816cc32015-03-09 17:12:05 -0500[diff] [blame]27#endif
Sricharan308fe922011-11-15 09:50:03 -0500[diff] [blame]28
Nishanth Menon19e1fdf2015-03-09 17:12:03 -0500[diff] [blame]29ENTRY(omap_smc1)
Daniel Allred2cff3e72016-06-27 09:19:17 -0500[diff] [blame^]30 push {r4-r12, lr} @ save registers - ROM code may pollute
Aneesh Ve3405bd2011-06-16 23:30:52 +0000[diff] [blame]31 @ our registers
Daniel Allred2cff3e72016-06-27 09:19:17 -0500[diff] [blame^]32 mov r12, r0 @ Service
33 mov r0, r1 @ Argument
Nishanth Menon19e1fdf2015-03-09 17:12:03 -0500[diff] [blame]34
Daniel Allred2cff3e72016-06-27 09:19:17 -0500[diff] [blame^]35 dsb
36 dmb
37 smc 0 @ SMC #0 to enter monitor mode
38 @ call ROM Code API for the service requested
39 pop {r4-r12, pc}
Nishanth Menon19e1fdf2015-03-09 17:12:03 -0500[diff] [blame]40ENDPROC(omap_smc1)
Daniel Allred2cff3e72016-06-27 09:19:17 -0500[diff] [blame^]41
42ENTRY(omap_smc_sec)
43 push {r4-r12, lr} @ save registers - ROM code may pollute
44 @ our registers
45 mov r6, #0xFF @ Indicate new Task call
46 mov r12, #0x00 @ Secure Service ID in R12
47
48 dsb
49 dmb
50 smc 0 @ SMC #0 to enter monitor mode
51
52 b omap_smc_sec_end @ exit at end of the service execution
53 nop
54
55 @ In case of IRQ happening in Secure, then ARM will branch here.
56 @ At that moment, IRQ will be pending and ARM will jump to Non Secure
57 @ IRQ handler
58 mov r12, #0xFE
59
60 dsb
61 dmb
62 smc 0 @ SMC #0 to enter monitor mode
63
64omap_smc_sec_end:
65 pop {r4-r12, pc}
66ENDPROC(omap_smc_sec)