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Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +09001/*
2 * Configuation settings for the Hitachi Solution Engine 7750
3 *
4 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +09007 */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +09008
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +09009#ifndef __MS7750SE_H
10#define __MS7750SE_H
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090011
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090012#define CONFIG_CPU_SH7750 1
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090013/* #define CONFIG_CPU_SH7751 1 */
14/* #define CONFIG_CPU_TYPE_R 1 */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090015#define __LITTLE_ENDIAN__ 1
16
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020017#define CONFIG_DISPLAY_BOARDINFO
18
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090019/*
20 * Command line configuration.
21 */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090022#define CONFIG_CONS_SCIF1 1
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090023
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090024#define CONFIG_ENV_OVERWRITE 1
25
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090026/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020027#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
28#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090029
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020030#define CONFIG_SYS_LONGHELP
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020031#define CONFIG_SYS_PBSIZE 256
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090032
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020033#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
Wolfgang Denk0708bc62010-10-07 21:51:12 +020034#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090035
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090036/* NOR Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020037/* #define CONFIG_SYS_FLASH_BASE (0xA1000000)*/
38#define CONFIG_SYS_FLASH_BASE (0xA0000000)
39#define CONFIG_SYS_MAX_FLASH_BANKS (1) /* Max number of
Wolfgang Denka1be4762008-05-20 16:00:29 +020040 * Flash memory banks
41 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020042#define CONFIG_SYS_MAX_FLASH_SECT 142
43#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090044
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020045#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
46#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) /* Address of u-boot image in Flash */
47#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
48#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090049
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
51#define CONFIG_SYS_RX_ETH_BUFFER (8)
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090052
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +020054#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020055#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
56#undef CONFIG_SYS_FLASH_QUIET_TEST
57#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090058
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020059#define CONFIG_ENV_SECT_SIZE 0x20000
60#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
62#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
63#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090064
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090065/* Board Clock */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090066#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090067#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
68#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +020069#define CONFIG_SYS_TMU_CLK_DIV 4
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090070
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090071#endif /* __MS7750SE_H */