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Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +09001/*
2 * Configuation settings for the Hitachi Solution Engine 7750
3 *
4 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +09007 */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +09008
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +09009#ifndef __MS7750SE_H
10#define __MS7750SE_H
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090011
12#define CONFIG_SH 1
13#define CONFIG_SH4 1
14#define CONFIG_CPU_SH7750 1
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090015/* #define CONFIG_CPU_SH7751 1 */
16/* #define CONFIG_CPU_TYPE_R 1 */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090017#define CONFIG_MS7750SE 1
18#define __LITTLE_ENDIAN__ 1
19
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090020/*
21 * Command line configuration.
22 */
Wolfgang Denk0a5c2142007-12-27 01:52:50 +010023/*#include <config_cmd_default.h>*/
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090024
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090025#define CONFIG_CMD_FLASH
Mike Frysinger78dcaf42009-01-28 19:08:14 -050026#define CONFIG_CMD_SAVEENV
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090027
Jean-Christophe PLAGNIOL-VILLARD6ce9ea62008-08-13 01:40:38 +020028#define CONFIG_SCIF_CONSOLE 1
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090029#define CONFIG_BAUDRATE 38400
30#define CONFIG_CONS_SCIF1 1
Helmut Raigerd5a184b2011-10-20 04:19:47 +000031#define CONFIG_BOARD_LATE_INIT
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090032
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090033#define CONFIG_BOOTDELAY -1
Wolfgang Denka1be4762008-05-20 16:00:29 +020034#define CONFIG_BOOTARGS "console=ttySC0,38400"
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090035#define CONFIG_ENV_OVERWRITE 1
36
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090037/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020038#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
39#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090040
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020041#define CONFIG_SYS_LONGHELP
42#define CONFIG_SYS_PROMPT "=> "
43#define CONFIG_SYS_CBSIZE 256
44#define CONFIG_SYS_PBSIZE 256
45#define CONFIG_SYS_MAXARGS 16
46#define CONFIG_SYS_BARGSIZE 512
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090047
Nobuhiro Iwamatsuec9415d2011-01-17 21:08:58 +090048#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
Wolfgang Denk0708bc62010-10-07 21:51:12 +020050#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090051
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090052/* NOR Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053/* #define CONFIG_SYS_FLASH_BASE (0xA1000000)*/
54#define CONFIG_SYS_FLASH_BASE (0xA0000000)
55#define CONFIG_SYS_MAX_FLASH_BANKS (1) /* Max number of
Wolfgang Denka1be4762008-05-20 16:00:29 +020056 * Flash memory banks
57 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058#define CONFIG_SYS_MAX_FLASH_SECT 142
59#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090060
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
62#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) /* Address of u-boot image in Flash */
63#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
64#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090065
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020066#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
67#define CONFIG_SYS_RX_ETH_BUFFER (8)
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090068
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020069#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +020070#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
72#undef CONFIG_SYS_FLASH_QUIET_TEST
73#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090074
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090075
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020076#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020077#define CONFIG_ENV_SECT_SIZE 0x20000
78#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
80#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
81#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090082
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090083/* Board Clock */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090084#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090085#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
86#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +020087#define CONFIG_SYS_TMU_CLK_DIV 4
Jean-Christophe PLAGNIOL-VILLARD51704102009-06-04 12:06:47 +020088#define CONFIG_SYS_HZ 1000
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090089
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090090#endif /* __MS7750SE_H */