blob: 637eb2dd06f5394d491a11cf5d6675219ca07339 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07002/*
3 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07005 */
6
7#include <common.h>
Patrick Delaunay9225f3e2020-04-27 15:29:59 +02008#include <clk.h>
Simon Glass63334482019-11-14 12:57:39 -07009#include <cpu_func.h>
Simon Glassa7ea72c2015-07-07 20:53:37 -060010#include <dm.h>
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -070011#include <errno.h>
Patrick Delaunaybb3569d2020-04-27 15:29:58 +020012#include <generic-phy.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -070014#include <malloc.h>
Simon Glass2dd337a2015-09-02 17:24:58 -060015#include <memalign.h>
Stephen Warren79beb282015-03-24 20:07:35 -060016#include <phys2bus.h>
Patrick Delaunay9225f3e2020-04-27 15:29:59 +020017#include <usb.h>
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -070018#include <usbroothubdes.h>
Mateusz Kulikowski2765f1e2016-01-23 11:54:30 +010019#include <wait_bit.h>
Simon Glass274e0b02020-05-10 11:39:56 -060020#include <asm/cache.h>
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -070021#include <asm/io.h>
Simon Glass9bc15642020-02-03 07:36:16 -070022#include <dm/device_compat.h>
Simon Glassdbd79542020-05-10 11:40:11 -060023#include <linux/delay.h>
João Loureiroec76d072021-03-17 16:52:21 +010024#include <linux/usb/otg.h>
Kever Yang327c24d2017-03-10 12:05:14 +080025#include <power/regulator.h>
Ley Foon Tan23865562018-08-29 00:08:48 +080026#include <reset.h>
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -070027
28#include "dwc2.h"
29
30/* Use only HC channel 0. */
31#define DWC2_HC_CHANNEL 0
32
33#define DWC2_STATUS_BUF_SIZE 64
Alexey Brodkinf19414b2018-02-28 16:16:58 +030034#define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -070035
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -070036#define MAX_DEVICE 16
37#define MAX_ENDPOINT 16
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -070038
Simon Glasse3c23a02015-07-07 20:53:36 -060039struct dwc2_priv {
Sven Schwermer8a3cb9f12018-11-21 08:43:56 +010040#if CONFIG_IS_ENABLED(DM_USB)
Alexander Stein76fac502015-07-24 09:22:14 +020041 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
42 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
Christophe Kerellof2a5a0b2018-03-15 18:00:30 +010043#ifdef CONFIG_DM_REGULATOR
44 struct udevice *vbus_supply;
45#endif
Patrick Delaunaybb3569d2020-04-27 15:29:58 +020046 struct phy phy;
Patrick Delaunay9225f3e2020-04-27 15:29:59 +020047 struct clk_bulk clks;
Simon Glassa7ea72c2015-07-07 20:53:37 -060048#else
Simon Glasse3c23a02015-07-07 20:53:36 -060049 uint8_t *aligned_buffer;
50 uint8_t *status_buffer;
Simon Glassa7ea72c2015-07-07 20:53:37 -060051#endif
Stefan Brüns081dcc72016-01-23 01:42:25 +010052 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
53 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
Simon Glasse3c23a02015-07-07 20:53:36 -060054 struct dwc2_core_regs *regs;
55 int root_hub_devnum;
Marek Vasut39209492016-04-27 14:55:57 +020056 bool ext_vbus;
Meng Dongyang697a8bc2017-06-28 19:22:43 +080057 /*
58 * The hnp/srp capability must be disabled if the platform
59 * does't support hnp/srp. Otherwise the force mode can't work.
60 */
Meng Dongyangcc3fe062017-06-08 15:34:20 +080061 bool hnp_srp_disable;
Marek Vasut43db5a62016-04-27 14:58:49 +020062 bool oc_disable;
Ley Foon Tan23865562018-08-29 00:08:48 +080063
64 struct reset_ctl_bulk resets;
Simon Glasse3c23a02015-07-07 20:53:36 -060065};
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -070066
Sven Schwermer8a3cb9f12018-11-21 08:43:56 +010067#if !CONFIG_IS_ENABLED(DM_USB)
Alexander Stein76fac502015-07-24 09:22:14 +020068/* We need cacheline-aligned buffers for DMA transfers and dcache support */
69DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
70 ARCH_DMA_MINALIGN);
71DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
72 ARCH_DMA_MINALIGN);
Simon Glasse3c23a02015-07-07 20:53:36 -060073
74static struct dwc2_priv local;
Simon Glassa7ea72c2015-07-07 20:53:37 -060075#endif
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -070076
77/*
78 * DWC2 IP interface
79 */
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -070080
81/*
82 * Initializes the FSLSPClkSel field of the HCFG register
83 * depending on the PHY type.
84 */
85static void init_fslspclksel(struct dwc2_core_regs *regs)
86{
87 uint32_t phyclk;
88
Tom Rinia99817c2021-08-10 16:17:55 -040089#if (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -070090 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
91#else
92 /* High speed PHY running at full speed or high speed */
93 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
94#endif
95
Tom Rinia99817c2021-08-10 16:17:55 -040096#ifdef DWC2_ULPI_FS_LS
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -070097 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
98 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
99 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
100 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
101 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
102
103 if (hval == 2 && fval == 1)
104 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
105#endif
106
107 clrsetbits_le32(&regs->host_regs.hcfg,
108 DWC2_HCFG_FSLSPCLKSEL_MASK,
109 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
110}
111
112/*
113 * Flush a Tx FIFO.
114 *
115 * @param regs Programming view of DWC_otg controller.
116 * @param num Tx FIFO to flush.
117 */
Sean Anderson62eff9b2020-09-15 10:45:15 -0400118static void dwc_otg_flush_tx_fifo(struct udevice *dev,
119 struct dwc2_core_regs *regs, const int num)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700120{
121 int ret;
122
123 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
124 &regs->grstctl);
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100125 ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
126 false, 1000, false);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700127 if (ret)
Patrice Chotarda259c1d2018-03-15 18:00:32 +0100128 dev_info(dev, "%s: Timeout!\n", __func__);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700129
130 /* Wait for 3 PHY Clocks */
131 udelay(1);
132}
133
134/*
135 * Flush Rx FIFO.
136 *
137 * @param regs Programming view of DWC_otg controller.
138 */
Sean Anderson62eff9b2020-09-15 10:45:15 -0400139static void dwc_otg_flush_rx_fifo(struct udevice *dev,
140 struct dwc2_core_regs *regs)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700141{
142 int ret;
143
144 writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100145 ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
146 false, 1000, false);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700147 if (ret)
Patrice Chotarda259c1d2018-03-15 18:00:32 +0100148 dev_info(dev, "%s: Timeout!\n", __func__);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700149
150 /* Wait for 3 PHY Clocks */
151 udelay(1);
152}
153
154/*
155 * Do core a soft reset of the core. Be careful with this because it
156 * resets all the internal state machines of the core.
157 */
Sean Anderson62eff9b2020-09-15 10:45:15 -0400158static void dwc_otg_core_reset(struct udevice *dev,
159 struct dwc2_core_regs *regs)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700160{
161 int ret;
162
163 /* Wait for AHB master IDLE state. */
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100164 ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
165 true, 1000, false);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700166 if (ret)
Patrice Chotarda259c1d2018-03-15 18:00:32 +0100167 dev_info(dev, "%s: Timeout!\n", __func__);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700168
169 /* Core Soft Reset */
170 writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100171 ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_CSFTRST,
172 false, 1000, false);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700173 if (ret)
Patrice Chotarda259c1d2018-03-15 18:00:32 +0100174 dev_info(dev, "%s: Timeout!\n", __func__);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700175
176 /*
177 * Wait for core to come out of reset.
178 * NOTE: This long sleep is _very_ important, otherwise the core will
179 * not stay in host mode after a connector ID change!
180 */
181 mdelay(100);
182}
183
Sven Schwermer8a3cb9f12018-11-21 08:43:56 +0100184#if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
Kever Yang327c24d2017-03-10 12:05:14 +0800185static int dwc_vbus_supply_init(struct udevice *dev)
186{
Christophe Kerellof2a5a0b2018-03-15 18:00:30 +0100187 struct dwc2_priv *priv = dev_get_priv(dev);
Kever Yang327c24d2017-03-10 12:05:14 +0800188 int ret;
189
Christophe Kerellof2a5a0b2018-03-15 18:00:30 +0100190 ret = device_get_supply_regulator(dev, "vbus-supply",
191 &priv->vbus_supply);
Kever Yang327c24d2017-03-10 12:05:14 +0800192 if (ret) {
193 debug("%s: No vbus supply\n", dev->name);
194 return 0;
195 }
196
Jonas Karlman4f634d62023-07-19 21:20:56 +0000197 ret = regulator_set_enable_if_allowed(priv->vbus_supply, true);
198 if (ret && ret != -ENOSYS) {
Patrice Chotarda259c1d2018-03-15 18:00:32 +0100199 dev_err(dev, "Error enabling vbus supply\n");
Kever Yang327c24d2017-03-10 12:05:14 +0800200 return ret;
201 }
202
203 return 0;
204}
Christophe Kerellof2a5a0b2018-03-15 18:00:30 +0100205
206static int dwc_vbus_supply_exit(struct udevice *dev)
207{
208 struct dwc2_priv *priv = dev_get_priv(dev);
209 int ret;
210
Jonas Karlman4f634d62023-07-19 21:20:56 +0000211 ret = regulator_set_enable_if_allowed(priv->vbus_supply, false);
212 if (ret && ret != -ENOSYS) {
213 dev_err(dev, "Error disabling vbus supply\n");
214 return ret;
Christophe Kerellof2a5a0b2018-03-15 18:00:30 +0100215 }
216
217 return 0;
218}
Kever Yang327c24d2017-03-10 12:05:14 +0800219#else
220static int dwc_vbus_supply_init(struct udevice *dev)
221{
222 return 0;
223}
Christophe Kerellof2a5a0b2018-03-15 18:00:30 +0100224
Sven Schwermer8a3cb9f12018-11-21 08:43:56 +0100225#if CONFIG_IS_ENABLED(DM_USB)
Christophe Kerellof2a5a0b2018-03-15 18:00:30 +0100226static int dwc_vbus_supply_exit(struct udevice *dev)
227{
228 return 0;
229}
Kever Yang327c24d2017-03-10 12:05:14 +0800230#endif
Christophe Kerellof2a5a0b2018-03-15 18:00:30 +0100231#endif
Kever Yang327c24d2017-03-10 12:05:14 +0800232
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700233/*
234 * This function initializes the DWC_otg controller registers for
235 * host mode.
236 *
237 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
238 * request queues. Host channels are reset to ensure that they are ready for
239 * performing transfers.
240 *
Kever Yang327c24d2017-03-10 12:05:14 +0800241 * @param dev USB Device (NULL if driver model is not being used)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700242 * @param regs Programming view of DWC_otg controller
243 *
244 */
Kever Yang327c24d2017-03-10 12:05:14 +0800245static void dwc_otg_core_host_init(struct udevice *dev,
246 struct dwc2_core_regs *regs)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700247{
248 uint32_t nptxfifosize = 0;
249 uint32_t ptxfifosize = 0;
250 uint32_t hprt0 = 0;
251 int i, ret, num_channels;
252
253 /* Restart the Phy Clock */
254 writel(0, &regs->pcgcctl);
255
256 /* Initialize Host Configuration Register */
257 init_fslspclksel(regs);
Tom Rinia99817c2021-08-10 16:17:55 -0400258#ifdef DWC2_DFLT_SPEED_FULL
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700259 setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
260#endif
261
262 /* Configure data FIFO sizes */
Tom Rinia99817c2021-08-10 16:17:55 -0400263#ifdef DWC2_ENABLE_DYNAMIC_FIFO
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700264 if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
265 /* Rx FIFO */
Tom Rinia99817c2021-08-10 16:17:55 -0400266 writel(DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700267
268 /* Non-periodic Tx FIFO */
Tom Rinia99817c2021-08-10 16:17:55 -0400269 nptxfifosize |= DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700270 DWC2_FIFOSIZE_DEPTH_OFFSET;
Tom Rinia99817c2021-08-10 16:17:55 -0400271 nptxfifosize |= DWC2_HOST_RX_FIFO_SIZE <<
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700272 DWC2_FIFOSIZE_STARTADDR_OFFSET;
273 writel(nptxfifosize, &regs->gnptxfsiz);
274
275 /* Periodic Tx FIFO */
Tom Rinia99817c2021-08-10 16:17:55 -0400276 ptxfifosize |= DWC2_HOST_PERIO_TX_FIFO_SIZE <<
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700277 DWC2_FIFOSIZE_DEPTH_OFFSET;
Tom Rinia99817c2021-08-10 16:17:55 -0400278 ptxfifosize |= (DWC2_HOST_RX_FIFO_SIZE +
279 DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700280 DWC2_FIFOSIZE_STARTADDR_OFFSET;
281 writel(ptxfifosize, &regs->hptxfsiz);
282 }
283#endif
284
285 /* Clear Host Set HNP Enable in the OTG Control Register */
286 clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
287
288 /* Make sure the FIFOs are flushed. */
Sean Anderson62eff9b2020-09-15 10:45:15 -0400289 dwc_otg_flush_tx_fifo(dev, regs, 0x10); /* All Tx FIFOs */
290 dwc_otg_flush_rx_fifo(dev, regs);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700291
292 /* Flush out any leftover queued requests. */
293 num_channels = readl(&regs->ghwcfg2);
294 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
295 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
296 num_channels += 1;
297
298 for (i = 0; i < num_channels; i++)
299 clrsetbits_le32(&regs->hc_regs[i].hcchar,
300 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
301 DWC2_HCCHAR_CHDIS);
302
303 /* Halt all channels to put them into a known state. */
304 for (i = 0; i < num_channels; i++) {
305 clrsetbits_le32(&regs->hc_regs[i].hcchar,
306 DWC2_HCCHAR_EPDIR,
307 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100308 ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar,
309 DWC2_HCCHAR_CHEN, false, 1000, false);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700310 if (ret)
Sean Anderson62eff9b2020-09-15 10:45:15 -0400311 dev_info(dev, "%s: Timeout!\n", __func__);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700312 }
313
314 /* Turn on the vbus power. */
315 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
Teik Heng Chong9715f3c2023-06-21 11:13:58 +0800316 hprt0 = readl(&regs->hprt0) & ~DWC2_HPRT0_W1C_MASK;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700317 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
318 hprt0 |= DWC2_HPRT0_PRTPWR;
319 writel(hprt0, &regs->hprt0);
320 }
321 }
Kever Yang327c24d2017-03-10 12:05:14 +0800322
323 if (dev)
324 dwc_vbus_supply_init(dev);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700325}
326
327/*
328 * This function initializes the DWC_otg controller registers and
329 * prepares the core for device mode or host mode operation.
330 *
331 * @param regs Programming view of the DWC_otg controller
332 */
Sean Anderson62eff9b2020-09-15 10:45:15 -0400333static void dwc_otg_core_init(struct udevice *dev)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700334{
Sean Anderson62eff9b2020-09-15 10:45:15 -0400335 struct dwc2_priv *priv = dev_get_priv(dev);
Marek Vasut36fc5692016-04-27 14:53:33 +0200336 struct dwc2_core_regs *regs = priv->regs;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700337 uint32_t ahbcfg = 0;
338 uint32_t usbcfg = 0;
Tom Rinia99817c2021-08-10 16:17:55 -0400339 uint8_t brst_sz = DWC2_DMA_BURST_SIZE;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700340
341 /* Common Initialization */
342 usbcfg = readl(&regs->gusbcfg);
343
344 /* Program the ULPI External VBUS bit if needed */
Marek Vasut39209492016-04-27 14:55:57 +0200345 if (priv->ext_vbus) {
Marek Vasut43db5a62016-04-27 14:58:49 +0200346 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
347 if (!priv->oc_disable) {
348 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
349 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
350 }
Marek Vasut39209492016-04-27 14:55:57 +0200351 } else {
352 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
353 }
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700354
355 /* Set external TS Dline pulsing */
Tom Rinia99817c2021-08-10 16:17:55 -0400356#ifdef DWC2_TS_DLINE
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700357 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
358#else
359 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
360#endif
361 writel(usbcfg, &regs->gusbcfg);
362
363 /* Reset the Controller */
Sean Anderson62eff9b2020-09-15 10:45:15 -0400364 dwc_otg_core_reset(dev, regs);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700365
366 /*
367 * This programming sequence needs to happen in FS mode before
368 * any other programming occurs
369 */
Tom Rinia99817c2021-08-10 16:17:55 -0400370#if defined(DWC2_DFLT_SPEED_FULL) && \
371 (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700372 /* If FS mode with FS PHY */
373 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
374
375 /* Reset after a PHY select */
Sean Anderson62eff9b2020-09-15 10:45:15 -0400376 dwc_otg_core_reset(dev, regs);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700377
378 /*
379 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
380 * Also do this on HNP Dev/Host mode switches (done in dev_init
381 * and host_init).
382 */
383 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
384 init_fslspclksel(regs);
385
Tom Rinia99817c2021-08-10 16:17:55 -0400386#ifdef DWC2_I2C_ENABLE
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700387 /* Program GUSBCFG.OtgUtmifsSel to I2C */
388 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
389
390 /* Program GI2CCTL.I2CEn */
391 clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
392 DWC2_GI2CCTL_I2CDEVADDR_MASK,
393 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
394 setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
395#endif
396
397#else
398 /* High speed PHY. */
399
400 /*
401 * HS PHY parameters. These parameters are preserved during
402 * soft reset so only program the first time. Do a soft reset
403 * immediately after setting phyif.
404 */
405 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
Tom Rinia99817c2021-08-10 16:17:55 -0400406 usbcfg |= DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700407
408 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
Tom Rinia99817c2021-08-10 16:17:55 -0400409#ifdef DWC2_PHY_ULPI_DDR
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700410 usbcfg |= DWC2_GUSBCFG_DDRSEL;
411#else
412 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
413#endif
414 } else { /* UTMI+ interface */
Tom Rinia99817c2021-08-10 16:17:55 -0400415#if (DWC2_UTMI_WIDTH == 16)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700416 usbcfg |= DWC2_GUSBCFG_PHYIF;
417#endif
418 }
419
420 writel(usbcfg, &regs->gusbcfg);
421
422 /* Reset after setting the PHY parameters */
Sean Anderson62eff9b2020-09-15 10:45:15 -0400423 dwc_otg_core_reset(dev, regs);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700424#endif
425
426 usbcfg = readl(&regs->gusbcfg);
427 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
Tom Rinia99817c2021-08-10 16:17:55 -0400428#ifdef DWC2_ULPI_FS_LS
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700429 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
430 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
431 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
432 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
433 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
434 if (hval == 2 && fval == 1) {
435 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
436 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
437 }
438#endif
Meng Dongyangcc3fe062017-06-08 15:34:20 +0800439 if (priv->hnp_srp_disable)
440 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
441
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700442 writel(usbcfg, &regs->gusbcfg);
443
444 /* Program the GAHBCFG Register. */
445 switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
446 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
447 break;
448 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
449 while (brst_sz > 1) {
450 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
451 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
452 brst_sz >>= 1;
453 }
454
Tom Rinia99817c2021-08-10 16:17:55 -0400455#ifdef DWC2_DMA_ENABLE
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700456 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
457#endif
458 break;
459
460 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
461 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
Tom Rinia99817c2021-08-10 16:17:55 -0400462#ifdef DWC2_DMA_ENABLE
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700463 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
464#endif
465 break;
466 }
467
468 writel(ahbcfg, &regs->gahbcfg);
469
Meng Dongyangcc3fe062017-06-08 15:34:20 +0800470 /* Program the capabilities in GUSBCFG Register */
471 usbcfg = 0;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700472
Meng Dongyangcc3fe062017-06-08 15:34:20 +0800473 if (!priv->hnp_srp_disable)
474 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
Tom Rinia99817c2021-08-10 16:17:55 -0400475#ifdef DWC2_IC_USB_CAP
Meng Dongyangcc3fe062017-06-08 15:34:20 +0800476 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700477#endif
Meng Dongyangcc3fe062017-06-08 15:34:20 +0800478
479 setbits_le32(&regs->gusbcfg, usbcfg);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700480}
481
482/*
483 * Prepares a host channel for transferring packets to/from a specific
484 * endpoint. The HCCHARn register is set up with the characteristics specified
485 * in _hc. Host channel interrupts that may need to be serviced while this
486 * transfer is in progress are enabled.
487 *
488 * @param regs Programming view of DWC_otg controller
489 * @param hc Information needed to initialize the host channel
490 */
491static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
Stephen Warrendead8db2015-04-10 21:05:21 -0600492 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
493 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700494{
495 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
Stephen Warrendead8db2015-04-10 21:05:21 -0600496 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
497 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
498 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
499 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
500 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
501
502 if (dev->speed == USB_SPEED_LOW)
503 hcchar |= DWC2_HCCHAR_LSPDDEV;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700504
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700505 /*
506 * Program the HCCHARn register with the endpoint characteristics
507 * for the current transfer.
508 */
509 writel(hcchar, &hc_regs->hcchar);
510
Stefan Brüns2e194e22016-01-17 04:09:54 +0100511 /* Program the HCSPLIT register, default to no SPLIT */
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700512 writel(0, &hc_regs->hcsplt);
513}
514
Stefan Brüns2e194e22016-01-17 04:09:54 +0100515static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
516 uint8_t hub_devnum, uint8_t hub_port)
517{
518 uint32_t hcsplt = 0;
519
520 hcsplt = DWC2_HCSPLT_SPLTENA;
521 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
522 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
523
524 /* Program the HCSPLIT register for SPLITs */
525 writel(hcsplt, &hc_regs->hcsplt);
526}
527
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700528/*
529 * DWC2 to USB API interface
530 */
531/* Direction: In ; Request: Status */
Simon Glasse3c23a02015-07-07 20:53:36 -0600532static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
533 struct usb_device *dev, void *buffer,
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700534 int txlen, struct devrequest *cmd)
535{
536 uint32_t hprt0 = 0;
537 uint32_t port_status = 0;
538 uint32_t port_change = 0;
539 int len = 0;
540 int stat = 0;
541
542 switch (cmd->requesttype & ~USB_DIR_IN) {
543 case 0:
544 *(uint16_t *)buffer = cpu_to_le16(1);
545 len = 2;
546 break;
547 case USB_RECIP_INTERFACE:
548 case USB_RECIP_ENDPOINT:
549 *(uint16_t *)buffer = cpu_to_le16(0);
550 len = 2;
551 break;
552 case USB_TYPE_CLASS:
553 *(uint32_t *)buffer = cpu_to_le32(0);
554 len = 4;
555 break;
556 case USB_RECIP_OTHER | USB_TYPE_CLASS:
557 hprt0 = readl(&regs->hprt0);
558 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
559 port_status |= USB_PORT_STAT_CONNECTION;
560 if (hprt0 & DWC2_HPRT0_PRTENA)
561 port_status |= USB_PORT_STAT_ENABLE;
562 if (hprt0 & DWC2_HPRT0_PRTSUSP)
563 port_status |= USB_PORT_STAT_SUSPEND;
564 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
565 port_status |= USB_PORT_STAT_OVERCURRENT;
566 if (hprt0 & DWC2_HPRT0_PRTRST)
567 port_status |= USB_PORT_STAT_RESET;
568 if (hprt0 & DWC2_HPRT0_PRTPWR)
569 port_status |= USB_PORT_STAT_POWER;
570
Stephen Warrend3388f82015-03-27 21:55:38 -0600571 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
572 port_status |= USB_PORT_STAT_LOW_SPEED;
573 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
574 DWC2_HPRT0_PRTSPD_HIGH)
575 port_status |= USB_PORT_STAT_HIGH_SPEED;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700576
577 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
578 port_change |= USB_PORT_STAT_C_ENABLE;
579 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
580 port_change |= USB_PORT_STAT_C_CONNECTION;
581 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
582 port_change |= USB_PORT_STAT_C_OVERCURRENT;
583
584 *(uint32_t *)buffer = cpu_to_le32(port_status |
585 (port_change << 16));
586 len = 4;
587 break;
588 default:
589 puts("unsupported root hub command\n");
590 stat = USB_ST_STALLED;
591 }
592
593 dev->act_len = min(len, txlen);
594 dev->status = stat;
595
596 return stat;
597}
598
599/* Direction: In ; Request: Descriptor */
600static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
601 void *buffer, int txlen,
602 struct devrequest *cmd)
603{
604 unsigned char data[32];
605 uint32_t dsc;
606 int len = 0;
607 int stat = 0;
608 uint16_t wValue = cpu_to_le16(cmd->value);
609 uint16_t wLength = cpu_to_le16(cmd->length);
610
611 switch (cmd->requesttype & ~USB_DIR_IN) {
612 case 0:
613 switch (wValue & 0xff00) {
614 case 0x0100: /* device descriptor */
Masahiro Yamadadb204642014-11-07 03:03:31 +0900615 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700616 memcpy(buffer, root_hub_dev_des, len);
617 break;
618 case 0x0200: /* configuration descriptor */
Masahiro Yamadadb204642014-11-07 03:03:31 +0900619 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700620 memcpy(buffer, root_hub_config_des, len);
621 break;
622 case 0x0300: /* string descriptors */
623 switch (wValue & 0xff) {
624 case 0x00:
Masahiro Yamadadb204642014-11-07 03:03:31 +0900625 len = min3(txlen, (int)sizeof(root_hub_str_index0),
626 (int)wLength);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700627 memcpy(buffer, root_hub_str_index0, len);
628 break;
629 case 0x01:
Masahiro Yamadadb204642014-11-07 03:03:31 +0900630 len = min3(txlen, (int)sizeof(root_hub_str_index1),
631 (int)wLength);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700632 memcpy(buffer, root_hub_str_index1, len);
633 break;
634 }
635 break;
636 default:
637 stat = USB_ST_STALLED;
638 }
639 break;
640
641 case USB_TYPE_CLASS:
642 /* Root port config, set 1 port and nothing else. */
643 dsc = 0x00000001;
644
645 data[0] = 9; /* min length; */
646 data[1] = 0x29;
647 data[2] = dsc & RH_A_NDP;
648 data[3] = 0;
649 if (dsc & RH_A_PSM)
650 data[3] |= 0x1;
651 if (dsc & RH_A_NOCP)
652 data[3] |= 0x10;
653 else if (dsc & RH_A_OCPM)
654 data[3] |= 0x8;
655
656 /* corresponds to data[4-7] */
657 data[5] = (dsc & RH_A_POTPGT) >> 24;
658 data[7] = dsc & RH_B_DR;
659 if (data[2] < 7) {
660 data[8] = 0xff;
661 } else {
662 data[0] += 2;
663 data[8] = (dsc & RH_B_DR) >> 8;
664 data[9] = 0xff;
665 data[10] = data[9];
666 }
667
Masahiro Yamadadb204642014-11-07 03:03:31 +0900668 len = min3(txlen, (int)data[0], (int)wLength);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700669 memcpy(buffer, data, len);
670 break;
671 default:
672 puts("unsupported root hub command\n");
673 stat = USB_ST_STALLED;
674 }
675
676 dev->act_len = min(len, txlen);
677 dev->status = stat;
678
679 return stat;
680}
681
682/* Direction: In ; Request: Configuration */
683static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
684 void *buffer, int txlen,
685 struct devrequest *cmd)
686{
687 int len = 0;
688 int stat = 0;
689
690 switch (cmd->requesttype & ~USB_DIR_IN) {
691 case 0:
692 *(uint8_t *)buffer = 0x01;
693 len = 1;
694 break;
695 default:
696 puts("unsupported root hub command\n");
697 stat = USB_ST_STALLED;
698 }
699
700 dev->act_len = min(len, txlen);
701 dev->status = stat;
702
703 return stat;
704}
705
706/* Direction: In */
Simon Glasse3c23a02015-07-07 20:53:36 -0600707static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
708 struct usb_device *dev, void *buffer,
709 int txlen, struct devrequest *cmd)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700710{
711 switch (cmd->request) {
712 case USB_REQ_GET_STATUS:
Simon Glasse3c23a02015-07-07 20:53:36 -0600713 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700714 txlen, cmd);
715 case USB_REQ_GET_DESCRIPTOR:
716 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
717 txlen, cmd);
718 case USB_REQ_GET_CONFIGURATION:
719 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
720 txlen, cmd);
721 default:
722 puts("unsupported root hub command\n");
723 return USB_ST_STALLED;
724 }
725}
726
727/* Direction: Out */
Simon Glasse3c23a02015-07-07 20:53:36 -0600728static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
729 struct usb_device *dev,
730 void *buffer, int txlen,
731 struct devrequest *cmd)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700732{
Simon Glasse3c23a02015-07-07 20:53:36 -0600733 struct dwc2_core_regs *regs = priv->regs;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700734 int len = 0;
735 int stat = 0;
736 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
737 uint16_t wValue = cpu_to_le16(cmd->value);
738
739 switch (bmrtype_breq & ~USB_DIR_IN) {
740 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
741 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
742 break;
743
744 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
745 switch (wValue) {
746 case USB_PORT_FEAT_C_CONNECTION:
Teik Heng Chong9715f3c2023-06-21 11:13:58 +0800747 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTCONNDET);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700748 break;
749 }
750 break;
751
752 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
753 switch (wValue) {
754 case USB_PORT_FEAT_SUSPEND:
755 break;
756
757 case USB_PORT_FEAT_RESET:
Teik Heng Chong9715f3c2023-06-21 11:13:58 +0800758 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTRST);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700759 mdelay(50);
Teik Heng Chong9715f3c2023-06-21 11:13:58 +0800760 clrbits_le32(&regs->hprt0, DWC2_HPRT0_W1C_MASK | DWC2_HPRT0_PRTRST);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700761 break;
762
763 case USB_PORT_FEAT_POWER:
Teik Heng Chong9715f3c2023-06-21 11:13:58 +0800764 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTRST);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700765 break;
766
767 case USB_PORT_FEAT_ENABLE:
768 break;
769 }
770 break;
771 case (USB_REQ_SET_ADDRESS << 8):
Simon Glasse3c23a02015-07-07 20:53:36 -0600772 priv->root_hub_devnum = wValue;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700773 break;
774 case (USB_REQ_SET_CONFIGURATION << 8):
775 break;
776 default:
777 puts("unsupported root hub command\n");
778 stat = USB_ST_STALLED;
779 }
780
781 len = min(len, txlen);
782
783 dev->act_len = len;
784 dev->status = stat;
785
786 return stat;
787}
788
Simon Glasse3c23a02015-07-07 20:53:36 -0600789static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
790 unsigned long pipe, void *buffer, int txlen,
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700791 struct devrequest *cmd)
792{
793 int stat = 0;
794
795 if (usb_pipeint(pipe)) {
796 puts("Root-Hub submit IRQ: NOT implemented\n");
797 return 0;
798 }
799
800 if (cmd->requesttype & USB_DIR_IN)
Simon Glasse3c23a02015-07-07 20:53:36 -0600801 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700802 else
Simon Glasse3c23a02015-07-07 20:53:36 -0600803 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700804
805 mdelay(1);
806
807 return stat;
808}
809
Stefan Brüns081dcc72016-01-23 01:42:25 +0100810int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
Stephen Warren8a346662015-03-07 22:48:51 -0700811{
Stephen Warren8a346662015-03-07 22:48:51 -0700812 int ret;
813 uint32_t hcint, hctsiz;
814
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100815 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
Christophe Kerello4edc9802018-03-15 18:00:31 +0100816 2000, false);
Stephen Warren8a346662015-03-07 22:48:51 -0700817 if (ret)
818 return ret;
819
820 hcint = readl(&hc_regs->hcint);
Stephen Warren8a346662015-03-07 22:48:51 -0700821 hctsiz = readl(&hc_regs->hctsiz);
822 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
823 DWC2_HCTSIZ_XFERSIZE_OFFSET;
Stephen Warren9f80e742015-03-07 22:48:55 -0700824 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
Stephen Warren8a346662015-03-07 22:48:51 -0700825
Stefan Brünsaa9506e2016-01-17 04:09:52 +0100826 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
827 *toggle);
Stephen Warren8a346662015-03-07 22:48:51 -0700828
Stefan Brünsaa9506e2016-01-17 04:09:52 +0100829 if (hcint & DWC2_HCINT_XFERCOMP)
830 return 0;
831
832 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
833 return -EAGAIN;
Stephen Warren8a346662015-03-07 22:48:51 -0700834
Stefan Brünsaa9506e2016-01-17 04:09:52 +0100835 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
836 return -EINVAL;
Stephen Warren8a346662015-03-07 22:48:51 -0700837}
838
Stephen Warren972ad642015-03-07 22:48:52 -0700839static int dwc2_eptype[] = {
840 DWC2_HCCHAR_EPTYPE_ISOC,
841 DWC2_HCCHAR_EPTYPE_INTR,
842 DWC2_HCCHAR_EPTYPE_CONTROL,
843 DWC2_HCCHAR_EPTYPE_BULK,
844};
845
Stefan Brüns2385db32016-01-17 04:09:53 +0100846static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
Stefan Brüns081dcc72016-01-23 01:42:25 +0100847 u8 *pid, int in, void *buffer, int num_packets,
Stefan Brüns247241e2016-01-17 04:09:56 +0100848 int xfer_len, int *actual_len, int odd_frame)
Stefan Brüns2385db32016-01-17 04:09:53 +0100849{
850 int ret = 0;
851 uint32_t sub;
852
853 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
854 *pid, xfer_len, num_packets);
855
856 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
857 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
858 (*pid << DWC2_HCTSIZ_PID_OFFSET),
859 &hc_regs->hctsiz);
860
Eddie Cai408bdee2017-04-06 11:37:04 +0800861 if (xfer_len) {
862 if (in) {
863 invalidate_dcache_range(
864 (uintptr_t)aligned_buffer,
865 (uintptr_t)aligned_buffer +
866 roundup(xfer_len, ARCH_DMA_MINALIGN));
867 } else {
868 memcpy(aligned_buffer, buffer, xfer_len);
869 flush_dcache_range(
870 (uintptr_t)aligned_buffer,
871 (uintptr_t)aligned_buffer +
872 roundup(xfer_len, ARCH_DMA_MINALIGN));
873 }
Stefan Brüns2385db32016-01-17 04:09:53 +0100874 }
875
876 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
877
878 /* Clear old interrupt conditions for this host channel. */
879 writel(0x3fff, &hc_regs->hcint);
880
881 /* Set host channel enable after all other setup is complete. */
882 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
Stefan Brüns247241e2016-01-17 04:09:56 +0100883 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
884 DWC2_HCCHAR_ODDFRM,
Stefan Brüns2385db32016-01-17 04:09:53 +0100885 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
Stefan Brüns247241e2016-01-17 04:09:56 +0100886 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
Stefan Brüns2385db32016-01-17 04:09:53 +0100887 DWC2_HCCHAR_CHEN);
888
889 ret = wait_for_chhltd(hc_regs, &sub, pid);
890 if (ret < 0)
891 return ret;
892
893 if (in) {
894 xfer_len -= sub;
895
896 invalidate_dcache_range((unsigned long)aligned_buffer,
897 (unsigned long)aligned_buffer +
898 roundup(xfer_len, ARCH_DMA_MINALIGN));
899
900 memcpy(buffer, aligned_buffer, xfer_len);
901 }
902 *actual_len = xfer_len;
903
904 return ret;
905}
906
Simon Glasse3c23a02015-07-07 20:53:36 -0600907int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
Stefan Brüns081dcc72016-01-23 01:42:25 +0100908 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700909{
Simon Glasse3c23a02015-07-07 20:53:36 -0600910 struct dwc2_core_regs *regs = priv->regs;
Stephen Warren972ad642015-03-07 22:48:52 -0700911 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
Stefan Brüns247241e2016-01-17 04:09:56 +0100912 struct dwc2_host_regs *host_regs = &regs->host_regs;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700913 int devnum = usb_pipedevice(pipe);
914 int ep = usb_pipeendpoint(pipe);
915 int max = usb_maxpacket(dev, pipe);
Stephen Warren972ad642015-03-07 22:48:52 -0700916 int eptype = dwc2_eptype[usb_pipetype(pipe)];
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700917 int done = 0;
Stephen Warren766fe412015-04-11 21:52:02 -0600918 int ret = 0;
Stefan Brüns0c4b0652016-01-17 04:09:55 +0100919 int do_split = 0;
920 int complete_split = 0;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700921 uint32_t xfer_len;
922 uint32_t num_packets;
923 int stop_transfer = 0;
Stefan Brüns575b0eb2016-01-17 04:09:51 +0100924 uint32_t max_xfer_len;
Stefan Brüns247241e2016-01-17 04:09:56 +0100925 int ssplit_frame_num = 0;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700926
Stephen Warren972ad642015-03-07 22:48:52 -0700927 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
928 in, len);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700929
Tom Rinia99817c2021-08-10 16:17:55 -0400930 max_xfer_len = DWC2_MAX_PACKET_COUNT * max;
931 if (max_xfer_len > DWC2_MAX_TRANSFER_SIZE)
932 max_xfer_len = DWC2_MAX_TRANSFER_SIZE;
Stefan Brüns575b0eb2016-01-17 04:09:51 +0100933 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
934 max_xfer_len = DWC2_DATA_BUF_SIZE;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700935
Stefan Brüns575b0eb2016-01-17 04:09:51 +0100936 /* Make sure that max_xfer_len is a multiple of max packet size. */
937 num_packets = max_xfer_len / max;
938 max_xfer_len = num_packets * max;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700939
Stefan Brüns2385db32016-01-17 04:09:53 +0100940 /* Initialize channel */
941 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
942 eptype, max);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700943
Stefan Brüns0c4b0652016-01-17 04:09:55 +0100944 /* Check if the target is a FS/LS device behind a HS hub */
945 if (dev->speed != USB_SPEED_HIGH) {
946 uint8_t hub_addr;
947 uint8_t hub_port;
948 uint32_t hprt0 = readl(&regs->hprt0);
949 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
950 DWC2_HPRT0_PRTSPD_HIGH) {
951 usb_find_usb2_hub_address_port(dev, &hub_addr,
952 &hub_port);
953 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
954
955 do_split = 1;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700956 num_packets = 1;
Stefan Brüns0c4b0652016-01-17 04:09:55 +0100957 max_xfer_len = max;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700958 }
Stefan Brüns0c4b0652016-01-17 04:09:55 +0100959 }
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700960
Stefan Brüns2385db32016-01-17 04:09:53 +0100961 do {
962 int actual_len = 0;
Stefan Brüns0c4b0652016-01-17 04:09:55 +0100963 uint32_t hcint;
Stefan Brüns247241e2016-01-17 04:09:56 +0100964 int odd_frame = 0;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700965 xfer_len = len - done;
Stephen Warren972ad642015-03-07 22:48:52 -0700966
Stefan Brüns575b0eb2016-01-17 04:09:51 +0100967 if (xfer_len > max_xfer_len)
968 xfer_len = max_xfer_len;
969 else if (xfer_len > max)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700970 num_packets = (xfer_len + max - 1) / max;
Stefan Brüns575b0eb2016-01-17 04:09:51 +0100971 else
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700972 num_packets = 1;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700973
Stefan Brüns0c4b0652016-01-17 04:09:55 +0100974 if (complete_split)
975 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
976 else if (do_split)
977 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
Alexander Stein76fac502015-07-24 09:22:14 +0200978
Stefan Brüns247241e2016-01-17 04:09:56 +0100979 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
980 int uframe_num = readl(&host_regs->hfnum);
981 if (!(uframe_num & 0x1))
982 odd_frame = 1;
Simon Glasse3c23a02015-07-07 20:53:36 -0600983 }
Stephen Warren7100da32015-03-08 11:08:13 -0600984
Stefan Brüns2385db32016-01-17 04:09:53 +0100985 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
986 in, (char *)buffer + done, num_packets,
Stefan Brüns247241e2016-01-17 04:09:56 +0100987 xfer_len, &actual_len, odd_frame);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -0700988
Stefan Brüns0c4b0652016-01-17 04:09:55 +0100989 hcint = readl(&hc_regs->hcint);
990 if (complete_split) {
991 stop_transfer = 0;
Stefan Brüns247241e2016-01-17 04:09:56 +0100992 if (hcint & DWC2_HCINT_NYET) {
Stefan Brüns0c4b0652016-01-17 04:09:55 +0100993 ret = 0;
Stefan Brüns247241e2016-01-17 04:09:56 +0100994 int frame_num = DWC2_HFNUM_MAX_FRNUM &
995 readl(&host_regs->hfnum);
996 if (((frame_num - ssplit_frame_num) &
997 DWC2_HFNUM_MAX_FRNUM) > 4)
998 ret = -EAGAIN;
999 } else
Stefan Brüns0c4b0652016-01-17 04:09:55 +01001000 complete_split = 0;
1001 } else if (do_split) {
1002 if (hcint & DWC2_HCINT_ACK) {
Stefan Brüns247241e2016-01-17 04:09:56 +01001003 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1004 readl(&host_regs->hfnum);
Stefan Brüns0c4b0652016-01-17 04:09:55 +01001005 ret = 0;
1006 complete_split = 1;
1007 }
1008 }
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001009
Stephen Warren766fe412015-04-11 21:52:02 -06001010 if (ret)
Stephen Warren8a346662015-03-07 22:48:51 -07001011 break;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001012
Stefan Brüns2385db32016-01-17 04:09:53 +01001013 if (actual_len < xfer_len)
1014 stop_transfer = 1;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001015
Stefan Brüns2385db32016-01-17 04:09:53 +01001016 done += actual_len;
Stephen Warren7100da32015-03-08 11:08:13 -06001017
Stefan Brüns0c4b0652016-01-17 04:09:55 +01001018 /* Transactions are done when when either all data is transferred or
1019 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1020 * is executed.
1021 */
1022 } while (((done < len) && !stop_transfer) || complete_split);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001023
1024 writel(0, &hc_regs->hcintmsk);
1025 writel(0xFFFFFFFF, &hc_regs->hcint);
1026
1027 dev->status = 0;
1028 dev->act_len = done;
1029
Stephen Warren766fe412015-04-11 21:52:02 -06001030 return ret;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001031}
1032
Stephen Warren972ad642015-03-07 22:48:52 -07001033/* U-Boot USB transmission interface */
Simon Glasse3c23a02015-07-07 20:53:36 -06001034int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1035 unsigned long pipe, void *buffer, int len)
Stephen Warren972ad642015-03-07 22:48:52 -07001036{
1037 int devnum = usb_pipedevice(pipe);
1038 int ep = usb_pipeendpoint(pipe);
Stefan Brüns081dcc72016-01-23 01:42:25 +01001039 u8* pid;
Stephen Warren972ad642015-03-07 22:48:52 -07001040
Stefan Brüns081dcc72016-01-23 01:42:25 +01001041 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
Stephen Warren972ad642015-03-07 22:48:52 -07001042 dev->status = 0;
1043 return -EINVAL;
1044 }
1045
Stefan Brüns081dcc72016-01-23 01:42:25 +01001046 if (usb_pipein(pipe))
1047 pid = &priv->in_data_toggle[devnum][ep];
1048 else
1049 pid = &priv->out_data_toggle[devnum][ep];
1050
1051 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
Stephen Warren972ad642015-03-07 22:48:52 -07001052}
1053
Simon Glasse3c23a02015-07-07 20:53:36 -06001054static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1055 unsigned long pipe, void *buffer, int len,
1056 struct devrequest *setup)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001057{
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001058 int devnum = usb_pipedevice(pipe);
Stefan Brüns081dcc72016-01-23 01:42:25 +01001059 int ret, act_len;
1060 u8 pid;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001061 /* For CONTROL endpoint pid should start with DATA1 */
1062 int status_direction;
1063
Simon Glasse3c23a02015-07-07 20:53:36 -06001064 if (devnum == priv->root_hub_devnum) {
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001065 dev->status = 0;
1066 dev->speed = USB_SPEED_HIGH;
Simon Glasse3c23a02015-07-07 20:53:36 -06001067 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1068 setup);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001069 }
1070
Stefan Brüns0c4b0652016-01-17 04:09:55 +01001071 /* SETUP stage */
Stephen Warren4db200e2015-03-07 22:48:53 -07001072 pid = DWC2_HC_PID_SETUP;
Stefan Brüns0c4b0652016-01-17 04:09:55 +01001073 do {
1074 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1075 } while (ret == -EAGAIN);
Stephen Warren4db200e2015-03-07 22:48:53 -07001076 if (ret)
1077 return ret;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001078
Stefan Brüns0c4b0652016-01-17 04:09:55 +01001079 /* DATA stage */
1080 act_len = 0;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001081 if (buffer) {
Stephen Warrenb0ad4a32015-03-07 22:48:54 -07001082 pid = DWC2_HC_PID_DATA1;
Stefan Brüns0c4b0652016-01-17 04:09:55 +01001083 do {
1084 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1085 buffer, len);
1086 act_len += dev->act_len;
1087 buffer += dev->act_len;
1088 len -= dev->act_len;
1089 } while (ret == -EAGAIN);
Stephen Warren4db200e2015-03-07 22:48:53 -07001090 if (ret)
1091 return ret;
Stefan Brüns0c4b0652016-01-17 04:09:55 +01001092 status_direction = usb_pipeout(pipe);
1093 } else {
1094 /* No-data CONTROL always ends with an IN transaction */
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001095 status_direction = 1;
Stefan Brüns0c4b0652016-01-17 04:09:55 +01001096 }
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001097
Stefan Brüns0c4b0652016-01-17 04:09:55 +01001098 /* STATUS stage */
Stephen Warren4db200e2015-03-07 22:48:53 -07001099 pid = DWC2_HC_PID_DATA1;
Stefan Brüns0c4b0652016-01-17 04:09:55 +01001100 do {
1101 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1102 priv->status_buffer, 0);
1103 } while (ret == -EAGAIN);
Stephen Warren4db200e2015-03-07 22:48:53 -07001104 if (ret)
1105 return ret;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001106
Stephen Warren4db200e2015-03-07 22:48:53 -07001107 dev->act_len = act_len;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001108
Stephen Warren8a346662015-03-07 22:48:51 -07001109 return 0;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001110}
1111
Simon Glasse3c23a02015-07-07 20:53:36 -06001112int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
Michal Suchanek1c95b9f2019-08-18 10:55:27 +02001113 unsigned long pipe, void *buffer, int len, int interval,
1114 bool nonblock)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001115{
Stephen Warren766fe412015-04-11 21:52:02 -06001116 unsigned long timeout;
1117 int ret;
1118
Stephen Warrendf7b37d2015-04-10 21:05:22 -06001119 /* FIXME: what is interval? */
Stephen Warren766fe412015-04-11 21:52:02 -06001120
1121 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1122 for (;;) {
1123 if (get_timer(0) > timeout) {
Sean Anderson62eff9b2020-09-15 10:45:15 -04001124#if CONFIG_IS_ENABLED(DM_USB)
1125 dev_err(dev->dev,
1126 "Timeout poll on interrupt endpoint\n");
1127#else
1128 log_err("Timeout poll on interrupt endpoint\n");
1129#endif
Stephen Warren766fe412015-04-11 21:52:02 -06001130 return -ETIMEDOUT;
1131 }
Simon Glasse3c23a02015-07-07 20:53:36 -06001132 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
Michal Suchanekc7a7ae52019-08-18 10:55:28 +02001133 if ((ret != -EAGAIN) || nonblock)
Stephen Warren766fe412015-04-11 21:52:02 -06001134 return ret;
1135 }
Ley Foon Tan23865562018-08-29 00:08:48 +08001136}
1137
1138static int dwc2_reset(struct udevice *dev)
1139{
1140 int ret;
1141 struct dwc2_priv *priv = dev_get_priv(dev);
1142
1143 ret = reset_get_bulk(dev, &priv->resets);
1144 if (ret) {
1145 dev_warn(dev, "Can't get reset: %d\n", ret);
1146 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1147 * DT property is not present.
1148 */
1149 if (ret == -ENOENT || ret == -ENOTSUPP)
1150 return 0;
1151 else
1152 return ret;
1153 }
1154
Patrick Delaunay8bef1692020-04-27 15:30:00 +02001155 /* force reset to clear all IP register */
1156 reset_assert_bulk(&priv->resets);
Ley Foon Tan23865562018-08-29 00:08:48 +08001157 ret = reset_deassert_bulk(&priv->resets);
1158 if (ret) {
1159 reset_release_bulk(&priv->resets);
1160 dev_err(dev, "Failed to reset: %d\n", ret);
1161 return ret;
1162 }
1163
1164 return 0;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001165}
1166
Kever Yang327c24d2017-03-10 12:05:14 +08001167static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001168{
Simon Glasse3c23a02015-07-07 20:53:36 -06001169 struct dwc2_core_regs *regs = priv->regs;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001170 uint32_t snpsid;
1171 int i, j;
Ley Foon Tan23865562018-08-29 00:08:48 +08001172 int ret;
1173
1174 ret = dwc2_reset(dev);
1175 if (ret)
1176 return ret;
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001177
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001178 snpsid = readl(&regs->gsnpsid);
Patrice Chotarda259c1d2018-03-15 18:00:32 +01001179 dev_info(dev, "Core Release: %x.%03x\n",
1180 snpsid >> 12 & 0xf, snpsid & 0xfff);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001181
Peter Griffin79d657d2015-05-12 14:38:27 +01001182 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1183 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
Patrice Chotarda259c1d2018-03-15 18:00:32 +01001184 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1185 snpsid);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001186 return -ENODEV;
1187 }
1188
Tom Rinia99817c2021-08-10 16:17:55 -04001189#ifdef DWC2_PHY_ULPI_EXT_VBUS
Marek Vasut39209492016-04-27 14:55:57 +02001190 priv->ext_vbus = 1;
1191#else
1192 priv->ext_vbus = 0;
1193#endif
1194
Sean Anderson62eff9b2020-09-15 10:45:15 -04001195 dwc_otg_core_init(dev);
João Loureiroec76d072021-03-17 16:52:21 +01001196
1197 if (usb_get_dr_mode(dev_ofnode(dev)) == USB_DR_MODE_PERIPHERAL) {
1198 dev_dbg(dev, "USB device %s dr_mode set to %d. Skipping host_init.\n",
1199 dev->name, usb_get_dr_mode(dev_ofnode(dev)));
1200 } else {
1201 dwc_otg_core_host_init(dev, regs);
1202 }
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001203
Teik Heng Chong9715f3c2023-06-21 11:13:58 +08001204 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTRST);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001205 mdelay(50);
Teik Heng Chong9715f3c2023-06-21 11:13:58 +08001206 clrbits_le32(&regs->hprt0, DWC2_HPRT0_W1C_MASK | DWC2_HPRT0_PRTRST);
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001207
1208 for (i = 0; i < MAX_DEVICE; i++) {
Stefan Brüns081dcc72016-01-23 01:42:25 +01001209 for (j = 0; j < MAX_ENDPOINT; j++) {
1210 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1211 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1212 }
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001213 }
1214
Stefan Roesec526e832016-05-06 13:53:37 +02001215 /*
1216 * Add a 1 second delay here. This gives the host controller
1217 * a bit time before the comminucation with the USB devices
1218 * is started (the bus is scanned) and fixes the USB detection
1219 * problems with some problematic USB keys.
1220 */
1221 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1222 mdelay(1000);
1223
Patrick Delaunayce17fe12020-04-27 15:30:01 +02001224 printf("USB DWC2\n");
1225
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001226 return 0;
1227}
1228
Simon Glasse3c23a02015-07-07 20:53:36 -06001229static void dwc2_uninit_common(struct dwc2_core_regs *regs)
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001230{
1231 /* Put everything in reset. */
Teik Heng Chong9715f3c2023-06-21 11:13:58 +08001232 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTRST);
Simon Glasse3c23a02015-07-07 20:53:36 -06001233}
1234
Sven Schwermer8a3cb9f12018-11-21 08:43:56 +01001235#if !CONFIG_IS_ENABLED(DM_USB)
Simon Glasse3c23a02015-07-07 20:53:36 -06001236int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1237 int len, struct devrequest *setup)
1238{
1239 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1240}
1241
1242int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1243 int len)
1244{
1245 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1246}
1247
1248int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
Michal Suchanek1c95b9f2019-08-18 10:55:27 +02001249 int len, int interval, bool nonblock)
Simon Glasse3c23a02015-07-07 20:53:36 -06001250{
Michal Suchanek1c95b9f2019-08-18 10:55:27 +02001251 return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
1252 nonblock);
Simon Glasse3c23a02015-07-07 20:53:36 -06001253}
1254
1255/* U-Boot USB control interface */
1256int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1257{
1258 struct dwc2_priv *priv = &local;
1259
1260 memset(priv, '\0', sizeof(*priv));
1261 priv->root_hub_devnum = 0;
1262 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1263 priv->aligned_buffer = aligned_buffer_addr;
1264 priv->status_buffer = status_buffer_addr;
1265
1266 /* board-dependant init */
1267 if (board_usb_init(index, USB_INIT_HOST))
1268 return -1;
1269
Kever Yang327c24d2017-03-10 12:05:14 +08001270 return dwc2_init_common(NULL, priv);
Simon Glasse3c23a02015-07-07 20:53:36 -06001271}
1272
1273int usb_lowlevel_stop(int index)
1274{
1275 dwc2_uninit_common(local.regs);
1276
Oleksandr Tymoshenko7a881752014-02-01 21:51:25 -07001277 return 0;
1278}
Simon Glassa7ea72c2015-07-07 20:53:37 -06001279#endif
1280
Sven Schwermer8a3cb9f12018-11-21 08:43:56 +01001281#if CONFIG_IS_ENABLED(DM_USB)
Simon Glassa7ea72c2015-07-07 20:53:37 -06001282static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1283 unsigned long pipe, void *buffer, int length,
1284 struct devrequest *setup)
1285{
1286 struct dwc2_priv *priv = dev_get_priv(dev);
1287
1288 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1289 dev->name, udev, udev->dev->name, udev->portnr);
1290
1291 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1292}
1293
1294static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1295 unsigned long pipe, void *buffer, int length)
1296{
1297 struct dwc2_priv *priv = dev_get_priv(dev);
1298
1299 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1300
1301 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1302}
1303
1304static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1305 unsigned long pipe, void *buffer, int length,
Michal Suchanek1c95b9f2019-08-18 10:55:27 +02001306 int interval, bool nonblock)
Simon Glassa7ea72c2015-07-07 20:53:37 -06001307{
1308 struct dwc2_priv *priv = dev_get_priv(dev);
1309
1310 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1311
Michal Suchanek1c95b9f2019-08-18 10:55:27 +02001312 return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
1313 nonblock);
Simon Glassa7ea72c2015-07-07 20:53:37 -06001314}
1315
Simon Glassaad29ae2020-12-03 16:55:21 -07001316static int dwc2_usb_of_to_plat(struct udevice *dev)
Simon Glassa7ea72c2015-07-07 20:53:37 -06001317{
1318 struct dwc2_priv *priv = dev_get_priv(dev);
Simon Glassa7ea72c2015-07-07 20:53:37 -06001319
Sean Anderson62eff9b2020-09-15 10:45:15 -04001320 priv->regs = dev_read_addr_ptr(dev);
1321 if (!priv->regs)
Simon Glassa7ea72c2015-07-07 20:53:37 -06001322 return -EINVAL;
Simon Glassa7ea72c2015-07-07 20:53:37 -06001323
Meng Dongyang697a8bc2017-06-28 19:22:43 +08001324 priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1325 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
Meng Dongyangcc3fe062017-06-08 15:34:20 +08001326
Simon Glassa7ea72c2015-07-07 20:53:37 -06001327 return 0;
1328}
1329
Patrick Delaunaybb3569d2020-04-27 15:29:58 +02001330static int dwc2_setup_phy(struct udevice *dev)
1331{
1332 struct dwc2_priv *priv = dev_get_priv(dev);
1333 int ret;
1334
1335 ret = generic_phy_get_by_index(dev, 0, &priv->phy);
1336 if (ret) {
1337 if (ret == -ENOENT)
1338 return 0; /* no PHY, nothing to do */
1339 dev_err(dev, "Failed to get USB PHY: %d.\n", ret);
1340 return ret;
1341 }
1342
1343 ret = generic_phy_init(&priv->phy);
1344 if (ret) {
1345 dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret);
1346 return ret;
1347 }
1348
1349 ret = generic_phy_power_on(&priv->phy);
1350 if (ret) {
1351 dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret);
1352 generic_phy_exit(&priv->phy);
1353 return ret;
1354 }
1355
1356 return 0;
1357}
1358
1359static int dwc2_shutdown_phy(struct udevice *dev)
1360{
1361 struct dwc2_priv *priv = dev_get_priv(dev);
1362 int ret;
1363
1364 /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */
1365 if (!generic_phy_valid(&priv->phy))
1366 return 0; /* no PHY, nothing to do */
1367
1368 ret = generic_phy_power_off(&priv->phy);
1369 if (ret) {
1370 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1371 return ret;
1372 }
1373
1374 ret = generic_phy_exit(&priv->phy);
1375 if (ret) {
1376 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1377 return ret;
1378 }
1379
1380 return 0;
1381}
1382
Patrick Delaunay9225f3e2020-04-27 15:29:59 +02001383static int dwc2_clk_init(struct udevice *dev)
1384{
1385 struct dwc2_priv *priv = dev_get_priv(dev);
1386 int ret;
1387
1388 ret = clk_get_bulk(dev, &priv->clks);
1389 if (ret == -ENOSYS || ret == -ENOENT)
1390 return 0;
1391 if (ret)
1392 return ret;
1393
1394 ret = clk_enable_bulk(&priv->clks);
1395 if (ret) {
1396 clk_release_bulk(&priv->clks);
1397 return ret;
1398 }
1399
1400 return 0;
1401}
1402
Simon Glassa7ea72c2015-07-07 20:53:37 -06001403static int dwc2_usb_probe(struct udevice *dev)
1404{
1405 struct dwc2_priv *priv = dev_get_priv(dev);
Marek Vasut1ea9ac62016-04-26 03:02:35 +02001406 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
Patrick Delaunaybb3569d2020-04-27 15:29:58 +02001407 int ret;
Marek Vasut1ea9ac62016-04-26 03:02:35 +02001408
1409 bus_priv->desc_before_addr = true;
Simon Glassa7ea72c2015-07-07 20:53:37 -06001410
Patrick Delaunay9225f3e2020-04-27 15:29:59 +02001411 ret = dwc2_clk_init(dev);
1412 if (ret)
1413 return ret;
1414
Patrick Delaunaybb3569d2020-04-27 15:29:58 +02001415 ret = dwc2_setup_phy(dev);
1416 if (ret)
1417 return ret;
1418
Kever Yang327c24d2017-03-10 12:05:14 +08001419 return dwc2_init_common(dev, priv);
Simon Glassa7ea72c2015-07-07 20:53:37 -06001420}
1421
1422static int dwc2_usb_remove(struct udevice *dev)
1423{
1424 struct dwc2_priv *priv = dev_get_priv(dev);
Christophe Kerellof2a5a0b2018-03-15 18:00:30 +01001425 int ret;
1426
1427 ret = dwc_vbus_supply_exit(dev);
1428 if (ret)
1429 return ret;
Simon Glassa7ea72c2015-07-07 20:53:37 -06001430
Patrick Delaunaybb3569d2020-04-27 15:29:58 +02001431 ret = dwc2_shutdown_phy(dev);
1432 if (ret) {
1433 dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret);
1434 return ret;
1435 }
1436
Simon Glassa7ea72c2015-07-07 20:53:37 -06001437 dwc2_uninit_common(priv->regs);
1438
Ley Foon Tan23865562018-08-29 00:08:48 +08001439 reset_release_bulk(&priv->resets);
Patrick Delaunay9225f3e2020-04-27 15:29:59 +02001440 clk_disable_bulk(&priv->clks);
1441 clk_release_bulk(&priv->clks);
Ley Foon Tan23865562018-08-29 00:08:48 +08001442
Simon Glassa7ea72c2015-07-07 20:53:37 -06001443 return 0;
1444}
1445
1446struct dm_usb_ops dwc2_usb_ops = {
1447 .control = dwc2_submit_control_msg,
1448 .bulk = dwc2_submit_bulk_msg,
1449 .interrupt = dwc2_submit_int_msg,
1450};
1451
1452static const struct udevice_id dwc2_usb_ids[] = {
1453 { .compatible = "brcm,bcm2835-usb" },
Emmanuel Vadot80447002018-07-02 14:34:23 +02001454 { .compatible = "brcm,bcm2708-usb" },
Marek Vasutac4a35f2015-08-12 22:19:14 +02001455 { .compatible = "snps,dwc2" },
Simon Glassa7ea72c2015-07-07 20:53:37 -06001456 { }
1457};
1458
1459U_BOOT_DRIVER(usb_dwc2) = {
Marek Vasutaf83c782015-08-12 22:19:15 +02001460 .name = "dwc2_usb",
Simon Glassa7ea72c2015-07-07 20:53:37 -06001461 .id = UCLASS_USB,
1462 .of_match = dwc2_usb_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -07001463 .of_to_plat = dwc2_usb_of_to_plat,
Simon Glassa7ea72c2015-07-07 20:53:37 -06001464 .probe = dwc2_usb_probe,
1465 .remove = dwc2_usb_remove,
1466 .ops = &dwc2_usb_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -07001467 .priv_auto = sizeof(struct dwc2_priv),
Simon Glassa7ea72c2015-07-07 20:53:37 -06001468 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1469};
1470#endif