Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 2 | /* |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 3 | * Copyright (C) 2021 Waymo LLC |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 4 | * Copyright (C) 2011 Michal Simek <monstr@monstr.eu> |
| 5 | * Copyright (C) 2011 PetaLogix |
| 6 | * Copyright (C) 2010 Xilinx, Inc. All rights reserved. |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <config.h> |
| 10 | #include <common.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 11 | #include <cpu_func.h> |
Simon Glass | 1ab1692 | 2022-07-31 12:28:48 -0600 | [diff] [blame] | 12 | #include <display_options.h> |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 13 | #include <dm.h> |
Venkatesh Yadav Abbarapu | 1bbe450 | 2022-09-29 10:26:05 +0530 | [diff] [blame] | 14 | #include <dm/device_compat.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 15 | #include <log.h> |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 16 | #include <net.h> |
| 17 | #include <malloc.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 18 | #include <asm/global_data.h> |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 19 | #include <asm/io.h> |
| 20 | #include <phy.h> |
| 21 | #include <miiphy.h> |
Siva Durga Prasad Paladugu | 2063362 | 2017-01-06 16:18:50 +0530 | [diff] [blame] | 22 | #include <wait_bit.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 23 | #include <linux/delay.h> |
T Karthik Reddy | 4a3f40b | 2022-05-10 13:26:09 +0200 | [diff] [blame] | 24 | #include <eth_phy.h> |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 25 | |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 26 | DECLARE_GLOBAL_DATA_PTR; |
| 27 | |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 28 | /* Link setup */ |
| 29 | #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ |
| 30 | #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ |
| 31 | #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ |
| 32 | #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ |
| 33 | |
| 34 | /* Interrupt Status/Enable/Mask Registers bit definitions */ |
| 35 | #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ |
| 36 | #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ |
| 37 | |
| 38 | /* Receive Configuration Word 1 (RCW1) Register bit definitions */ |
| 39 | #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */ |
| 40 | |
| 41 | /* Transmitter Configuration (TC) Register bit definitions */ |
| 42 | #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */ |
| 43 | |
| 44 | #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF |
| 45 | |
| 46 | /* MDIO Management Configuration (MC) Register bit definitions */ |
| 47 | #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/ |
| 48 | |
| 49 | /* MDIO Management Control Register (MCR) Register bit definitions */ |
| 50 | #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */ |
| 51 | #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */ |
| 52 | #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */ |
| 53 | #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */ |
| 54 | #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */ |
| 55 | #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */ |
| 56 | #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */ |
| 57 | #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */ |
| 58 | |
| 59 | #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */ |
| 60 | |
Siva Durga Prasad Paladugu | f802603 | 2017-01-06 16:27:15 +0530 | [diff] [blame] | 61 | #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */ |
| 62 | |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 63 | /* DMA macros */ |
| 64 | /* Bitmasks of XAXIDMA_CR_OFFSET register */ |
| 65 | #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */ |
| 66 | #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ |
| 67 | |
| 68 | /* Bitmasks of XAXIDMA_SR_OFFSET register */ |
| 69 | #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */ |
| 70 | |
| 71 | /* Bitmask for interrupts */ |
| 72 | #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */ |
| 73 | #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ |
| 74 | #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */ |
| 75 | |
| 76 | /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */ |
| 77 | #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ |
| 78 | #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ |
| 79 | |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 80 | /* Bitmasks for XXV Ethernet MAC */ |
| 81 | #define XXV_TC_TX_MASK 0x00000001 |
| 82 | #define XXV_TC_FCS_MASK 0x00000002 |
| 83 | #define XXV_RCW1_RX_MASK 0x00000001 |
| 84 | #define XXV_RCW1_FCS_MASK 0x00000002 |
| 85 | |
| 86 | #define DMAALIGN 128 |
| 87 | #define XXV_MIN_PKT_SIZE 60 |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 88 | |
| 89 | static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 90 | static u8 txminframe[XXV_MIN_PKT_SIZE] __attribute((aligned(DMAALIGN))); |
| 91 | |
| 92 | enum emac_variant { |
| 93 | EMAC_1G = 0, |
| 94 | EMAC_10G_25G = 1, |
| 95 | }; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 96 | |
| 97 | /* Reflect dma offsets */ |
| 98 | struct axidma_reg { |
| 99 | u32 control; /* DMACR */ |
| 100 | u32 status; /* DMASR */ |
Vipul Kumar | 3b06a0f | 2018-01-23 14:52:35 +0530 | [diff] [blame] | 101 | u32 current; /* CURDESC low 32 bit */ |
| 102 | u32 current_hi; /* CURDESC high 32 bit */ |
| 103 | u32 tail; /* TAILDESC low 32 bit */ |
| 104 | u32 tail_hi; /* TAILDESC high 32 bit */ |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 105 | }; |
| 106 | |
Ashok Reddy Soma | 3c4df95 | 2021-06-24 00:34:40 -0600 | [diff] [blame] | 107 | /* Platform data structures */ |
| 108 | struct axidma_plat { |
| 109 | struct eth_pdata eth_pdata; |
| 110 | struct axidma_reg *dmatx; |
| 111 | struct axidma_reg *dmarx; |
Andy Chiu | 58af7eb | 2022-11-01 11:57:59 +0800 | [diff] [blame] | 112 | int pcsaddr; |
Ashok Reddy Soma | 3c4df95 | 2021-06-24 00:34:40 -0600 | [diff] [blame] | 113 | int phyaddr; |
| 114 | u8 eth_hasnobuf; |
Maxim Kochetkov | 61cd6fd | 2023-08-11 10:43:51 +0300 | [diff] [blame] | 115 | ofnode phynode; |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 116 | enum emac_variant mactype; |
Ashok Reddy Soma | 3c4df95 | 2021-06-24 00:34:40 -0600 | [diff] [blame] | 117 | }; |
| 118 | |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 119 | /* Private driver structures */ |
| 120 | struct axidma_priv { |
| 121 | struct axidma_reg *dmatx; |
| 122 | struct axidma_reg *dmarx; |
Andy Chiu | 58af7eb | 2022-11-01 11:57:59 +0800 | [diff] [blame] | 123 | int pcsaddr; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 124 | int phyaddr; |
Michal Simek | 6cb55e7 | 2015-12-09 14:39:42 +0100 | [diff] [blame] | 125 | struct axi_regs *iobase; |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 126 | phy_interface_t interface; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 127 | struct phy_device *phydev; |
| 128 | struct mii_dev *bus; |
Siva Durga Prasad Paladugu | f802603 | 2017-01-06 16:27:15 +0530 | [diff] [blame] | 129 | u8 eth_hasnobuf; |
Maxim Kochetkov | 61cd6fd | 2023-08-11 10:43:51 +0300 | [diff] [blame] | 130 | ofnode phynode; |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 131 | enum emac_variant mactype; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 132 | }; |
| 133 | |
| 134 | /* BD descriptors */ |
| 135 | struct axidma_bd { |
Ashok Reddy Soma | 91d455a | 2020-09-03 08:36:43 -0600 | [diff] [blame] | 136 | u32 next_desc; /* Next descriptor pointer */ |
| 137 | u32 next_desc_msb; |
| 138 | u32 buf_addr; /* Buffer address */ |
| 139 | u32 buf_addr_msb; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 140 | u32 reserved3; |
| 141 | u32 reserved4; |
| 142 | u32 cntrl; /* Control */ |
| 143 | u32 status; /* Status */ |
| 144 | u32 app0; |
| 145 | u32 app1; /* TX start << 16 | insert */ |
| 146 | u32 app2; /* TX csum seed */ |
| 147 | u32 app3; |
| 148 | u32 app4; |
| 149 | u32 sw_id_offset; |
| 150 | u32 reserved5; |
| 151 | u32 reserved6; |
| 152 | }; |
| 153 | |
| 154 | /* Static BDs - driver uses only one BD */ |
| 155 | static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN))); |
| 156 | static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN))); |
| 157 | |
| 158 | struct axi_regs { |
| 159 | u32 reserved[3]; |
| 160 | u32 is; /* 0xC: Interrupt status */ |
| 161 | u32 reserved2; |
| 162 | u32 ie; /* 0x14: Interrupt enable */ |
| 163 | u32 reserved3[251]; |
| 164 | u32 rcw1; /* 0x404: Rx Configuration Word 1 */ |
| 165 | u32 tc; /* 0x408: Tx Configuration */ |
| 166 | u32 reserved4; |
| 167 | u32 emmc; /* 0x410: EMAC mode configuration */ |
| 168 | u32 reserved5[59]; |
| 169 | u32 mdio_mc; /* 0x500: MII Management Config */ |
| 170 | u32 mdio_mcr; /* 0x504: MII Management Control */ |
| 171 | u32 mdio_mwd; /* 0x508: MII Management Write Data */ |
| 172 | u32 mdio_mrd; /* 0x50C: MII Management Read Data */ |
| 173 | u32 reserved6[124]; |
| 174 | u32 uaw0; /* 0x700: Unicast address word 0 */ |
| 175 | u32 uaw1; /* 0x704: Unicast address word 1 */ |
| 176 | }; |
| 177 | |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 178 | struct xxv_axi_regs { |
| 179 | u32 gt_reset; /* 0x0 */ |
| 180 | u32 reserved[2]; |
| 181 | u32 tc; /* 0xC: Tx Configuration */ |
| 182 | u32 reserved2; |
| 183 | u32 rcw1; /* 0x14: Rx Configuration Word 1 */ |
| 184 | }; |
| 185 | |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 186 | /* Use MII register 1 (MII status register) to detect PHY */ |
| 187 | #define PHY_DETECT_REG 1 |
| 188 | |
| 189 | /* |
| 190 | * Mask used to verify certain PHY features (or register contents) |
| 191 | * in the register above: |
| 192 | * 0x1000: 10Mbps full duplex support |
| 193 | * 0x0800: 10Mbps half duplex support |
| 194 | * 0x0008: Auto-negotiation support |
| 195 | */ |
| 196 | #define PHY_DETECT_MASK 0x1808 |
| 197 | |
Michal Simek | f522187 | 2015-12-09 14:36:31 +0100 | [diff] [blame] | 198 | static inline int mdio_wait(struct axi_regs *regs) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 199 | { |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 200 | u32 timeout = 200; |
| 201 | |
| 202 | /* Wait till MDIO interface is ready to accept a new transaction. */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 203 | while (timeout && (!(readl(®s->mdio_mcr) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 204 | & XAE_MDIO_MCR_READY_MASK))) { |
| 205 | timeout--; |
| 206 | udelay(1); |
| 207 | } |
| 208 | if (!timeout) { |
| 209 | printf("%s: Timeout\n", __func__); |
| 210 | return 1; |
| 211 | } |
| 212 | return 0; |
| 213 | } |
| 214 | |
Vipul Kumar | 3b06a0f | 2018-01-23 14:52:35 +0530 | [diff] [blame] | 215 | /** |
| 216 | * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write. |
| 217 | * @bd: pointer to BD descriptor structure |
| 218 | * @desc: Address offset of DMA descriptors |
| 219 | * |
| 220 | * This function writes the value into the corresponding Axi DMA register. |
| 221 | */ |
| 222 | static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc) |
| 223 | { |
| 224 | #if defined(CONFIG_PHYS_64BIT) |
Ashok Reddy Soma | 91d455a | 2020-09-03 08:36:43 -0600 | [diff] [blame] | 225 | writeq((unsigned long)bd, desc); |
Vipul Kumar | 3b06a0f | 2018-01-23 14:52:35 +0530 | [diff] [blame] | 226 | #else |
| 227 | writel((u32)bd, desc); |
| 228 | #endif |
| 229 | } |
| 230 | |
Michal Simek | 41beca1 | 2015-12-09 14:44:38 +0100 | [diff] [blame] | 231 | static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum, |
| 232 | u16 *val) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 233 | { |
Michal Simek | 41beca1 | 2015-12-09 14:44:38 +0100 | [diff] [blame] | 234 | struct axi_regs *regs = priv->iobase; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 235 | u32 mdioctrlreg = 0; |
| 236 | |
Michal Simek | f522187 | 2015-12-09 14:36:31 +0100 | [diff] [blame] | 237 | if (mdio_wait(regs)) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 238 | return 1; |
| 239 | |
| 240 | mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & |
| 241 | XAE_MDIO_MCR_PHYAD_MASK) | |
| 242 | ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) |
| 243 | & XAE_MDIO_MCR_REGAD_MASK) | |
| 244 | XAE_MDIO_MCR_INITIATE_MASK | |
| 245 | XAE_MDIO_MCR_OP_READ_MASK; |
| 246 | |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 247 | writel(mdioctrlreg, ®s->mdio_mcr); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 248 | |
Michal Simek | f522187 | 2015-12-09 14:36:31 +0100 | [diff] [blame] | 249 | if (mdio_wait(regs)) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 250 | return 1; |
| 251 | |
| 252 | /* Read data */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 253 | *val = readl(®s->mdio_mrd); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 254 | return 0; |
| 255 | } |
| 256 | |
Michal Simek | 41beca1 | 2015-12-09 14:44:38 +0100 | [diff] [blame] | 257 | static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum, |
| 258 | u32 data) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 259 | { |
Michal Simek | 41beca1 | 2015-12-09 14:44:38 +0100 | [diff] [blame] | 260 | struct axi_regs *regs = priv->iobase; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 261 | u32 mdioctrlreg = 0; |
| 262 | |
Michal Simek | f522187 | 2015-12-09 14:36:31 +0100 | [diff] [blame] | 263 | if (mdio_wait(regs)) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 264 | return 1; |
| 265 | |
| 266 | mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & |
| 267 | XAE_MDIO_MCR_PHYAD_MASK) | |
| 268 | ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) |
| 269 | & XAE_MDIO_MCR_REGAD_MASK) | |
| 270 | XAE_MDIO_MCR_INITIATE_MASK | |
| 271 | XAE_MDIO_MCR_OP_WRITE_MASK; |
| 272 | |
| 273 | /* Write data */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 274 | writel(data, ®s->mdio_mwd); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 275 | |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 276 | writel(mdioctrlreg, ®s->mdio_mcr); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 277 | |
Michal Simek | f522187 | 2015-12-09 14:36:31 +0100 | [diff] [blame] | 278 | if (mdio_wait(regs)) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 279 | return 1; |
| 280 | |
| 281 | return 0; |
| 282 | } |
| 283 | |
Michal Simek | 0b13ee2 | 2015-12-08 16:10:05 +0100 | [diff] [blame] | 284 | static int axiemac_phy_init(struct udevice *dev) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 285 | { |
| 286 | u16 phyreg; |
Patrick van Gelder | 70ab943 | 2020-06-03 14:18:04 +0200 | [diff] [blame] | 287 | int i; |
| 288 | u32 ret; |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 289 | struct axidma_priv *priv = dev_get_priv(dev); |
Michal Simek | 6cb55e7 | 2015-12-09 14:39:42 +0100 | [diff] [blame] | 290 | struct axi_regs *regs = priv->iobase; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 291 | struct phy_device *phydev; |
| 292 | |
| 293 | u32 supported = SUPPORTED_10baseT_Half | |
| 294 | SUPPORTED_10baseT_Full | |
| 295 | SUPPORTED_100baseT_Half | |
| 296 | SUPPORTED_100baseT_Full | |
| 297 | SUPPORTED_1000baseT_Half | |
| 298 | SUPPORTED_1000baseT_Full; |
| 299 | |
Michal Simek | 0b13ee2 | 2015-12-08 16:10:05 +0100 | [diff] [blame] | 300 | /* Set default MDIO divisor */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 301 | writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc); |
Michal Simek | 0b13ee2 | 2015-12-08 16:10:05 +0100 | [diff] [blame] | 302 | |
T Karthik Reddy | 4a3f40b | 2022-05-10 13:26:09 +0200 | [diff] [blame] | 303 | if (IS_ENABLED(CONFIG_DM_ETH_PHY)) |
| 304 | priv->phyaddr = eth_phy_get_addr(dev); |
| 305 | |
Andy Chiu | 58af7eb | 2022-11-01 11:57:59 +0800 | [diff] [blame] | 306 | /* |
| 307 | * Set address of PCS/PMA PHY to the one pointed by phy-handle for |
| 308 | * backward compatibility. |
| 309 | */ |
| 310 | if (priv->phyaddr != -1 && priv->pcsaddr == 0) |
| 311 | priv->pcsaddr = priv->phyaddr; |
| 312 | |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 313 | if (priv->phyaddr == -1) { |
| 314 | /* Detect the PHY address */ |
| 315 | for (i = 31; i >= 0; i--) { |
Michal Simek | 41beca1 | 2015-12-09 14:44:38 +0100 | [diff] [blame] | 316 | ret = phyread(priv, i, PHY_DETECT_REG, &phyreg); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 317 | if (!ret && (phyreg != 0xFFFF) && |
| 318 | ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { |
| 319 | /* Found a valid PHY address */ |
| 320 | priv->phyaddr = i; |
| 321 | debug("axiemac: Found valid phy address, %x\n", |
Michal Simek | 2f1e065 | 2015-12-09 10:54:53 +0100 | [diff] [blame] | 322 | i); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 323 | break; |
| 324 | } |
| 325 | } |
| 326 | } |
| 327 | |
| 328 | /* Interface - look at tsec */ |
Siva Durga Prasad Paladugu | 4934851 | 2016-02-21 15:46:14 +0530 | [diff] [blame] | 329 | phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); |
Venkatesh Yadav Abbarapu | 1bbe450 | 2022-09-29 10:26:05 +0530 | [diff] [blame] | 330 | if (IS_ERR_OR_NULL(phydev)) { |
| 331 | dev_err(dev, "phy_connect() failed\n"); |
| 332 | return -ENODEV; |
| 333 | } |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 334 | |
| 335 | phydev->supported &= supported; |
| 336 | phydev->advertising = phydev->supported; |
| 337 | priv->phydev = phydev; |
Maxim Kochetkov | 61cd6fd | 2023-08-11 10:43:51 +0300 | [diff] [blame] | 338 | if (ofnode_valid(priv->phynode)) |
| 339 | priv->phydev->node = priv->phynode; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 340 | phy_config(phydev); |
Michal Simek | 0b13ee2 | 2015-12-08 16:10:05 +0100 | [diff] [blame] | 341 | |
| 342 | return 0; |
| 343 | } |
| 344 | |
Andy Chiu | 8144a2a | 2022-11-01 11:58:00 +0800 | [diff] [blame] | 345 | static int pcs_pma_startup(struct axidma_priv *priv) |
| 346 | { |
| 347 | u32 rc, retry_cnt = 0; |
| 348 | u16 mii_reg; |
| 349 | |
| 350 | rc = phyread(priv, priv->pcsaddr, MII_BMCR, &mii_reg); |
| 351 | if (rc) |
| 352 | goto failed_mdio; |
| 353 | |
| 354 | if (!(mii_reg & BMCR_ANENABLE)) { |
| 355 | mii_reg |= BMCR_ANENABLE; |
| 356 | if (phywrite(priv, priv->pcsaddr, MII_BMCR, mii_reg)) |
| 357 | goto failed_mdio; |
| 358 | } |
| 359 | |
| 360 | /* |
| 361 | * Check the internal PHY status and warn user if the link between it |
| 362 | * and the external PHY is not obtained. |
| 363 | */ |
| 364 | debug("axiemac: waiting for link status of the PCS/PMA PHY"); |
| 365 | while (retry_cnt * 10 < PHY_ANEG_TIMEOUT) { |
| 366 | rc = phyread(priv, priv->pcsaddr, MII_BMSR, &mii_reg); |
| 367 | if ((mii_reg & BMSR_LSTATUS) && mii_reg != 0xffff && !rc) { |
| 368 | debug(".Done\n"); |
| 369 | return 0; |
| 370 | } |
| 371 | if ((retry_cnt++ % 10) == 0) |
| 372 | debug("."); |
| 373 | mdelay(10); |
| 374 | } |
| 375 | debug("\n"); |
| 376 | printf("axiemac: Warning, PCS/PMA PHY@%d is not ready, link is down\n", |
| 377 | priv->pcsaddr); |
| 378 | return 1; |
| 379 | failed_mdio: |
| 380 | printf("axiemac: MDIO to the PCS/PMA PHY has failed\n"); |
| 381 | return 1; |
| 382 | } |
| 383 | |
Michal Simek | 0b13ee2 | 2015-12-08 16:10:05 +0100 | [diff] [blame] | 384 | /* Setting axi emac and phy to proper setting */ |
| 385 | static int setup_phy(struct udevice *dev) |
| 386 | { |
Siva Durga Prasad Paladugu | a1c6ed8 | 2016-02-21 15:46:15 +0530 | [diff] [blame] | 387 | u16 temp; |
| 388 | u32 speed, emmc_reg, ret; |
Michal Simek | 0b13ee2 | 2015-12-08 16:10:05 +0100 | [diff] [blame] | 389 | struct axidma_priv *priv = dev_get_priv(dev); |
| 390 | struct axi_regs *regs = priv->iobase; |
| 391 | struct phy_device *phydev = priv->phydev; |
| 392 | |
Siva Durga Prasad Paladugu | a1c6ed8 | 2016-02-21 15:46:15 +0530 | [diff] [blame] | 393 | if (priv->interface == PHY_INTERFACE_MODE_SGMII) { |
| 394 | /* |
| 395 | * In SGMII cases the isolate bit might set |
| 396 | * after DMA and ethernet resets and hence |
| 397 | * check and clear if set. |
| 398 | */ |
Andy Chiu | 58af7eb | 2022-11-01 11:57:59 +0800 | [diff] [blame] | 399 | ret = phyread(priv, priv->pcsaddr, MII_BMCR, &temp); |
Siva Durga Prasad Paladugu | a1c6ed8 | 2016-02-21 15:46:15 +0530 | [diff] [blame] | 400 | if (ret) |
| 401 | return 0; |
| 402 | if (temp & BMCR_ISOLATE) { |
| 403 | temp &= ~BMCR_ISOLATE; |
Andy Chiu | 58af7eb | 2022-11-01 11:57:59 +0800 | [diff] [blame] | 404 | ret = phywrite(priv, priv->pcsaddr, MII_BMCR, temp); |
Siva Durga Prasad Paladugu | a1c6ed8 | 2016-02-21 15:46:15 +0530 | [diff] [blame] | 405 | if (ret) |
| 406 | return 0; |
| 407 | } |
| 408 | } |
| 409 | |
Timur Tabi | 4238746 | 2012-07-09 08:52:43 +0000 | [diff] [blame] | 410 | if (phy_startup(phydev)) { |
| 411 | printf("axiemac: could not initialize PHY %s\n", |
| 412 | phydev->dev->name); |
| 413 | return 0; |
| 414 | } |
Andy Chiu | 8144a2a | 2022-11-01 11:58:00 +0800 | [diff] [blame] | 415 | if (priv->interface == PHY_INTERFACE_MODE_SGMII || |
| 416 | priv->interface == PHY_INTERFACE_MODE_1000BASEX) { |
| 417 | if (pcs_pma_startup(priv)) |
| 418 | return 0; |
| 419 | } |
Michal Simek | 5848f13 | 2013-11-21 16:15:51 +0100 | [diff] [blame] | 420 | if (!phydev->link) { |
| 421 | printf("%s: No link.\n", phydev->dev->name); |
| 422 | return 0; |
| 423 | } |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 424 | |
| 425 | switch (phydev->speed) { |
| 426 | case 1000: |
| 427 | speed = XAE_EMMC_LINKSPD_1000; |
| 428 | break; |
| 429 | case 100: |
| 430 | speed = XAE_EMMC_LINKSPD_100; |
| 431 | break; |
| 432 | case 10: |
| 433 | speed = XAE_EMMC_LINKSPD_10; |
| 434 | break; |
| 435 | default: |
| 436 | return 0; |
| 437 | } |
| 438 | |
| 439 | /* Setup the emac for the phy speed */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 440 | emmc_reg = readl(®s->emmc); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 441 | emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK; |
| 442 | emmc_reg |= speed; |
| 443 | |
| 444 | /* Write new speed setting out to Axi Ethernet */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 445 | writel(emmc_reg, ®s->emmc); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 446 | |
| 447 | /* |
| 448 | * Setting the operating speed of the MAC needs a delay. There |
| 449 | * doesn't seem to be register to poll, so please consider this |
| 450 | * during your application design. |
| 451 | */ |
| 452 | udelay(1); |
| 453 | |
| 454 | return 1; |
| 455 | } |
| 456 | |
| 457 | /* STOP DMA transfers */ |
Michal Simek | 8fbf79f | 2015-12-16 09:18:12 +0100 | [diff] [blame] | 458 | static void axiemac_stop(struct udevice *dev) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 459 | { |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 460 | struct axidma_priv *priv = dev_get_priv(dev); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 461 | u32 temp; |
| 462 | |
| 463 | /* Stop the hardware */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 464 | temp = readl(&priv->dmatx->control); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 465 | temp &= ~XAXIDMA_CR_RUNSTOP_MASK; |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 466 | writel(temp, &priv->dmatx->control); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 467 | |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 468 | temp = readl(&priv->dmarx->control); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 469 | temp &= ~XAXIDMA_CR_RUNSTOP_MASK; |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 470 | writel(temp, &priv->dmarx->control); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 471 | |
| 472 | debug("axiemac: Halted\n"); |
| 473 | } |
| 474 | |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 475 | static int xxv_axi_ethernet_init(struct axidma_priv *priv) |
| 476 | { |
| 477 | struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase; |
| 478 | |
| 479 | writel(readl(®s->rcw1) | XXV_RCW1_FCS_MASK, ®s->rcw1); |
| 480 | writel(readl(®s->tc) | XXV_TC_FCS_MASK, ®s->tc); |
| 481 | writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc); |
| 482 | writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1); |
| 483 | |
| 484 | return 0; |
| 485 | } |
| 486 | |
Michal Simek | 638c0ef | 2015-12-09 14:53:51 +0100 | [diff] [blame] | 487 | static int axi_ethernet_init(struct axidma_priv *priv) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 488 | { |
Michal Simek | 638c0ef | 2015-12-09 14:53:51 +0100 | [diff] [blame] | 489 | struct axi_regs *regs = priv->iobase; |
Siva Durga Prasad Paladugu | 2063362 | 2017-01-06 16:18:50 +0530 | [diff] [blame] | 490 | int err; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 491 | |
| 492 | /* |
| 493 | * Check the status of the MgtRdy bit in the interrupt status |
| 494 | * registers. This must be done to allow the MGT clock to become stable |
| 495 | * for the Sgmii and 1000BaseX PHY interfaces. No other register reads |
| 496 | * will be valid until this bit is valid. |
| 497 | * The bit is always a 1 for all other PHY interfaces. |
Siva Durga Prasad Paladugu | f802603 | 2017-01-06 16:27:15 +0530 | [diff] [blame] | 498 | * Interrupt status and enable registers are not available in non |
| 499 | * processor mode and hence bypass in this mode |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 500 | */ |
Siva Durga Prasad Paladugu | f802603 | 2017-01-06 16:27:15 +0530 | [diff] [blame] | 501 | if (!priv->eth_hasnobuf) { |
Ălvaro FernĂĄndez Rojas | 918de03 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 502 | err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK, |
| 503 | true, 200, false); |
Siva Durga Prasad Paladugu | f802603 | 2017-01-06 16:27:15 +0530 | [diff] [blame] | 504 | if (err) { |
| 505 | printf("%s: Timeout\n", __func__); |
| 506 | return 1; |
| 507 | } |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 508 | |
Siva Durga Prasad Paladugu | f802603 | 2017-01-06 16:27:15 +0530 | [diff] [blame] | 509 | /* |
| 510 | * Stop the device and reset HW |
| 511 | * Disable interrupts |
| 512 | */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 513 | writel(0, ®s->ie); |
Siva Durga Prasad Paladugu | f802603 | 2017-01-06 16:27:15 +0530 | [diff] [blame] | 514 | } |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 515 | |
| 516 | /* Disable the receiver */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 517 | writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 518 | |
| 519 | /* |
| 520 | * Stopping the receiver in mid-packet causes a dropped packet |
| 521 | * indication from HW. Clear it. |
| 522 | */ |
Siva Durga Prasad Paladugu | f802603 | 2017-01-06 16:27:15 +0530 | [diff] [blame] | 523 | if (!priv->eth_hasnobuf) { |
| 524 | /* Set the interrupt status register to clear the interrupt */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 525 | writel(XAE_INT_RXRJECT_MASK, ®s->is); |
Siva Durga Prasad Paladugu | f802603 | 2017-01-06 16:27:15 +0530 | [diff] [blame] | 526 | } |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 527 | |
| 528 | /* Setup HW */ |
| 529 | /* Set default MDIO divisor */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 530 | writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 531 | |
| 532 | debug("axiemac: InitHw done\n"); |
| 533 | return 0; |
| 534 | } |
| 535 | |
Michal Simek | 8fbf79f | 2015-12-16 09:18:12 +0100 | [diff] [blame] | 536 | static int axiemac_write_hwaddr(struct udevice *dev) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 537 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 538 | struct eth_pdata *pdata = dev_get_plat(dev); |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 539 | struct axidma_priv *priv = dev_get_priv(dev); |
| 540 | struct axi_regs *regs = priv->iobase; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 541 | |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 542 | if (priv->mactype != EMAC_1G) |
| 543 | return 0; |
| 544 | |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 545 | /* Set the MAC address */ |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 546 | int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) | |
| 547 | (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0])); |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 548 | writel(val, ®s->uaw0); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 549 | |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 550 | val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4]; |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 551 | val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK; |
| 552 | writel(val, ®s->uaw1); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 553 | return 0; |
| 554 | } |
| 555 | |
| 556 | /* Reset DMA engine */ |
Michal Simek | 638c0ef | 2015-12-09 14:53:51 +0100 | [diff] [blame] | 557 | static void axi_dma_init(struct axidma_priv *priv) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 558 | { |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 559 | u32 timeout = 500; |
| 560 | |
| 561 | /* Reset the engine so the hardware starts from a known state */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 562 | writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control); |
| 563 | writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 564 | |
| 565 | /* At the initialization time, hardware should finish reset quickly */ |
| 566 | while (timeout--) { |
| 567 | /* Check transmit/receive channel */ |
| 568 | /* Reset is done when the reset bit is low */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 569 | if (!((readl(&priv->dmatx->control) | |
| 570 | readl(&priv->dmarx->control)) |
Michal Simek | 5aa4539 | 2015-10-28 11:00:47 +0100 | [diff] [blame] | 571 | & XAXIDMA_CR_RESET_MASK)) { |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 572 | break; |
| 573 | } |
| 574 | } |
| 575 | if (!timeout) |
| 576 | printf("%s: Timeout\n", __func__); |
| 577 | } |
| 578 | |
Michal Simek | 8fbf79f | 2015-12-16 09:18:12 +0100 | [diff] [blame] | 579 | static int axiemac_start(struct udevice *dev) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 580 | { |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 581 | struct axidma_priv *priv = dev_get_priv(dev); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 582 | u32 temp; |
| 583 | |
| 584 | debug("axiemac: Init started\n"); |
| 585 | /* |
| 586 | * Initialize AXIDMA engine. AXIDMA engine must be initialized before |
| 587 | * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is |
| 588 | * reset, and since AXIDMA reset line is connected to AxiEthernet, this |
| 589 | * would ensure a reset of AxiEthernet. |
| 590 | */ |
Michal Simek | 638c0ef | 2015-12-09 14:53:51 +0100 | [diff] [blame] | 591 | axi_dma_init(priv); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 592 | |
| 593 | /* Initialize AxiEthernet hardware. */ |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 594 | if (priv->mactype == EMAC_1G) { |
| 595 | if (axi_ethernet_init(priv)) |
| 596 | return -1; |
| 597 | } else { |
| 598 | if (xxv_axi_ethernet_init(priv)) |
| 599 | return -1; |
| 600 | } |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 601 | |
| 602 | /* Disable all RX interrupts before RxBD space setup */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 603 | temp = readl(&priv->dmarx->control); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 604 | temp &= ~XAXIDMA_IRQ_ALL_MASK; |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 605 | writel(temp, &priv->dmarx->control); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 606 | |
| 607 | /* Start DMA RX channel. Now it's ready to receive data.*/ |
Vipul Kumar | 3b06a0f | 2018-01-23 14:52:35 +0530 | [diff] [blame] | 608 | axienet_dma_write(&rx_bd, &priv->dmarx->current); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 609 | |
| 610 | /* Setup the BD. */ |
| 611 | memset(&rx_bd, 0, sizeof(rx_bd)); |
Ashok Reddy Soma | 91d455a | 2020-09-03 08:36:43 -0600 | [diff] [blame] | 612 | rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd); |
| 613 | rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe); |
| 614 | #if defined(CONFIG_PHYS_64BIT) |
| 615 | rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd); |
| 616 | rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe); |
| 617 | #endif |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 618 | rx_bd.cntrl = sizeof(rxframe); |
| 619 | /* Flush the last BD so DMA core could see the updates */ |
Ashok Reddy Soma | f29a570 | 2020-09-03 08:36:44 -0600 | [diff] [blame] | 620 | flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd)); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 621 | |
| 622 | /* It is necessary to flush rxframe because if you don't do it |
| 623 | * then cache can contain uninitialized data */ |
Ashok Reddy Soma | f29a570 | 2020-09-03 08:36:44 -0600 | [diff] [blame] | 624 | flush_cache((phys_addr_t)&rxframe, sizeof(rxframe)); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 625 | |
| 626 | /* Start the hardware */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 627 | temp = readl(&priv->dmarx->control); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 628 | temp |= XAXIDMA_CR_RUNSTOP_MASK; |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 629 | writel(temp, &priv->dmarx->control); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 630 | |
| 631 | /* Rx BD is ready - start */ |
Vipul Kumar | 3b06a0f | 2018-01-23 14:52:35 +0530 | [diff] [blame] | 632 | axienet_dma_write(&rx_bd, &priv->dmarx->tail); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 633 | |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 634 | if (priv->mactype == EMAC_1G) { |
| 635 | struct axi_regs *regs = priv->iobase; |
| 636 | /* Enable TX */ |
| 637 | writel(XAE_TC_TX_MASK, ®s->tc); |
| 638 | /* Enable RX */ |
| 639 | writel(XAE_RCW1_RX_MASK, ®s->rcw1); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 640 | |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 641 | /* PHY setup */ |
| 642 | if (!setup_phy(dev)) { |
| 643 | axiemac_stop(dev); |
| 644 | return -1; |
| 645 | } |
| 646 | } else { |
| 647 | struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase; |
| 648 | /* Enable TX */ |
| 649 | writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc); |
| 650 | |
| 651 | /* Enable RX */ |
| 652 | writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 653 | } |
| 654 | |
| 655 | debug("axiemac: Init complete\n"); |
| 656 | return 0; |
| 657 | } |
| 658 | |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 659 | static int axiemac_send(struct udevice *dev, void *ptr, int len) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 660 | { |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 661 | struct axidma_priv *priv = dev_get_priv(dev); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 662 | u32 timeout; |
| 663 | |
| 664 | if (len > PKTSIZE_ALIGN) |
| 665 | len = PKTSIZE_ALIGN; |
| 666 | |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 667 | /* If size is less than min packet size, pad to min size */ |
| 668 | if (priv->mactype == EMAC_10G_25G && len < XXV_MIN_PKT_SIZE) { |
| 669 | memset(txminframe, 0, XXV_MIN_PKT_SIZE); |
| 670 | memcpy(txminframe, ptr, len); |
| 671 | len = XXV_MIN_PKT_SIZE; |
| 672 | ptr = txminframe; |
| 673 | } |
| 674 | |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 675 | /* Flush packet to main memory to be trasfered by DMA */ |
Ashok Reddy Soma | f29a570 | 2020-09-03 08:36:44 -0600 | [diff] [blame] | 676 | flush_cache((phys_addr_t)ptr, len); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 677 | |
| 678 | /* Setup Tx BD */ |
| 679 | memset(&tx_bd, 0, sizeof(tx_bd)); |
| 680 | /* At the end of the ring, link the last BD back to the top */ |
Ashok Reddy Soma | 91d455a | 2020-09-03 08:36:43 -0600 | [diff] [blame] | 681 | tx_bd.next_desc = lower_32_bits((unsigned long)&tx_bd); |
| 682 | tx_bd.buf_addr = lower_32_bits((unsigned long)ptr); |
| 683 | #if defined(CONFIG_PHYS_64BIT) |
| 684 | tx_bd.next_desc_msb = upper_32_bits((unsigned long)&tx_bd); |
| 685 | tx_bd.buf_addr_msb = upper_32_bits((unsigned long)ptr); |
| 686 | #endif |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 687 | /* Save len */ |
| 688 | tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK | |
| 689 | XAXIDMA_BD_CTRL_TXEOF_MASK; |
| 690 | |
| 691 | /* Flush the last BD so DMA core could see the updates */ |
Ashok Reddy Soma | f29a570 | 2020-09-03 08:36:44 -0600 | [diff] [blame] | 692 | flush_cache((phys_addr_t)&tx_bd, sizeof(tx_bd)); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 693 | |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 694 | if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) { |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 695 | u32 temp; |
Vipul Kumar | 3b06a0f | 2018-01-23 14:52:35 +0530 | [diff] [blame] | 696 | axienet_dma_write(&tx_bd, &priv->dmatx->current); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 697 | /* Start the hardware */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 698 | temp = readl(&priv->dmatx->control); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 699 | temp |= XAXIDMA_CR_RUNSTOP_MASK; |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 700 | writel(temp, &priv->dmatx->control); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 701 | } |
| 702 | |
| 703 | /* Start transfer */ |
Vipul Kumar | 3b06a0f | 2018-01-23 14:52:35 +0530 | [diff] [blame] | 704 | axienet_dma_write(&tx_bd, &priv->dmatx->tail); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 705 | |
| 706 | /* Wait for transmission to complete */ |
| 707 | debug("axiemac: Waiting for tx to be done\n"); |
| 708 | timeout = 200; |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 709 | while (timeout && (!(readl(&priv->dmatx->status) & |
Michal Simek | 5aa4539 | 2015-10-28 11:00:47 +0100 | [diff] [blame] | 710 | (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) { |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 711 | timeout--; |
| 712 | udelay(1); |
| 713 | } |
| 714 | if (!timeout) { |
| 715 | printf("%s: Timeout\n", __func__); |
| 716 | return 1; |
| 717 | } |
| 718 | |
| 719 | debug("axiemac: Sending complete\n"); |
| 720 | return 0; |
| 721 | } |
| 722 | |
Michal Simek | 638c0ef | 2015-12-09 14:53:51 +0100 | [diff] [blame] | 723 | static int isrxready(struct axidma_priv *priv) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 724 | { |
| 725 | u32 status; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 726 | |
| 727 | /* Read pending interrupts */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 728 | status = readl(&priv->dmarx->status); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 729 | |
| 730 | /* Acknowledge pending interrupts */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 731 | writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 732 | |
| 733 | /* |
| 734 | * If Reception done interrupt is asserted, call RX call back function |
| 735 | * to handle the processed BDs and then raise the according flag. |
| 736 | */ |
| 737 | if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) |
| 738 | return 1; |
| 739 | |
| 740 | return 0; |
| 741 | } |
| 742 | |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 743 | static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 744 | { |
| 745 | u32 length; |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 746 | struct axidma_priv *priv = dev_get_priv(dev); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 747 | u32 temp; |
| 748 | |
| 749 | /* Wait for an incoming packet */ |
Michal Simek | 638c0ef | 2015-12-09 14:53:51 +0100 | [diff] [blame] | 750 | if (!isrxready(priv)) |
Maksim Kiselev | 3789b99 | 2023-07-19 09:53:37 +0300 | [diff] [blame] | 751 | return -EAGAIN; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 752 | |
| 753 | debug("axiemac: RX data ready\n"); |
| 754 | |
| 755 | /* Disable IRQ for a moment till packet is handled */ |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 756 | temp = readl(&priv->dmarx->control); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 757 | temp &= ~XAXIDMA_IRQ_ALL_MASK; |
Siva Durga Prasad Paladugu | d227c9a | 2017-11-23 12:23:12 +0530 | [diff] [blame] | 758 | writel(temp, &priv->dmarx->control); |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 759 | if (!priv->eth_hasnobuf && priv->mactype == EMAC_1G) |
Siva Durga Prasad Paladugu | f802603 | 2017-01-06 16:27:15 +0530 | [diff] [blame] | 760 | length = rx_bd.app4 & 0xFFFF; /* max length mask */ |
| 761 | else |
| 762 | length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 763 | |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 764 | #ifdef DEBUG |
| 765 | print_buffer(&rxframe, &rxframe[0], 1, length, 16); |
| 766 | #endif |
Michal Simek | 0305be8 | 2015-12-09 14:13:23 +0100 | [diff] [blame] | 767 | |
| 768 | *packetp = rxframe; |
| 769 | return length; |
| 770 | } |
| 771 | |
| 772 | static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length) |
| 773 | { |
| 774 | struct axidma_priv *priv = dev_get_priv(dev); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 775 | |
| 776 | #ifdef DEBUG |
| 777 | /* It is useful to clear buffer to be sure that it is consistent */ |
| 778 | memset(rxframe, 0, sizeof(rxframe)); |
| 779 | #endif |
| 780 | /* Setup RxBD */ |
| 781 | /* Clear the whole buffer and setup it again - all flags are cleared */ |
| 782 | memset(&rx_bd, 0, sizeof(rx_bd)); |
Ashok Reddy Soma | 91d455a | 2020-09-03 08:36:43 -0600 | [diff] [blame] | 783 | rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd); |
| 784 | rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe); |
| 785 | #if defined(CONFIG_PHYS_64BIT) |
| 786 | rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd); |
| 787 | rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe); |
| 788 | #endif |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 789 | rx_bd.cntrl = sizeof(rxframe); |
| 790 | |
| 791 | /* Write bd to HW */ |
Ashok Reddy Soma | f29a570 | 2020-09-03 08:36:44 -0600 | [diff] [blame] | 792 | flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd)); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 793 | |
| 794 | /* It is necessary to flush rxframe because if you don't do it |
| 795 | * then cache will contain previous packet */ |
Ashok Reddy Soma | f29a570 | 2020-09-03 08:36:44 -0600 | [diff] [blame] | 796 | flush_cache((phys_addr_t)&rxframe, sizeof(rxframe)); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 797 | |
| 798 | /* Rx BD is ready - start again */ |
Vipul Kumar | 3b06a0f | 2018-01-23 14:52:35 +0530 | [diff] [blame] | 799 | axienet_dma_write(&rx_bd, &priv->dmarx->tail); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 800 | |
| 801 | debug("axiemac: RX completed, framelength = %d\n", length); |
| 802 | |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 803 | return 0; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 804 | } |
| 805 | |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 806 | static int axiemac_miiphy_read(struct mii_dev *bus, int addr, |
| 807 | int devad, int reg) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 808 | { |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 809 | int ret; |
| 810 | u16 value; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 811 | |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 812 | ret = phyread(bus->priv, addr, reg, &value); |
| 813 | debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, |
| 814 | value, ret); |
| 815 | return value; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 816 | } |
| 817 | |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 818 | static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad, |
| 819 | int reg, u16 value) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 820 | { |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 821 | debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); |
| 822 | return phywrite(bus->priv, addr, reg, value); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 823 | } |
| 824 | |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 825 | static int axi_emac_probe(struct udevice *dev) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 826 | { |
Ashok Reddy Soma | 3c4df95 | 2021-06-24 00:34:40 -0600 | [diff] [blame] | 827 | struct axidma_plat *plat = dev_get_plat(dev); |
| 828 | struct eth_pdata *pdata = &plat->eth_pdata; |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 829 | struct axidma_priv *priv = dev_get_priv(dev); |
| 830 | int ret; |
| 831 | |
Ashok Reddy Soma | 3c4df95 | 2021-06-24 00:34:40 -0600 | [diff] [blame] | 832 | priv->iobase = (struct axi_regs *)pdata->iobase; |
| 833 | priv->dmatx = plat->dmatx; |
| 834 | /* RX channel offset is 0x30 */ |
| 835 | priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30); |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 836 | priv->mactype = plat->mactype; |
Ashok Reddy Soma | 3c4df95 | 2021-06-24 00:34:40 -0600 | [diff] [blame] | 837 | |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 838 | if (priv->mactype == EMAC_1G) { |
| 839 | priv->eth_hasnobuf = plat->eth_hasnobuf; |
Andy Chiu | 58af7eb | 2022-11-01 11:57:59 +0800 | [diff] [blame] | 840 | priv->pcsaddr = plat->pcsaddr; |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 841 | priv->phyaddr = plat->phyaddr; |
Maxim Kochetkov | 61cd6fd | 2023-08-11 10:43:51 +0300 | [diff] [blame] | 842 | priv->phynode = plat->phynode; |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 843 | priv->interface = pdata->phy_interface; |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 844 | |
T Karthik Reddy | 4a3f40b | 2022-05-10 13:26:09 +0200 | [diff] [blame] | 845 | if (IS_ENABLED(CONFIG_DM_ETH_PHY)) |
| 846 | priv->bus = eth_phy_get_mdio_bus(dev); |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 847 | |
T Karthik Reddy | 4a3f40b | 2022-05-10 13:26:09 +0200 | [diff] [blame] | 848 | if (!priv->bus) { |
| 849 | priv->bus = mdio_alloc(); |
| 850 | priv->bus->read = axiemac_miiphy_read; |
| 851 | priv->bus->write = axiemac_miiphy_write; |
| 852 | priv->bus->priv = priv; |
| 853 | |
| 854 | ret = mdio_register_seq(priv->bus, dev_seq(dev)); |
| 855 | if (ret) |
| 856 | return ret; |
| 857 | } |
| 858 | |
| 859 | if (IS_ENABLED(CONFIG_DM_ETH_PHY)) |
| 860 | eth_phy_set_mdio_bus(dev, priv->bus); |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 861 | |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 862 | axiemac_phy_init(dev); |
| 863 | } |
Michal Simek | 0b13ee2 | 2015-12-08 16:10:05 +0100 | [diff] [blame] | 864 | |
T Karthik Reddy | 4a3f40b | 2022-05-10 13:26:09 +0200 | [diff] [blame] | 865 | printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase, |
| 866 | priv->phyaddr, phy_string_for_interface(pdata->phy_interface)); |
| 867 | |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 868 | return 0; |
| 869 | } |
| 870 | |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 871 | static int axi_emac_remove(struct udevice *dev) |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 872 | { |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 873 | struct axidma_priv *priv = dev_get_priv(dev); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 874 | |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 875 | if (priv->mactype == EMAC_1G) { |
| 876 | free(priv->phydev); |
| 877 | mdio_unregister(priv->bus); |
| 878 | mdio_free(priv->bus); |
| 879 | } |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 880 | |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 881 | return 0; |
| 882 | } |
| 883 | |
| 884 | static const struct eth_ops axi_emac_ops = { |
Michal Simek | 8fbf79f | 2015-12-16 09:18:12 +0100 | [diff] [blame] | 885 | .start = axiemac_start, |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 886 | .send = axiemac_send, |
| 887 | .recv = axiemac_recv, |
Michal Simek | 0305be8 | 2015-12-09 14:13:23 +0100 | [diff] [blame] | 888 | .free_pkt = axiemac_free_pkt, |
Michal Simek | 8fbf79f | 2015-12-16 09:18:12 +0100 | [diff] [blame] | 889 | .stop = axiemac_stop, |
| 890 | .write_hwaddr = axiemac_write_hwaddr, |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 891 | }; |
| 892 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 893 | static int axi_emac_of_to_plat(struct udevice *dev) |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 894 | { |
Ashok Reddy Soma | 3c4df95 | 2021-06-24 00:34:40 -0600 | [diff] [blame] | 895 | struct axidma_plat *plat = dev_get_plat(dev); |
| 896 | struct eth_pdata *pdata = &plat->eth_pdata; |
Maxim Kochetkov | 61cd6fd | 2023-08-11 10:43:51 +0300 | [diff] [blame] | 897 | struct ofnode_phandle_args pcs_node, axistream_node; |
| 898 | ofnode phynode; |
| 899 | int ret; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 900 | |
Masahiro Yamada | a89b4de | 2020-07-17 14:36:48 +0900 | [diff] [blame] | 901 | pdata->iobase = dev_read_addr(dev); |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 902 | plat->mactype = dev_get_driver_data(dev); |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 903 | |
Maxim Kochetkov | 61cd6fd | 2023-08-11 10:43:51 +0300 | [diff] [blame] | 904 | ret = dev_read_phandle_with_args(dev, "axistream-connected", NULL, 0, 0, |
| 905 | &axistream_node); |
| 906 | if (ret) { |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 907 | printf("%s: axistream is not found\n", __func__); |
| 908 | return -EINVAL; |
| 909 | } |
Maxim Kochetkov | 61cd6fd | 2023-08-11 10:43:51 +0300 | [diff] [blame] | 910 | |
| 911 | plat->dmatx = (struct axidma_reg *)ofnode_get_addr(axistream_node.node); |
Ashok Reddy Soma | 3c4df95 | 2021-06-24 00:34:40 -0600 | [diff] [blame] | 912 | if (!plat->dmatx) { |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 913 | printf("%s: axi_dma register space not found\n", __func__); |
| 914 | return -EINVAL; |
| 915 | } |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 916 | |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 917 | if (plat->mactype == EMAC_1G) { |
| 918 | plat->phyaddr = -1; |
Andy Chiu | 58af7eb | 2022-11-01 11:57:59 +0800 | [diff] [blame] | 919 | /* PHYAD 0 always redirects to the PCS/PMA PHY */ |
| 920 | plat->pcsaddr = 0; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 921 | |
Maxim Kochetkov | 61cd6fd | 2023-08-11 10:43:51 +0300 | [diff] [blame] | 922 | phynode = dev_get_phy_node(dev); |
| 923 | if (ofnode_valid(phynode)) { |
T Karthik Reddy | 4a3f40b | 2022-05-10 13:26:09 +0200 | [diff] [blame] | 924 | if (!(IS_ENABLED(CONFIG_DM_ETH_PHY))) |
Maxim Kochetkov | 61cd6fd | 2023-08-11 10:43:51 +0300 | [diff] [blame] | 925 | plat->phyaddr = ofnode_read_u32_default(phynode, |
| 926 | "reg", -1); |
| 927 | plat->phynode = phynode; |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 928 | } |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 929 | |
Marek BehĂșn | bc19477 | 2022-04-07 00:33:01 +0200 | [diff] [blame] | 930 | pdata->phy_interface = dev_read_phy_mode(dev); |
Marek BehĂșn | 48631e4 | 2022-04-07 00:33:03 +0200 | [diff] [blame] | 931 | if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 932 | return -EINVAL; |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 933 | |
Maxim Kochetkov | 61cd6fd | 2023-08-11 10:43:51 +0300 | [diff] [blame] | 934 | plat->eth_hasnobuf = dev_read_bool(dev, "xlnx,eth-hasnobuf"); |
Andy Chiu | 58af7eb | 2022-11-01 11:57:59 +0800 | [diff] [blame] | 935 | |
| 936 | if (pdata->phy_interface == PHY_INTERFACE_MODE_SGMII || |
| 937 | pdata->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { |
Maxim Kochetkov | 61cd6fd | 2023-08-11 10:43:51 +0300 | [diff] [blame] | 938 | ret = dev_read_phandle_with_args(dev, "pcs-handle", NULL, 0, 0, |
| 939 | &pcs_node); |
| 940 | if (!ret) { |
| 941 | plat->pcsaddr = ofnode_read_u32_default(pcs_node.node, |
| 942 | "reg", -1); |
Andy Chiu | 58af7eb | 2022-11-01 11:57:59 +0800 | [diff] [blame] | 943 | } |
| 944 | } |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 945 | } |
Siva Durga Prasad Paladugu | f802603 | 2017-01-06 16:27:15 +0530 | [diff] [blame] | 946 | |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 947 | return 0; |
Michal Simek | 6fc7c45 | 2011-10-06 20:35:35 +0000 | [diff] [blame] | 948 | } |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 949 | |
| 950 | static const struct udevice_id axi_emac_ids[] = { |
Ashok Reddy Soma | 645aa76 | 2021-06-24 00:34:41 -0600 | [diff] [blame] | 951 | { .compatible = "xlnx,axi-ethernet-1.00.a", .data = (uintptr_t)EMAC_1G }, |
| 952 | { .compatible = "xlnx,xxv-ethernet-1.0", .data = (uintptr_t)EMAC_10G_25G }, |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 953 | { } |
| 954 | }; |
| 955 | |
| 956 | U_BOOT_DRIVER(axi_emac) = { |
| 957 | .name = "axi_emac", |
| 958 | .id = UCLASS_ETH, |
| 959 | .of_match = axi_emac_ids, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 960 | .of_to_plat = axi_emac_of_to_plat, |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 961 | .probe = axi_emac_probe, |
| 962 | .remove = axi_emac_remove, |
| 963 | .ops = &axi_emac_ops, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 964 | .priv_auto = sizeof(struct axidma_priv), |
Ashok Reddy Soma | 3c4df95 | 2021-06-24 00:34:40 -0600 | [diff] [blame] | 965 | .plat_auto = sizeof(struct axidma_plat), |
Michal Simek | 682baac | 2015-12-08 15:44:41 +0100 | [diff] [blame] | 966 | }; |