Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Copyright Altera Corporation (C) 2014-2015 |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 4 | */ |
| 5 | #include <common.h> |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 6 | #include <dm.h> |
Marek Vasut | 1b1cc10 | 2015-08-01 22:25:29 +0200 | [diff] [blame] | 7 | #include <errno.h> |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 8 | #include <div64.h> |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 9 | #include <ram.h> |
| 10 | #include <reset.h> |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 11 | #include <watchdog.h> |
| 12 | #include <asm/arch/fpga_manager.h> |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 13 | #include <asm/arch/reset_manager.h> |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 14 | #include <asm/arch/sdram.h> |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 15 | #include <asm/arch/system_manager.h> |
| 16 | #include <asm/io.h> |
| 17 | |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 18 | #include "sequencer.h" |
| 19 | |
| 20 | #ifdef CONFIG_SPL_BUILD |
| 21 | |
| 22 | struct altera_gen5_sdram_priv { |
| 23 | struct ram_info info; |
| 24 | }; |
| 25 | |
| 26 | struct altera_gen5_sdram_platdata { |
| 27 | struct socfpga_sdr *sdr; |
| 28 | }; |
| 29 | |
Marek Vasut | e08c559 | 2015-07-26 10:37:54 +0200 | [diff] [blame] | 30 | struct sdram_prot_rule { |
Marek Vasut | 6772cd9 | 2015-08-01 23:12:11 +0200 | [diff] [blame] | 31 | u32 sdram_start; /* SDRAM start address */ |
| 32 | u32 sdram_end; /* SDRAM end address */ |
Marek Vasut | e08c559 | 2015-07-26 10:37:54 +0200 | [diff] [blame] | 33 | u32 rule; /* SDRAM protection rule number: 0-19 */ |
| 34 | int valid; /* Rule valid or not? 1 - valid, 0 not*/ |
| 35 | |
| 36 | u32 security; |
| 37 | u32 portmask; |
| 38 | u32 result; |
| 39 | u32 lo_prot_id; |
| 40 | u32 hi_prot_id; |
| 41 | }; |
| 42 | |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 43 | static struct socfpga_system_manager *sysmgr_regs = |
| 44 | (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 45 | |
| 46 | static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 47 | |
Marek Vasut | 724c50f | 2015-08-01 19:20:19 +0200 | [diff] [blame] | 48 | /** |
| 49 | * get_errata_rows() - Up the number of DRAM rows to cover entire address space |
Marek Vasut | 3a07911 | 2015-08-01 21:16:20 +0200 | [diff] [blame] | 50 | * @cfg: SDRAM controller configuration data |
Marek Vasut | 724c50f | 2015-08-01 19:20:19 +0200 | [diff] [blame] | 51 | * |
| 52 | * SDRAM Failure happens when accessing non-existent memory. Artificially |
| 53 | * increase the number of rows so that the memory controller thinks it has |
| 54 | * 4GB of RAM. This function returns such amount of rows. |
| 55 | */ |
Marek Vasut | 32ada57 | 2015-08-01 21:35:18 +0200 | [diff] [blame] | 56 | static int get_errata_rows(const struct socfpga_sdram_config *cfg) |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 57 | { |
Marek Vasut | 724c50f | 2015-08-01 19:20:19 +0200 | [diff] [blame] | 58 | /* Define constant for 4G memory - used for SDRAM errata workaround */ |
| 59 | #define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL) |
| 60 | const unsigned long long memsize = MEMSIZE_4G; |
Marek Vasut | 3a07911 | 2015-08-01 21:16:20 +0200 | [diff] [blame] | 61 | const unsigned int cs = |
| 62 | ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> |
| 63 | SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; |
| 64 | const unsigned int rows = |
| 65 | (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> |
| 66 | SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; |
| 67 | const unsigned int banks = |
| 68 | (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> |
| 69 | SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; |
| 70 | const unsigned int cols = |
| 71 | (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> |
| 72 | SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB; |
Marek Vasut | 724c50f | 2015-08-01 19:20:19 +0200 | [diff] [blame] | 73 | const unsigned int width = 8; |
| 74 | |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 75 | unsigned long long newrows; |
Marek Vasut | 724c50f | 2015-08-01 19:20:19 +0200 | [diff] [blame] | 76 | int bits, inewrowslog2; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 77 | |
| 78 | debug("workaround rows - memsize %lld\n", memsize); |
| 79 | debug("workaround rows - cs %d\n", cs); |
| 80 | debug("workaround rows - width %d\n", width); |
| 81 | debug("workaround rows - rows %d\n", rows); |
| 82 | debug("workaround rows - banks %d\n", banks); |
| 83 | debug("workaround rows - cols %d\n", cols); |
| 84 | |
Marek Vasut | 186880e | 2015-08-01 18:54:34 +0200 | [diff] [blame] | 85 | newrows = lldiv(memsize, cs * (width / 8)); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 86 | debug("rows workaround - term1 %lld\n", newrows); |
| 87 | |
Marek Vasut | 186880e | 2015-08-01 18:54:34 +0200 | [diff] [blame] | 88 | newrows = lldiv(newrows, (1 << banks) * (1 << cols)); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 89 | debug("rows workaround - term2 %lld\n", newrows); |
| 90 | |
Marek Vasut | 186880e | 2015-08-01 18:54:34 +0200 | [diff] [blame] | 91 | /* |
| 92 | * Compute the hamming weight - same as number of bits set. |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 93 | * Need to see if result is ordinal power of 2 before |
| 94 | * attempting log2 of result. |
| 95 | */ |
Marek Vasut | 2fda506 | 2015-08-01 18:46:55 +0200 | [diff] [blame] | 96 | bits = generic_hweight32(newrows); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 97 | |
| 98 | debug("rows workaround - bits %d\n", bits); |
| 99 | |
| 100 | if (bits != 1) { |
| 101 | printf("SDRAM workaround failed, bits set %d\n", bits); |
| 102 | return rows; |
| 103 | } |
| 104 | |
| 105 | if (newrows > UINT_MAX) { |
| 106 | printf("SDRAM workaround rangecheck failed, %lld\n", newrows); |
| 107 | return rows; |
| 108 | } |
| 109 | |
Marek Vasut | 186880e | 2015-08-01 18:54:34 +0200 | [diff] [blame] | 110 | inewrowslog2 = __ilog2(newrows); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 111 | |
Marek Vasut | 186880e | 2015-08-01 18:54:34 +0200 | [diff] [blame] | 112 | debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 113 | |
| 114 | if (inewrowslog2 == -1) { |
Marek Vasut | 186880e | 2015-08-01 18:54:34 +0200 | [diff] [blame] | 115 | printf("SDRAM workaround failed, newrows %lld\n", newrows); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 116 | return rows; |
| 117 | } |
| 118 | |
| 119 | return inewrowslog2; |
| 120 | } |
| 121 | |
| 122 | /* SDRAM protection rules vary from 0-19, a total of 20 rules. */ |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 123 | static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl, |
| 124 | struct sdram_prot_rule *prule) |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 125 | { |
Marek Vasut | 6772cd9 | 2015-08-01 23:12:11 +0200 | [diff] [blame] | 126 | u32 lo_addr_bits; |
| 127 | u32 hi_addr_bits; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 128 | int ruleno = prule->rule; |
| 129 | |
| 130 | /* Select the rule */ |
| 131 | writel(ruleno, &sdr_ctrl->prot_rule_rdwr); |
| 132 | |
| 133 | /* Obtain the address bits */ |
Marek Vasut | 7fce5bc | 2015-08-01 22:40:48 +0200 | [diff] [blame] | 134 | lo_addr_bits = prule->sdram_start >> 20ULL; |
Marek Vasut | 12361a2 | 2016-04-04 17:52:21 +0200 | [diff] [blame] | 135 | hi_addr_bits = (prule->sdram_end - 1) >> 20ULL; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 136 | |
Marek Vasut | 6772cd9 | 2015-08-01 23:12:11 +0200 | [diff] [blame] | 137 | debug("sdram set rule start %x, %d\n", lo_addr_bits, |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 138 | prule->sdram_start); |
Marek Vasut | 6772cd9 | 2015-08-01 23:12:11 +0200 | [diff] [blame] | 139 | debug("sdram set rule end %x, %d\n", hi_addr_bits, |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 140 | prule->sdram_end); |
| 141 | |
| 142 | /* Set rule addresses */ |
| 143 | writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr); |
| 144 | |
| 145 | /* Set rule protection ids */ |
| 146 | writel(prule->lo_prot_id | (prule->hi_prot_id << 12), |
| 147 | &sdr_ctrl->prot_rule_id); |
| 148 | |
| 149 | /* Set the rule data */ |
| 150 | writel(prule->security | (prule->valid << 2) | |
| 151 | (prule->portmask << 3) | (prule->result << 13), |
| 152 | &sdr_ctrl->prot_rule_data); |
| 153 | |
| 154 | /* write the rule */ |
Marek Vasut | 7fce5bc | 2015-08-01 22:40:48 +0200 | [diff] [blame] | 155 | writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 156 | |
| 157 | /* Set rule number to 0 by default */ |
| 158 | writel(0, &sdr_ctrl->prot_rule_rdwr); |
| 159 | } |
| 160 | |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 161 | static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl, |
| 162 | struct sdram_prot_rule *prule) |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 163 | { |
Marek Vasut | 9114407 | 2015-08-01 23:21:23 +0200 | [diff] [blame] | 164 | u32 addr; |
| 165 | u32 id; |
| 166 | u32 data; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 167 | int ruleno = prule->rule; |
| 168 | |
| 169 | /* Read the rule */ |
| 170 | writel(ruleno, &sdr_ctrl->prot_rule_rdwr); |
Marek Vasut | 9114407 | 2015-08-01 23:21:23 +0200 | [diff] [blame] | 171 | writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 172 | |
| 173 | /* Get the addresses */ |
| 174 | addr = readl(&sdr_ctrl->prot_rule_addr); |
| 175 | prule->sdram_start = (addr & 0xFFF) << 20; |
| 176 | prule->sdram_end = ((addr >> 12) & 0xFFF) << 20; |
| 177 | |
| 178 | /* Get the configured protection IDs */ |
| 179 | id = readl(&sdr_ctrl->prot_rule_id); |
| 180 | prule->lo_prot_id = id & 0xFFF; |
| 181 | prule->hi_prot_id = (id >> 12) & 0xFFF; |
| 182 | |
| 183 | /* Get protection data */ |
| 184 | data = readl(&sdr_ctrl->prot_rule_data); |
| 185 | |
| 186 | prule->security = data & 0x3; |
| 187 | prule->valid = (data >> 2) & 0x1; |
| 188 | prule->portmask = (data >> 3) & 0x3FF; |
| 189 | prule->result = (data >> 13) & 0x1; |
| 190 | } |
| 191 | |
Marek Vasut | 6772cd9 | 2015-08-01 23:12:11 +0200 | [diff] [blame] | 192 | static void |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 193 | sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl, |
| 194 | const u32 sdram_start, const u32 sdram_end) |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 195 | { |
| 196 | struct sdram_prot_rule rule; |
| 197 | int rules; |
| 198 | |
| 199 | /* Start with accepting all SDRAM transaction */ |
| 200 | writel(0x0, &sdr_ctrl->protport_default); |
| 201 | |
| 202 | /* Clear all protection rules for warm boot case */ |
Marek Vasut | 7fce5bc | 2015-08-01 22:40:48 +0200 | [diff] [blame] | 203 | memset(&rule, 0, sizeof(rule)); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 204 | |
| 205 | for (rules = 0; rules < 20; rules++) { |
| 206 | rule.rule = rules; |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 207 | sdram_set_rule(sdr_ctrl, &rule); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | /* new rule: accept SDRAM */ |
| 211 | rule.sdram_start = sdram_start; |
| 212 | rule.sdram_end = sdram_end; |
| 213 | rule.lo_prot_id = 0x0; |
| 214 | rule.hi_prot_id = 0xFFF; |
| 215 | rule.portmask = 0x3FF; |
| 216 | rule.security = 0x3; |
| 217 | rule.result = 0; |
| 218 | rule.valid = 1; |
| 219 | rule.rule = 0; |
| 220 | |
| 221 | /* set new rule */ |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 222 | sdram_set_rule(sdr_ctrl, &rule); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 223 | |
| 224 | /* default rule: reject everything */ |
| 225 | writel(0x3ff, &sdr_ctrl->protport_default); |
| 226 | } |
| 227 | |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 228 | static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl) |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 229 | { |
| 230 | struct sdram_prot_rule rule; |
| 231 | int rules; |
| 232 | |
| 233 | debug("SDRAM Prot rule, default %x\n", |
| 234 | readl(&sdr_ctrl->protport_default)); |
| 235 | |
| 236 | for (rules = 0; rules < 20; rules++) { |
Marek Vasut | 42aa46d | 2015-12-29 09:38:52 +0100 | [diff] [blame] | 237 | rule.rule = rules; |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 238 | sdram_get_rule(sdr_ctrl, &rule); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 239 | debug("Rule %d, rules ...\n", rules); |
Marek Vasut | 6772cd9 | 2015-08-01 23:12:11 +0200 | [diff] [blame] | 240 | debug(" sdram start %x\n", rule.sdram_start); |
| 241 | debug(" sdram end %x\n", rule.sdram_end); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 242 | debug(" low prot id %d, hi prot id %d\n", |
| 243 | rule.lo_prot_id, |
| 244 | rule.hi_prot_id); |
| 245 | debug(" portmask %x\n", rule.portmask); |
| 246 | debug(" security %d\n", rule.security); |
| 247 | debug(" result %d\n", rule.result); |
| 248 | debug(" valid %d\n", rule.valid); |
| 249 | } |
| 250 | } |
| 251 | |
Marek Vasut | 116d88f | 2015-08-01 22:26:11 +0200 | [diff] [blame] | 252 | /** |
| 253 | * sdram_write_verify() - write to register and verify the write. |
| 254 | * @addr: Register address |
| 255 | * @val: Value to be written and verified |
| 256 | * |
| 257 | * This function writes to a register, reads back the value and compares |
| 258 | * the result with the written value to check if the data match. |
| 259 | */ |
| 260 | static unsigned sdram_write_verify(const u32 *addr, const u32 val) |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 261 | { |
Marek Vasut | 116d88f | 2015-08-01 22:26:11 +0200 | [diff] [blame] | 262 | u32 rval; |
| 263 | |
| 264 | debug(" Write - Address 0x%p Data 0x%08x\n", addr, val); |
| 265 | writel(val, addr); |
| 266 | |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 267 | debug(" Read and verify..."); |
Marek Vasut | 116d88f | 2015-08-01 22:26:11 +0200 | [diff] [blame] | 268 | rval = readl(addr); |
| 269 | if (rval != val) { |
| 270 | debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n", |
| 271 | addr, val, rval); |
| 272 | return -EINVAL; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 273 | } |
Marek Vasut | 116d88f | 2015-08-01 22:26:11 +0200 | [diff] [blame] | 274 | |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 275 | debug("correct!\n"); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 276 | return 0; |
| 277 | } |
| 278 | |
Marek Vasut | b0d848c | 2015-08-01 22:28:30 +0200 | [diff] [blame] | 279 | /** |
| 280 | * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register |
| 281 | * @cfg: SDRAM controller configuration data |
| 282 | * |
| 283 | * Return the value of DRAM CTRLCFG register. |
| 284 | */ |
Marek Vasut | 32ada57 | 2015-08-01 21:35:18 +0200 | [diff] [blame] | 285 | static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg) |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 286 | { |
Marek Vasut | 3a07911 | 2015-08-01 21:16:20 +0200 | [diff] [blame] | 287 | const u32 csbits = |
| 288 | ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> |
| 289 | SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; |
| 290 | u32 addrorder = |
| 291 | (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >> |
| 292 | SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB; |
| 293 | |
Marek Vasut | 4f3adbf | 2015-08-01 20:30:10 +0200 | [diff] [blame] | 294 | u32 ctrl_cfg = cfg->ctrl_cfg; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 295 | |
Marek Vasut | 82a2764 | 2015-08-01 19:33:40 +0200 | [diff] [blame] | 296 | /* |
| 297 | * SDRAM Failure When Accessing Non-Existent Memory |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 298 | * Set the addrorder field of the SDRAM control register |
| 299 | * based on the CSBITs setting. |
| 300 | */ |
Marek Vasut | 3a07911 | 2015-08-01 21:16:20 +0200 | [diff] [blame] | 301 | if (csbits == 1) { |
| 302 | if (addrorder != 0) |
Marek Vasut | 82a2764 | 2015-08-01 19:33:40 +0200 | [diff] [blame] | 303 | debug("INFO: Changing address order to 0 (chip, row, bank, column)\n"); |
Marek Vasut | 3a07911 | 2015-08-01 21:16:20 +0200 | [diff] [blame] | 304 | addrorder = 0; |
| 305 | } else if (csbits == 2) { |
| 306 | if (addrorder != 2) |
Marek Vasut | 82a2764 | 2015-08-01 19:33:40 +0200 | [diff] [blame] | 307 | debug("INFO: Changing address order to 2 (row, chip, bank, column)\n"); |
Marek Vasut | 3a07911 | 2015-08-01 21:16:20 +0200 | [diff] [blame] | 308 | addrorder = 2; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 309 | } |
| 310 | |
Marek Vasut | 3a07911 | 2015-08-01 21:16:20 +0200 | [diff] [blame] | 311 | ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK; |
Marek Vasut | 82a2764 | 2015-08-01 19:33:40 +0200 | [diff] [blame] | 312 | ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 313 | |
Marek Vasut | 1e271e4 | 2015-08-01 21:24:31 +0200 | [diff] [blame] | 314 | return ctrl_cfg; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 315 | } |
| 316 | |
Marek Vasut | b0d848c | 2015-08-01 22:28:30 +0200 | [diff] [blame] | 317 | /** |
| 318 | * sdr_get_addr_rw() - Get the value of DRAM ADDRW register |
| 319 | * @cfg: SDRAM controller configuration data |
| 320 | * |
| 321 | * Return the value of DRAM ADDRW register. |
| 322 | */ |
Marek Vasut | 32ada57 | 2015-08-01 21:35:18 +0200 | [diff] [blame] | 323 | static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 324 | { |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 325 | /* |
| 326 | * SDRAM Failure When Accessing Non-Existent Memory |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 327 | * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to |
| 328 | * log2(number of chip select bits). Since there's only |
| 329 | * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1, |
| 330 | * which is the same as "chip selects" - 1. |
| 331 | */ |
Marek Vasut | 3a07911 | 2015-08-01 21:16:20 +0200 | [diff] [blame] | 332 | const int rows = get_errata_rows(cfg); |
| 333 | u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK; |
Marek Vasut | 4f3adbf | 2015-08-01 20:30:10 +0200 | [diff] [blame] | 334 | |
Marek Vasut | 1e271e4 | 2015-08-01 21:24:31 +0200 | [diff] [blame] | 335 | return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 336 | } |
| 337 | |
Marek Vasut | b81f11c | 2015-08-01 21:26:55 +0200 | [diff] [blame] | 338 | /** |
| 339 | * sdr_load_regs() - Load SDRAM controller registers |
| 340 | * @cfg: SDRAM controller configuration data |
| 341 | * |
| 342 | * This function loads the register values into the SDRAM controller block. |
| 343 | */ |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 344 | static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl, |
| 345 | const struct socfpga_sdram_config *cfg) |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 346 | { |
Marek Vasut | 1e271e4 | 2015-08-01 21:24:31 +0200 | [diff] [blame] | 347 | const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); |
| 348 | const u32 dram_addrw = sdr_get_addr_rw(cfg); |
| 349 | |
Marek Vasut | 1e271e4 | 2015-08-01 21:24:31 +0200 | [diff] [blame] | 350 | debug("\nConfiguring CTRLCFG\n"); |
| 351 | writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); |
Marek Vasut | 71c1a00 | 2015-08-01 21:21:21 +0200 | [diff] [blame] | 352 | |
| 353 | debug("Configuring DRAMTIMING1\n"); |
| 354 | writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1); |
| 355 | |
| 356 | debug("Configuring DRAMTIMING2\n"); |
| 357 | writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2); |
| 358 | |
| 359 | debug("Configuring DRAMTIMING3\n"); |
| 360 | writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3); |
| 361 | |
| 362 | debug("Configuring DRAMTIMING4\n"); |
| 363 | writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4); |
| 364 | |
| 365 | debug("Configuring LOWPWRTIMING\n"); |
| 366 | writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing); |
| 367 | |
Marek Vasut | 1e271e4 | 2015-08-01 21:24:31 +0200 | [diff] [blame] | 368 | debug("Configuring DRAMADDRW\n"); |
| 369 | writel(dram_addrw, &sdr_ctrl->dram_addrw); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 370 | |
| 371 | debug("Configuring DRAMIFWIDTH\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 372 | writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 373 | |
| 374 | debug("Configuring DRAMDEVWIDTH\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 375 | writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 376 | |
| 377 | debug("Configuring LOWPWREQ\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 378 | writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 379 | |
| 380 | debug("Configuring DRAMINTR\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 381 | writel(cfg->dram_intr, &sdr_ctrl->dram_intr); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 382 | |
Marek Vasut | 71c1a00 | 2015-08-01 21:21:21 +0200 | [diff] [blame] | 383 | debug("Configuring STATICCFG\n"); |
| 384 | writel(cfg->static_cfg, &sdr_ctrl->static_cfg); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 385 | |
| 386 | debug("Configuring CTRLWIDTH\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 387 | writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 388 | |
| 389 | debug("Configuring PORTCFG\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 390 | writel(cfg->port_cfg, &sdr_ctrl->port_cfg); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 391 | |
Marek Vasut | 71c1a00 | 2015-08-01 21:21:21 +0200 | [diff] [blame] | 392 | debug("Configuring FIFOCFG\n"); |
| 393 | writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 394 | |
| 395 | debug("Configuring MPPRIORITY\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 396 | writel(cfg->mp_priority, &sdr_ctrl->mp_priority); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 397 | |
Marek Vasut | 71c1a00 | 2015-08-01 21:21:21 +0200 | [diff] [blame] | 398 | debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); |
| 399 | writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0); |
| 400 | writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1); |
| 401 | writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2); |
| 402 | writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3); |
| 403 | |
| 404 | debug("Configuring MPPACING_MPPACING_0\n"); |
| 405 | writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0); |
| 406 | writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1); |
| 407 | writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2); |
| 408 | writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3); |
| 409 | |
| 410 | debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); |
| 411 | writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0); |
| 412 | writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1); |
| 413 | writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 414 | |
| 415 | debug("Configuring PHYCTRL_PHYCTRL_0\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 416 | writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 417 | |
| 418 | debug("Configuring CPORTWIDTH\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 419 | writel(cfg->cport_width, &sdr_ctrl->cport_width); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 420 | |
| 421 | debug("Configuring CPORTWMAP\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 422 | writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 423 | |
| 424 | debug("Configuring CPORTRMAP\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 425 | writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 426 | |
| 427 | debug("Configuring RFIFOCMAP\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 428 | writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 429 | |
| 430 | debug("Configuring WFIFOCMAP\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 431 | writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 432 | |
| 433 | debug("Configuring CPORTRDWR\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 434 | writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 435 | |
| 436 | debug("Configuring DRAMODT\n"); |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 437 | writel(cfg->dram_odt, &sdr_ctrl->dram_odt); |
Chin Liang See | 3ea5951 | 2016-09-21 10:25:56 +0800 | [diff] [blame] | 438 | |
| 439 | debug("Configuring EXTRATIME1\n"); |
| 440 | writel(cfg->extratime1, &sdr_ctrl->extratime1); |
Marek Vasut | b81f11c | 2015-08-01 21:26:55 +0200 | [diff] [blame] | 441 | } |
| 442 | |
Marek Vasut | 5a4e8ed | 2015-08-01 22:03:48 +0200 | [diff] [blame] | 443 | /** |
| 444 | * sdram_mmr_init_full() - Function to initialize SDRAM MMR |
| 445 | * @sdr_phy_reg: Value of the PHY control register 0 |
| 446 | * |
| 447 | * Initialize the SDRAM MMR. |
| 448 | */ |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 449 | int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl, |
| 450 | unsigned int sdr_phy_reg) |
Marek Vasut | b81f11c | 2015-08-01 21:26:55 +0200 | [diff] [blame] | 451 | { |
Marek Vasut | 32ada57 | 2015-08-01 21:35:18 +0200 | [diff] [blame] | 452 | const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); |
Marek Vasut | b81f11c | 2015-08-01 21:26:55 +0200 | [diff] [blame] | 453 | const unsigned int rows = |
| 454 | (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> |
| 455 | SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; |
Marek Vasut | 116d88f | 2015-08-01 22:26:11 +0200 | [diff] [blame] | 456 | int ret; |
Marek Vasut | b81f11c | 2015-08-01 21:26:55 +0200 | [diff] [blame] | 457 | |
| 458 | writel(rows, &sysmgr_regs->iswgrp_handoff[4]); |
| 459 | |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 460 | sdr_load_regs(sdr_ctrl, cfg); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 461 | |
| 462 | /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 463 | writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 464 | |
| 465 | /* only enable if the FPGA is programmed */ |
| 466 | if (fpgamgr_test_fpga_ready()) { |
Marek Vasut | 116d88f | 2015-08-01 22:26:11 +0200 | [diff] [blame] | 467 | ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst, |
| 468 | cfg->fpgaport_rst); |
| 469 | if (ret) |
| 470 | return ret; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 471 | } |
| 472 | |
| 473 | /* Restore the SDR PHY Register if valid */ |
| 474 | if (sdr_phy_reg != 0xffffffff) |
| 475 | writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0); |
| 476 | |
Marek Vasut | 7697ff7 | 2015-08-01 20:58:44 +0200 | [diff] [blame] | 477 | /* Final step - apply configuration changes */ |
| 478 | debug("Configuring STATICCFG\n"); |
| 479 | clrsetbits_le32(&sdr_ctrl->static_cfg, |
| 480 | SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 481 | 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 482 | |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 483 | sdram_set_protection_config(sdr_ctrl, 0, |
| 484 | sdram_calculate_size(sdr_ctrl) - 1); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 485 | |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 486 | sdram_dump_protection_config(sdr_ctrl); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 487 | |
Marek Vasut | 116d88f | 2015-08-01 22:26:11 +0200 | [diff] [blame] | 488 | return 0; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 489 | } |
| 490 | |
Marek Vasut | 1796a09 | 2015-08-01 21:47:16 +0200 | [diff] [blame] | 491 | /** |
| 492 | * sdram_calculate_size() - Calculate SDRAM size |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 493 | * |
Marek Vasut | 1796a09 | 2015-08-01 21:47:16 +0200 | [diff] [blame] | 494 | * Calculate SDRAM device size based on SDRAM controller parameters. |
| 495 | * Size is specified in bytes. |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 496 | */ |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 497 | static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl) |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 498 | { |
| 499 | unsigned long temp; |
| 500 | unsigned long row, bank, col, cs, width; |
Marek Vasut | 6d6fbba | 2015-08-01 21:44:00 +0200 | [diff] [blame] | 501 | const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); |
| 502 | const unsigned int csbits = |
| 503 | ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> |
| 504 | SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; |
| 505 | const unsigned int rowbits = |
| 506 | (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> |
| 507 | SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 508 | |
| 509 | temp = readl(&sdr_ctrl->dram_addrw); |
| 510 | col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> |
| 511 | SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB; |
| 512 | |
Marek Vasut | 1796a09 | 2015-08-01 21:47:16 +0200 | [diff] [blame] | 513 | /* |
| 514 | * SDRAM Failure When Accessing Non-Existent Memory |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 515 | * Use ROWBITS from Quartus/QSys to calculate SDRAM size |
| 516 | * since the FB specifies we modify ROWBITs to work around SDRAM |
| 517 | * controller issue. |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 518 | */ |
| 519 | row = readl(&sysmgr_regs->iswgrp_handoff[4]); |
| 520 | if (row == 0) |
Marek Vasut | 6d6fbba | 2015-08-01 21:44:00 +0200 | [diff] [blame] | 521 | row = rowbits; |
Marek Vasut | 1796a09 | 2015-08-01 21:47:16 +0200 | [diff] [blame] | 522 | /* |
| 523 | * If the stored handoff value for rows is greater than |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 524 | * the field width in the sdr.dramaddrw register then |
| 525 | * something is very wrong. Revert to using the the #define |
| 526 | * value handed off by the SOCEDS tool chain instead of |
| 527 | * using a broken value. |
| 528 | */ |
| 529 | if (row > 31) |
Marek Vasut | 6d6fbba | 2015-08-01 21:44:00 +0200 | [diff] [blame] | 530 | row = rowbits; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 531 | |
| 532 | bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> |
| 533 | SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; |
| 534 | |
Marek Vasut | 1796a09 | 2015-08-01 21:47:16 +0200 | [diff] [blame] | 535 | /* |
| 536 | * SDRAM Failure When Accessing Non-Existent Memory |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 537 | * Use CSBITs from Quartus/QSys to calculate SDRAM size |
| 538 | * since the FB specifies we modify CSBITs to work around SDRAM |
| 539 | * controller issue. |
| 540 | */ |
Marek Vasut | 6d6fbba | 2015-08-01 21:44:00 +0200 | [diff] [blame] | 541 | cs = csbits; |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 542 | |
| 543 | width = readl(&sdr_ctrl->dram_if_width); |
Marek Vasut | 1796a09 | 2015-08-01 21:47:16 +0200 | [diff] [blame] | 544 | |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 545 | /* ECC would not be calculated as its not addressible */ |
| 546 | if (width == SDRAM_WIDTH_32BIT_WITH_ECC) |
| 547 | width = 32; |
| 548 | if (width == SDRAM_WIDTH_16BIT_WITH_ECC) |
| 549 | width = 16; |
| 550 | |
| 551 | /* calculate the SDRAM size base on this info */ |
| 552 | temp = 1 << (row + bank + col); |
| 553 | temp = temp * cs * (width / 8); |
| 554 | |
Marek Vasut | 1796a09 | 2015-08-01 21:47:16 +0200 | [diff] [blame] | 555 | debug("%s returns %ld\n", __func__, temp); |
Dinh Nguyen | 429642c | 2015-06-02 22:52:48 -0500 | [diff] [blame] | 556 | |
| 557 | return temp; |
| 558 | } |
Simon Goldschmidt | 24910c3 | 2019-04-16 22:04:39 +0200 | [diff] [blame] | 559 | |
| 560 | static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev) |
| 561 | { |
| 562 | struct altera_gen5_sdram_platdata *plat = dev->platdata; |
| 563 | |
| 564 | plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0); |
| 565 | if (!plat->sdr) |
| 566 | return -ENODEV; |
| 567 | |
| 568 | return 0; |
| 569 | } |
| 570 | |
| 571 | static int altera_gen5_sdram_probe(struct udevice *dev) |
| 572 | { |
| 573 | int ret; |
| 574 | unsigned long sdram_size; |
| 575 | struct altera_gen5_sdram_platdata *plat = dev->platdata; |
| 576 | struct altera_gen5_sdram_priv *priv = dev_get_priv(dev); |
| 577 | struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl; |
| 578 | struct reset_ctl_bulk resets; |
| 579 | |
| 580 | ret = reset_get_bulk(dev, &resets); |
| 581 | if (ret) { |
| 582 | dev_err(dev, "Can't get reset: %d\n", ret); |
| 583 | return -ENODEV; |
| 584 | } |
| 585 | reset_deassert_bulk(&resets); |
| 586 | |
| 587 | if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) { |
| 588 | puts("SDRAM init failed.\n"); |
| 589 | goto failed; |
| 590 | } |
| 591 | |
| 592 | debug("SDRAM: Calibrating PHY\n"); |
| 593 | /* SDRAM calibration */ |
| 594 | if (sdram_calibration_full(plat->sdr) == 0) { |
| 595 | puts("SDRAM calibration failed.\n"); |
| 596 | goto failed; |
| 597 | } |
| 598 | |
| 599 | sdram_size = sdram_calculate_size(sdr_ctrl); |
| 600 | debug("SDRAM: %ld MiB\n", sdram_size >> 20); |
| 601 | |
| 602 | /* Sanity check ensure correct SDRAM size specified */ |
| 603 | if (get_ram_size(0, sdram_size) != sdram_size) { |
| 604 | puts("SDRAM size check failed!\n"); |
| 605 | goto failed; |
| 606 | } |
| 607 | |
| 608 | priv->info.base = 0; |
| 609 | priv->info.size = sdram_size; |
| 610 | |
| 611 | return 0; |
| 612 | |
| 613 | failed: |
| 614 | reset_release_bulk(&resets); |
| 615 | return -ENODEV; |
| 616 | } |
| 617 | |
| 618 | static int altera_gen5_sdram_get_info(struct udevice *dev, |
| 619 | struct ram_info *info) |
| 620 | { |
| 621 | struct altera_gen5_sdram_priv *priv = dev_get_priv(dev); |
| 622 | |
| 623 | info->base = priv->info.base; |
| 624 | info->size = priv->info.size; |
| 625 | |
| 626 | return 0; |
| 627 | } |
| 628 | |
| 629 | static struct ram_ops altera_gen5_sdram_ops = { |
| 630 | .get_info = altera_gen5_sdram_get_info, |
| 631 | }; |
| 632 | |
| 633 | static const struct udevice_id altera_gen5_sdram_ids[] = { |
| 634 | { .compatible = "altr,sdr-ctl" }, |
| 635 | { /* sentinel */ } |
| 636 | }; |
| 637 | |
| 638 | U_BOOT_DRIVER(altera_gen5_sdram) = { |
| 639 | .name = "altr_sdr_ctl", |
| 640 | .id = UCLASS_RAM, |
| 641 | .of_match = altera_gen5_sdram_ids, |
| 642 | .ops = &altera_gen5_sdram_ops, |
| 643 | .ofdata_to_platdata = altera_gen5_sdram_ofdata_to_platdata, |
| 644 | .platdata_auto_alloc_size = sizeof(struct altera_gen5_sdram_platdata), |
| 645 | .probe = altera_gen5_sdram_probe, |
| 646 | .priv_auto_alloc_size = sizeof(struct altera_gen5_sdram_priv), |
| 647 | }; |
| 648 | |
| 649 | #endif /* CONFIG_SPL_BUILD */ |