Yanhong Wang | 5efc934 | 2023-03-29 11:42:23 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 OR MIT |
| 2 | /* |
| 3 | * Copyright (C) 2022 StarFive Technology Co., Ltd. |
| 4 | */ |
| 5 | |
| 6 | /dts-v1/; |
| 7 | |
| 8 | #include "jh7110.dtsi" |
| 9 | #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h> |
Mason Huo | 23dfd81 | 2023-07-25 17:46:50 +0800 | [diff] [blame^] | 10 | #include <dt-bindings/gpio/gpio.h> |
Yanhong Wang | 5efc934 | 2023-03-29 11:42:23 +0800 | [diff] [blame] | 11 | / { |
| 12 | aliases { |
| 13 | serial0 = &uart0; |
| 14 | spi0 = &qspi; |
| 15 | mmc0 = &mmc0; |
| 16 | mmc1 = &mmc1; |
| 17 | i2c0 = &i2c0; |
| 18 | i2c2 = &i2c2; |
| 19 | i2c5 = &i2c5; |
| 20 | i2c6 = &i2c6; |
Yanhong Wang | 7f63bd9 | 2023-06-15 17:36:44 +0800 | [diff] [blame] | 21 | ethernet0 = &gmac0; |
| 22 | ethernet1 = &gmac1; |
Yanhong Wang | 5efc934 | 2023-03-29 11:42:23 +0800 | [diff] [blame] | 23 | }; |
| 24 | |
| 25 | chosen { |
| 26 | stdout-path = "serial0:115200n8"; |
| 27 | }; |
| 28 | |
| 29 | cpus { |
| 30 | timebase-frequency = <4000000>; |
| 31 | }; |
| 32 | |
| 33 | memory@40000000 { |
| 34 | device_type = "memory"; |
| 35 | reg = <0x0 0x40000000 0x2 0x0>; |
| 36 | }; |
| 37 | }; |
| 38 | |
| 39 | &osc { |
| 40 | clock-frequency = <24000000>; |
| 41 | }; |
| 42 | |
| 43 | &rtc_osc { |
| 44 | clock-frequency = <32768>; |
| 45 | }; |
| 46 | |
| 47 | &gmac0_rmii_refin { |
| 48 | clock-frequency = <50000000>; |
| 49 | }; |
| 50 | |
| 51 | &gmac0_rgmii_rxin { |
| 52 | clock-frequency = <125000000>; |
| 53 | }; |
| 54 | |
| 55 | &gmac1_rmii_refin { |
| 56 | clock-frequency = <50000000>; |
| 57 | }; |
| 58 | |
| 59 | &gmac1_rgmii_rxin { |
| 60 | clock-frequency = <125000000>; |
| 61 | }; |
| 62 | |
| 63 | &i2stx_bclk_ext { |
| 64 | clock-frequency = <12288000>; |
| 65 | }; |
| 66 | |
| 67 | &i2stx_lrck_ext { |
| 68 | clock-frequency = <192000>; |
| 69 | }; |
| 70 | |
| 71 | &i2srx_bclk_ext { |
| 72 | clock-frequency = <12288000>; |
| 73 | }; |
| 74 | |
| 75 | &i2srx_lrck_ext { |
| 76 | clock-frequency = <192000>; |
| 77 | }; |
| 78 | |
| 79 | &tdm_ext { |
| 80 | clock-frequency = <49152000>; |
| 81 | }; |
| 82 | |
| 83 | &mclk_ext { |
| 84 | clock-frequency = <12288000>; |
| 85 | }; |
| 86 | |
| 87 | &uart0 { |
| 88 | reg-offset = <0>; |
| 89 | current-speed = <115200>; |
| 90 | clock-frequency = <24000000>; |
| 91 | pinctrl-names = "default"; |
| 92 | pinctrl-0 = <&uart0_pins>; |
| 93 | status = "okay"; |
| 94 | }; |
| 95 | |
| 96 | &i2c0 { |
| 97 | clock-frequency = <100000>; |
| 98 | i2c-sda-hold-time-ns = <300>; |
| 99 | i2c-sda-falling-time-ns = <510>; |
| 100 | i2c-scl-falling-time-ns = <510>; |
| 101 | pinctrl-names = "default"; |
| 102 | pinctrl-0 = <&i2c0_pins>; |
| 103 | status = "okay"; |
| 104 | }; |
| 105 | |
| 106 | &i2c2 { |
| 107 | clock-frequency = <100000>; |
| 108 | i2c-sda-hold-time-ns = <300>; |
| 109 | i2c-sda-falling-time-ns = <510>; |
| 110 | i2c-scl-falling-time-ns = <510>; |
| 111 | pinctrl-names = "default"; |
| 112 | pinctrl-0 = <&i2c2_pins>; |
| 113 | status = "okay"; |
| 114 | }; |
| 115 | |
| 116 | &i2c5 { |
| 117 | clock-frequency = <100000>; |
| 118 | i2c-sda-hold-time-ns = <300>; |
| 119 | i2c-sda-falling-time-ns = <510>; |
| 120 | i2c-scl-falling-time-ns = <510>; |
| 121 | pinctrl-names = "default"; |
| 122 | pinctrl-0 = <&i2c5_pins>; |
| 123 | status = "okay"; |
Yanhong Wang | d426942 | 2023-06-15 17:36:49 +0800 | [diff] [blame] | 124 | |
| 125 | eeprom@50 { |
| 126 | compatible = "atmel,24c04"; |
| 127 | reg = <0x50>; |
| 128 | pagesize = <16>; |
| 129 | }; |
Yanhong Wang | 5efc934 | 2023-03-29 11:42:23 +0800 | [diff] [blame] | 130 | }; |
| 131 | |
| 132 | &i2c6 { |
| 133 | clock-frequency = <100000>; |
| 134 | i2c-sda-hold-time-ns = <300>; |
| 135 | i2c-sda-falling-time-ns = <510>; |
| 136 | i2c-scl-falling-time-ns = <510>; |
| 137 | pinctrl-names = "default"; |
| 138 | pinctrl-0 = <&i2c6_pins>; |
| 139 | status = "okay"; |
| 140 | }; |
| 141 | |
| 142 | &sysgpio { |
| 143 | status = "okay"; |
| 144 | uart0_pins: uart0-0 { |
| 145 | tx-pins { |
| 146 | pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, |
| 147 | GPOEN_ENABLE, |
| 148 | GPI_NONE)>; |
| 149 | bias-disable; |
| 150 | drive-strength = <12>; |
| 151 | input-disable; |
| 152 | input-schmitt-disable; |
| 153 | slew-rate = <0>; |
| 154 | }; |
| 155 | |
| 156 | rx-pins { |
| 157 | pinmux = <GPIOMUX(6, GPOUT_LOW, |
| 158 | GPOEN_DISABLE, |
| 159 | GPI_SYS_UART0_RX)>; |
| 160 | bias-disable; /* external pull-up */ |
| 161 | drive-strength = <2>; |
| 162 | input-enable; |
| 163 | input-schmitt-enable; |
| 164 | slew-rate = <0>; |
| 165 | }; |
| 166 | }; |
| 167 | |
| 168 | i2c0_pins: i2c0-0 { |
| 169 | i2c-pins { |
| 170 | pinmux = <GPIOMUX(57, GPOUT_LOW, |
| 171 | GPOEN_SYS_I2C0_CLK, |
| 172 | GPI_SYS_I2C0_CLK)>, |
| 173 | <GPIOMUX(58, GPOUT_LOW, |
| 174 | GPOEN_SYS_I2C0_DATA, |
| 175 | GPI_SYS_I2C0_DATA)>; |
| 176 | bias-disable; /* external pull-up */ |
| 177 | input-enable; |
| 178 | input-schmitt-enable; |
| 179 | }; |
| 180 | }; |
| 181 | |
| 182 | i2c2_pins: i2c2-0 { |
| 183 | i2c-pins { |
| 184 | pinmux = <GPIOMUX(3, GPOUT_LOW, |
| 185 | GPOEN_SYS_I2C2_CLK, |
| 186 | GPI_SYS_I2C2_CLK)>, |
| 187 | <GPIOMUX(2, GPOUT_LOW, |
| 188 | GPOEN_SYS_I2C2_DATA, |
| 189 | GPI_SYS_I2C2_DATA)>; |
| 190 | bias-disable; /* external pull-up */ |
| 191 | input-enable; |
| 192 | input-schmitt-enable; |
| 193 | }; |
| 194 | }; |
| 195 | |
| 196 | i2c5_pins: i2c5-0 { |
| 197 | i2c-pins { |
| 198 | pinmux = <GPIOMUX(19, GPOUT_LOW, |
| 199 | GPOEN_SYS_I2C5_CLK, |
| 200 | GPI_SYS_I2C5_CLK)>, |
| 201 | <GPIOMUX(20, GPOUT_LOW, |
| 202 | GPOEN_SYS_I2C5_DATA, |
| 203 | GPI_SYS_I2C5_DATA)>; |
| 204 | bias-disable; /* external pull-up */ |
| 205 | input-enable; |
| 206 | input-schmitt-enable; |
| 207 | }; |
| 208 | }; |
| 209 | |
| 210 | i2c6_pins: i2c6-0 { |
| 211 | i2c-pins { |
| 212 | pinmux = <GPIOMUX(16, GPOUT_LOW, |
| 213 | GPOEN_SYS_I2C6_CLK, |
| 214 | GPI_SYS_I2C6_CLK)>, |
| 215 | <GPIOMUX(17, GPOUT_LOW, |
| 216 | GPOEN_SYS_I2C6_DATA, |
| 217 | GPI_SYS_I2C6_DATA)>; |
| 218 | bias-disable; /* external pull-up */ |
| 219 | input-enable; |
| 220 | input-schmitt-enable; |
| 221 | }; |
| 222 | }; |
| 223 | |
| 224 | mmc0_pins: mmc0-pins { |
| 225 | mmc0-pins-rest { |
| 226 | pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, |
| 227 | GPOEN_ENABLE, GPI_NONE)>; |
| 228 | bias-pull-up; |
| 229 | drive-strength = <12>; |
| 230 | input-disable; |
| 231 | input-schmitt-disable; |
| 232 | slew-rate = <0>; |
| 233 | }; |
| 234 | }; |
| 235 | |
| 236 | mmc1_pins: mmc1-pins { |
| 237 | mmc1-pins0 { |
| 238 | pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK, |
| 239 | GPOEN_ENABLE, GPI_NONE)>; |
| 240 | bias-pull-up; |
| 241 | drive-strength = <12>; |
| 242 | input-disable; |
| 243 | input-schmitt-disable; |
| 244 | slew-rate = <0>; |
| 245 | }; |
| 246 | |
| 247 | mmc1-pins1 { |
| 248 | pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD, |
| 249 | GPOEN_SYS_SDIO1_CMD, GPI_SYS_SDIO1_CMD)>, |
| 250 | <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0, |
| 251 | GPOEN_SYS_SDIO1_DATA0, GPI_SYS_SDIO1_DATA0)>, |
| 252 | <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1, |
| 253 | GPOEN_SYS_SDIO1_DATA1, GPI_SYS_SDIO1_DATA1)>, |
| 254 | <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2, |
| 255 | GPOEN_SYS_SDIO1_DATA2, GPI_SYS_SDIO1_DATA2)>, |
| 256 | <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3, |
| 257 | GPOEN_SYS_SDIO1_DATA3, GPI_SYS_SDIO1_DATA3)>; |
| 258 | bias-pull-up; |
| 259 | drive-strength = <12>; |
| 260 | input-enable; |
| 261 | input-schmitt-enable; |
| 262 | slew-rate = <0>; |
| 263 | }; |
| 264 | }; |
| 265 | }; |
| 266 | |
| 267 | &mmc0 { |
| 268 | compatible = "snps,dw-mshc"; |
| 269 | max-frequency = <100000000>; |
| 270 | bus-width = <8>; |
| 271 | pinctrl-names = "default"; |
| 272 | pinctrl-0 = <&mmc0_pins>; |
| 273 | cap-mmc-highspeed; |
| 274 | mmc-ddr-1_8v; |
| 275 | mmc-hs200-1_8v; |
| 276 | non-removable; |
| 277 | cap-mmc-hw-reset; |
| 278 | post-power-on-delay-ms = <200>; |
| 279 | status = "okay"; |
| 280 | |
| 281 | }; |
| 282 | |
| 283 | &mmc1 { |
| 284 | compatible = "snps,dw-mshc"; |
| 285 | max-frequency = <100000000>; |
| 286 | bus-width = <4>; |
| 287 | pinctrl-names = "default"; |
| 288 | pinctrl-0 = <&mmc1_pins>; |
| 289 | no-sdio; |
| 290 | no-mmc; |
| 291 | broken-cd; |
| 292 | cap-sd-highspeed; |
| 293 | post-power-on-delay-ms = <200>; |
| 294 | status = "okay"; |
| 295 | }; |
| 296 | |
| 297 | &qspi { |
| 298 | spi-max-frequency = <250000000>; |
| 299 | status = "okay"; |
| 300 | |
| 301 | nor-flash@0 { |
| 302 | compatible = "jedec,spi-nor"; |
| 303 | reg=<0>; |
| 304 | spi-max-frequency = <100000000>; |
| 305 | cdns,tshsl-ns = <1>; |
| 306 | cdns,tsd2d-ns = <1>; |
| 307 | cdns,tchsh-ns = <1>; |
| 308 | cdns,tslch-ns = <1>; |
| 309 | }; |
| 310 | }; |
| 311 | |
Mason Huo | 23dfd81 | 2023-07-25 17:46:50 +0800 | [diff] [blame^] | 312 | &pcie0 { |
| 313 | reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; |
| 314 | status = "disabled"; |
| 315 | }; |
| 316 | |
| 317 | &pcie1 { |
| 318 | reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; |
| 319 | status = "okay"; |
| 320 | }; |
| 321 | |
Yanhong Wang | 5efc934 | 2023-03-29 11:42:23 +0800 | [diff] [blame] | 322 | &syscrg { |
| 323 | assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, |
| 324 | <&syscrg JH7110_SYSCLK_BUS_ROOT>, |
| 325 | <&syscrg JH7110_SYSCLK_PERH_ROOT>, |
| 326 | <&syscrg JH7110_SYSCLK_QSPI_REF>; |
Xingyu Wu | 1345c9e | 2023-07-07 18:50:09 +0800 | [diff] [blame] | 327 | assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>, |
| 328 | <&pllclk JH7110_SYSCLK_PLL2_OUT>, |
| 329 | <&pllclk JH7110_SYSCLK_PLL2_OUT>, |
Yanhong Wang | 5efc934 | 2023-03-29 11:42:23 +0800 | [diff] [blame] | 330 | <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; |
| 331 | assigned-clock-rates = <0>, <0>, <0>, <0>; |
| 332 | }; |
| 333 | |
| 334 | &aoncrg { |
| 335 | assigned-clocks = <&aoncrg JH7110_AONCLK_APB_FUNC>; |
| 336 | assigned-clock-parents = <&osc>; |
| 337 | assigned-clock-rates = <0>; |
| 338 | }; |
Yanhong Wang | 7f63bd9 | 2023-06-15 17:36:44 +0800 | [diff] [blame] | 339 | |
| 340 | &gmac0 { |
| 341 | phy-handle = <&phy0>; |
| 342 | phy-mode = "rgmii-id"; |
| 343 | status = "okay"; |
| 344 | |
| 345 | mdio { |
| 346 | #address-cells = <1>; |
| 347 | #size-cells = <0>; |
| 348 | compatible = "snps,dwmac-mdio"; |
| 349 | |
| 350 | phy0: ethernet-phy@0 { |
| 351 | reg = <0>; |
| 352 | }; |
| 353 | }; |
| 354 | }; |
| 355 | |
| 356 | &gmac1 { |
| 357 | phy-handle = <&phy1>; |
| 358 | phy-mode = "rgmii-id"; |
| 359 | status = "okay"; |
| 360 | |
| 361 | mdio { |
| 362 | #address-cells = <1>; |
| 363 | #size-cells = <0>; |
| 364 | compatible = "snps,dwmac-mdio"; |
| 365 | |
| 366 | phy1: ethernet-phy@1 { |
| 367 | reg = <0>; |
| 368 | }; |
| 369 | }; |
| 370 | }; |