blob: e2807a6b4f05078ca35335f509fc5d1b376d2194 [file] [log] [blame]
Timur Tabi054838e2006-10-31 18:44:42 -06001/*
Kumar Gala6a6d9482009-07-28 21:49:52 -05002 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Timur Tabi054838e2006-10-31 18:44:42 -06003 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Timur Tabi054838e2006-10-31 18:44:42 -06005 */
6
7/*
Timur Tabi435e3a72007-01-31 15:54:29 -06008 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
Timur Tabi054838e2006-10-31 18:44:42 -06009
10 Memory map:
11
12 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
13 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
14 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
15 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
16 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
17 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
Timur Tabi435e3a72007-01-31 15:54:29 -060018 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
Timur Tabi054838e2006-10-31 18:44:42 -060019 0xF001_0000-0xF001_FFFF Local bus expansion slot
Timur Tabi435e3a72007-01-31 15:54:29 -060020 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
21 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
22 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
Timur Tabi054838e2006-10-31 18:44:42 -060023
24 I2C address list:
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +010025 Align. Board
26 Bus Addr Part No. Description Length Location
Timur Tabi054838e2006-10-31 18:44:42 -060027 ----------------------------------------------------------------
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +010028 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
Timur Tabi054838e2006-10-31 18:44:42 -060029
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +010030 I2C1 0x20 PCF8574 I2C Expander 0 U8
31 I2C1 0x21 PCF8574 I2C Expander 0 U10
32 I2C1 0x38 PCF8574A I2C Expander 0 U8
33 I2C1 0x39 PCF8574A I2C Expander 0 U10
34 I2C1 0x51 (DDR) DDR EEPROM 1 U1
35 I2C1 0x68 DS1339 RTC 1 U68
Timur Tabi054838e2006-10-31 18:44:42 -060036
37 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
38*/
39
40#ifndef __CONFIG_H
41#define __CONFIG_H
42
Wolfgang Denk0708bc62010-10-07 21:51:12 +020043#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020044#define CONFIG_SYS_LOWBOOT
Timur Tabi435e3a72007-01-31 15:54:29 -060045#endif
Timur Tabi054838e2006-10-31 18:44:42 -060046
47/*
48 * High Level Configuration Options
49 */
Peter Tyser72f2d392009-05-22 17:23:25 -050050#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
Timur Tabi054838e2006-10-31 18:44:42 -060051#define CONFIG_MPC8349 /* MPC8349 specific */
52
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020053#ifndef CONFIG_SYS_TEXT_BASE
54#define CONFIG_SYS_TEXT_BASE 0xFEF00000
55#endif
56
Joe Hershberger2ce021f2011-10-11 23:57:15 -050057#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
Timur Tabi054838e2006-10-31 18:44:42 -060058
Timur Tabi3e1d49a2008-02-08 13:15:55 -060059#define CONFIG_MISC_INIT_F
60#define CONFIG_MISC_INIT_R
Timur Tabi435e3a72007-01-31 15:54:29 -060061
Timur Tabi3e1d49a2008-02-08 13:15:55 -060062/*
63 * On-board devices
64 */
Timur Tabi435e3a72007-01-31 15:54:29 -060065
66#ifdef CONFIG_MPC8349ITX
Joe Hershberger2ce021f2011-10-11 23:57:15 -050067/* The CF card interface on the back of the board */
68#define CONFIG_COMPACT_FLASH
Timur Tabi3e1d49a2008-02-08 13:15:55 -060069#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
Valeriy Glushkovce9d5852009-06-30 15:48:41 +030070#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
Timur Tabi435e3a72007-01-31 15:54:29 -060071#endif
Timur Tabi054838e2006-10-31 18:44:42 -060072
Timur Tabi435e3a72007-01-31 15:54:29 -060073#define CONFIG_RTC_DS1337
Heiko Schocherf2850742012-10-24 13:48:22 +020074#define CONFIG_SYS_I2C
Timur Tabi435e3a72007-01-31 15:54:29 -060075#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
Timur Tabi054838e2006-10-31 18:44:42 -060076
Timur Tabi435e3a72007-01-31 15:54:29 -060077/*
78 * Device configurations
79 */
80
81/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +020082#ifdef CONFIG_SYS_I2C
83#define CONFIG_SYS_I2C_FSL
84#define CONFIG_SYS_FSL_I2C_SPEED 400000
85#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
86#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
87#define CONFIG_SYS_FSL_I2C2_SPEED 400000
88#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
89#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Timur Tabi054838e2006-10-31 18:44:42 -060090
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
Valeriy Glushkov3da9bbf2009-02-04 18:27:49 +020092#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
Timur Tabi054838e2006-10-31 18:44:42 -060093
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
95#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
96#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
97#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
98#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
Joe Hershberger2ce021f2011-10-11 23:57:15 -050099#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
100#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
Timur Tabi054838e2006-10-31 18:44:42 -0600101
Timur Tabi054838e2006-10-31 18:44:42 -0600102/* Don't probe these addresses: */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500103#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
105 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500106 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
Timur Tabi054838e2006-10-31 18:44:42 -0600107/* Bit definitions for the 8574[A] I2C expander */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500108 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
109#define I2C_8574_REVISION 0x03
Timur Tabi054838e2006-10-31 18:44:42 -0600110#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
111#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
112#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
113#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
114
Timur Tabi054838e2006-10-31 18:44:42 -0600115#endif
116
Timur Tabi435e3a72007-01-31 15:54:29 -0600117/* Compact Flash */
118#ifdef CONFIG_COMPACT_FLASH
Timur Tabi054838e2006-10-31 18:44:42 -0600119
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_IDE_MAXBUS 1
121#define CONFIG_SYS_IDE_MAXDEVICE 1
Timur Tabi054838e2006-10-31 18:44:42 -0600122
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
124#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
125#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
126#define CONFIG_SYS_ATA_REG_OFFSET 0
127#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
128#define CONFIG_SYS_ATA_STRIDE 2
Timur Tabi054838e2006-10-31 18:44:42 -0600129
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500130/* If a CF card is not inserted, time out quickly */
131#define ATA_RESET_TIME 1
Timur Tabi054838e2006-10-31 18:44:42 -0600132
Valeriy Glushkove3418772009-02-05 14:35:21 +0200133#endif
134
135/*
136 * SATA
137 */
138#ifdef CONFIG_SATA_SIL3114
139
140#define CONFIG_SYS_SATA_MAX_DEVICE 4
Valeriy Glushkove3418772009-02-05 14:35:21 +0200141#define CONFIG_LBA48
Timur Tabi054838e2006-10-31 18:44:42 -0600142
Timur Tabi435e3a72007-01-31 15:54:29 -0600143#endif
Timur Tabi054838e2006-10-31 18:44:42 -0600144
Valeriy Glushkovce9d5852009-06-30 15:48:41 +0300145#ifdef CONFIG_SYS_USB_HOST
146/*
147 * Support USB
148 */
Valeriy Glushkovce9d5852009-06-30 15:48:41 +0300149#define CONFIG_USB_EHCI_FSL
150
151/* Current USB implementation supports the only USB controller,
152 * so we have to choose between the MPH or the DR ones */
153#if 1
154#define CONFIG_HAS_FSL_MPH_USB
155#else
156#define CONFIG_HAS_FSL_DR_USB
157#endif
158
159#endif
160
Timur Tabi054838e2006-10-31 18:44:42 -0600161/*
Timur Tabi435e3a72007-01-31 15:54:29 -0600162 * DDR Setup
Timur Tabi054838e2006-10-31 18:44:42 -0600163 */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500164#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
166#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
167#define CONFIG_SYS_83XX_DDR_USES_CS0
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500168#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200169#define CONFIG_SYS_MEMTEST_END 0x2000
Timur Tabi054838e2006-10-31 18:44:42 -0600170
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500171#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
172 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
Timur Tabi83d47822007-04-30 13:59:50 -0500173
Valeriy Glushkov3da9bbf2009-02-04 18:27:49 +0200174#define CONFIG_VERY_BIG_RAM
175#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
176
Heiko Schocherf2850742012-10-24 13:48:22 +0200177#ifdef CONFIG_SYS_I2C
Timur Tabi435e3a72007-01-31 15:54:29 -0600178#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
179#endif
180
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500181/* No SPD? Then manually set up DDR parameters */
182#ifndef CONFIG_SPD_EEPROM
183 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
Joe Hershberger5ade3902011-10-11 23:57:31 -0500184 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500185 | CSCONFIG_ROW_BIT_13 \
186 | CSCONFIG_COL_BIT_10)
Timur Tabi054838e2006-10-31 18:44:42 -0600187
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200188 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
189 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
Timur Tabi054838e2006-10-31 18:44:42 -0600190#endif
191
Timur Tabi435e3a72007-01-31 15:54:29 -0600192/*
193 *Flash on the Local Bus
194 */
195
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500196#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
197#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
199#define CONFIG_SYS_FLASH_EMPTY_INFO
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500200/* 127 64KB sectors + 8 8KB sectors per device */
201#define CONFIG_SYS_MAX_FLASH_SECT 135
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
203#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
204#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Timur Tabi435e3a72007-01-31 15:54:29 -0600205
206/* The ITX has two flash chips, but the ITX-GP has only one. To support both
207boards, we say we have two, but don't display a message if we find only one. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#define CONFIG_SYS_FLASH_QUIET_TEST
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500209#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
210#define CONFIG_SYS_FLASH_BANKS_LIST \
211 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
212#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500213#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Timur Tabi435e3a72007-01-31 15:54:29 -0600214
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600215/* Vitesse 7385 */
216
217#ifdef CONFIG_VSC7385_ENET
218
219#define CONFIG_TSEC2
220
221/* The flash address and size of the VSC7385 firmware image */
222#define CONFIG_VSC7385_IMAGE 0xFEFFE000
223#define CONFIG_VSC7385_IMAGE_SIZE 8192
224
225#endif
226
Timur Tabi435e3a72007-01-31 15:54:29 -0600227/*
228 * BRx, ORx, LBLAWBARx, and LBLAWARx
229 */
230
231/* Flash */
Timur Tabi054838e2006-10-31 18:44:42 -0600232
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500233#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
234 | BR_PS_16 \
235 | BR_MS_GPCM \
236 | BR_V)
237#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500238 | OR_UPM_XAM \
239 | OR_GPCM_CSNT \
240 | OR_GPCM_ACS_DIV2 \
241 | OR_GPCM_XACS \
242 | OR_GPCM_SCY_15 \
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500243 | OR_GPCM_TRLX_SET \
244 | OR_GPCM_EHTR_SET \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500245 | OR_GPCM_EAD)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200246#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500247#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
Timur Tabi054838e2006-10-31 18:44:42 -0600248
Timur Tabi435e3a72007-01-31 15:54:29 -0600249/* Vitesse 7385 */
Timur Tabi054838e2006-10-31 18:44:42 -0600250
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200251#define CONFIG_SYS_VSC7385_BASE 0xF8000000
Timur Tabi054838e2006-10-31 18:44:42 -0600252
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600253#ifdef CONFIG_VSC7385_ENET
254
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500255#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
256 | BR_PS_8 \
257 | BR_MS_GPCM \
258 | BR_V)
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500259#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
260 | OR_GPCM_CSNT \
261 | OR_GPCM_XACS \
262 | OR_GPCM_SCY_15 \
263 | OR_GPCM_SETA \
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500264 | OR_GPCM_TRLX_SET \
265 | OR_GPCM_EHTR_SET \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500266 | OR_GPCM_EAD)
Timur Tabi054838e2006-10-31 18:44:42 -0600267
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200268#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
269#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Timur Tabi054838e2006-10-31 18:44:42 -0600270
Timur Tabi435e3a72007-01-31 15:54:29 -0600271#endif
272
273/* LED */
Timur Tabi054838e2006-10-31 18:44:42 -0600274
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500275#define CONFIG_SYS_LED_BASE 0xF9000000
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500276#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
277 | BR_PS_8 \
278 | BR_MS_GPCM \
279 | BR_V)
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500280#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
281 | OR_GPCM_CSNT \
282 | OR_GPCM_ACS_DIV2 \
283 | OR_GPCM_XACS \
284 | OR_GPCM_SCY_9 \
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500285 | OR_GPCM_TRLX_SET \
286 | OR_GPCM_EHTR_SET \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500287 | OR_GPCM_EAD)
Timur Tabi435e3a72007-01-31 15:54:29 -0600288
289/* Compact Flash */
Timur Tabi054838e2006-10-31 18:44:42 -0600290
291#ifdef CONFIG_COMPACT_FLASH
292
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500293#define CONFIG_SYS_CF_BASE 0xF0000000
Timur Tabi054838e2006-10-31 18:44:42 -0600294
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500295#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
296 | BR_PS_16 \
297 | BR_MS_UPMA \
298 | BR_V)
299#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
Timur Tabi054838e2006-10-31 18:44:42 -0600300
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200301#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
302#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
Timur Tabi054838e2006-10-31 18:44:42 -0600303
304#endif
305
Timur Tabi435e3a72007-01-31 15:54:29 -0600306/*
307 * U-Boot memory configuration
308 */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200309#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Timur Tabi054838e2006-10-31 18:44:42 -0600310
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200311#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
312#define CONFIG_SYS_RAMBOOT
Timur Tabi054838e2006-10-31 18:44:42 -0600313#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200314#undef CONFIG_SYS_RAMBOOT
Timur Tabi054838e2006-10-31 18:44:42 -0600315#endif
316
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200317#define CONFIG_SYS_INIT_RAM_LOCK
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500318#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
319#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Timur Tabi054838e2006-10-31 18:44:42 -0600320
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500321#define CONFIG_SYS_GBL_DATA_OFFSET \
322 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200323#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Timur Tabi054838e2006-10-31 18:44:42 -0600324
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200325/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kevin Hao349a0152016-07-08 11:25:14 +0800326#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Kim Phillips831d2f62012-06-30 18:29:20 -0500327#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Timur Tabi054838e2006-10-31 18:44:42 -0600328
329/*
330 * Local Bus LCRR and LBCR regs
331 * LCRR: DLL bypass, Clock divider is 4
332 * External Local Bus rate is
333 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
334 */
Kim Phillips328040a2009-09-25 18:19:44 -0500335#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
336#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200337#define CONFIG_SYS_LBC_LBCR 0x00000000
Timur Tabi054838e2006-10-31 18:44:42 -0600338
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500339 /* LB sdram refresh timer, about 6us */
340#define CONFIG_SYS_LBC_LSRT 0x32000000
341 /* LB refresh timer prescal, 266MHz/32*/
342#define CONFIG_SYS_LBC_MRTPR 0x20000000
Timur Tabi054838e2006-10-31 18:44:42 -0600343
344/*
Timur Tabi054838e2006-10-31 18:44:42 -0600345 * Serial Port
346 */
347#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200348#define CONFIG_SYS_NS16550_SERIAL
349#define CONFIG_SYS_NS16550_REG_SIZE 1
350#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Timur Tabi054838e2006-10-31 18:44:42 -0600351
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200352#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500353 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Timur Tabi435e3a72007-01-31 15:54:29 -0600354
Simon Glassa406b692016-10-17 20:12:38 -0600355#define CONSOLE ttyS0
Timur Tabi054838e2006-10-31 18:44:42 -0600356
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200357#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
358#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Timur Tabi054838e2006-10-31 18:44:42 -0600359
Timur Tabi435e3a72007-01-31 15:54:29 -0600360/*
361 * PCI
362 */
Timur Tabi054838e2006-10-31 18:44:42 -0600363#ifdef CONFIG_PCI
Gabor Juhosb4458732013-05-30 07:06:12 +0000364#define CONFIG_PCI_INDIRECT_BRIDGE
Timur Tabi054838e2006-10-31 18:44:42 -0600365
366#define CONFIG_MPC83XX_PCI2
367
368/*
369 * General PCI
370 * Addresses are mapped 1-1.
371 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200372#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
373#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
374#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500375#define CONFIG_SYS_PCI1_MMIO_BASE \
376 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200377#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
378#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500379#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
380#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
381#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Timur Tabi054838e2006-10-31 18:44:42 -0600382
383#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500384#define CONFIG_SYS_PCI2_MEM_BASE \
385 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200386#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
387#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500388#define CONFIG_SYS_PCI2_MMIO_BASE \
389 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200390#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
391#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500392#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
393#define CONFIG_SYS_PCI2_IO_PHYS \
394 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
395#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
Timur Tabi054838e2006-10-31 18:44:42 -0600396#endif
397
Timur Tabi054838e2006-10-31 18:44:42 -0600398#ifndef CONFIG_PCI_PNP
399 #define PCI_ENET0_IOADDR 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200400 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
Timur Tabi054838e2006-10-31 18:44:42 -0600401 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
402#endif
403
404#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
405
406#endif
407
Wolfgang Denk291ba1b2010-10-06 09:05:45 +0200408#define CONFIG_PCI_66M
409#ifdef CONFIG_PCI_66M
Timur Tabi435e3a72007-01-31 15:54:29 -0600410#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
411#else
412#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
413#endif
414
Timur Tabi054838e2006-10-31 18:44:42 -0600415/* TSEC */
416
417#ifdef CONFIG_TSEC_ENET
418
Timur Tabi054838e2006-10-31 18:44:42 -0600419#define CONFIG_MII
Timur Tabi054838e2006-10-31 18:44:42 -0600420
Kim Phillips177e58f2007-05-16 16:52:19 -0500421#define CONFIG_TSEC1
Timur Tabi054838e2006-10-31 18:44:42 -0600422
Kim Phillips177e58f2007-05-16 16:52:19 -0500423#ifdef CONFIG_TSEC1
Andy Fleming458c3892007-08-16 16:35:02 -0500424#define CONFIG_HAS_ETH0
Kim Phillips177e58f2007-05-16 16:52:19 -0500425#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200426#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +0100427#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
Timur Tabi054838e2006-10-31 18:44:42 -0600428#define TSEC1_PHYIDX 0
Andy Fleming09b88df2007-08-15 20:03:25 -0500429#define TSEC1_FLAGS TSEC_GIGABIT
Timur Tabi054838e2006-10-31 18:44:42 -0600430#endif
431
Kim Phillips177e58f2007-05-16 16:52:19 -0500432#ifdef CONFIG_TSEC2
Timur Tabi435e3a72007-01-31 15:54:29 -0600433#define CONFIG_HAS_ETH1
Kim Phillips177e58f2007-05-16 16:52:19 -0500434#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200435#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600436
Timur Tabi054838e2006-10-31 18:44:42 -0600437#define TSEC2_PHY_ADDR 4
438#define TSEC2_PHYIDX 0
Andy Fleming09b88df2007-08-15 20:03:25 -0500439#define TSEC2_FLAGS TSEC_GIGABIT
Timur Tabi054838e2006-10-31 18:44:42 -0600440#endif
441
442#define CONFIG_ETHPRIME "Freescale TSEC"
443
444#endif
445
Timur Tabi054838e2006-10-31 18:44:42 -0600446/*
447 * Environment
448 */
Timur Tabi435e3a72007-01-31 15:54:29 -0600449#define CONFIG_ENV_OVERWRITE
450
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200451#ifndef CONFIG_SYS_RAMBOOT
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500452 #define CONFIG_ENV_ADDR \
453 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200454 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500455 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi054838e2006-10-31 18:44:42 -0600456#else
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200457 #undef CONFIG_FLASH_CFI_DRIVER
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500458 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
459 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi054838e2006-10-31 18:44:42 -0600460#endif
461
462#define CONFIG_LOADS_ECHO /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200463#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
Timur Tabi054838e2006-10-31 18:44:42 -0600464
Jon Loeliger3b7116d2007-07-04 22:30:06 -0500465/*
Jon Loeligered26c742007-07-10 09:10:49 -0500466 * BOOTP options
467 */
468#define CONFIG_BOOTP_BOOTFILESIZE
469#define CONFIG_BOOTP_BOOTPATH
470#define CONFIG_BOOTP_GATEWAY
471#define CONFIG_BOOTP_HOSTNAME
472
Timur Tabi054838e2006-10-31 18:44:42 -0600473/* Watchdog */
Timur Tabi054838e2006-10-31 18:44:42 -0600474#undef CONFIG_WATCHDOG /* watchdog disabled */
Timur Tabi054838e2006-10-31 18:44:42 -0600475
476/*
477 * Miscellaneous configurable options
478 */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500479#define CONFIG_SYS_LONGHELP /* undef to save memory */
480#define CONFIG_CMDLINE_EDITING /* Command-line editing */
481#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Timur Tabi435e3a72007-01-31 15:54:29 -0600482
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200483#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kim Phillips73060b52009-08-26 21:27:37 -0500484#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Timur Tabi435e3a72007-01-31 15:54:29 -0600485
Timur Tabi054838e2006-10-31 18:44:42 -0600486/*
487 * For booting Linux, the board info and command line data
Ira W. Snyderc5a22d02010-09-10 15:42:32 -0700488 * have to be in the first 256 MB of memory, since this is
Timur Tabi054838e2006-10-31 18:44:42 -0600489 * the maximum mapped by the Linux kernel during initialization.
490 */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500491 /* Initial Memory map for Linux*/
492#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Kevin Hao9c747962016-07-08 11:25:15 +0800493#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabi054838e2006-10-31 18:44:42 -0600494
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200495#define CONFIG_SYS_HRCW_LOW (\
Timur Tabi054838e2006-10-31 18:44:42 -0600496 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
497 HRCWL_DDR_TO_SCB_CLK_1X1 |\
498 HRCWL_CSB_TO_CLKIN_4X1 |\
499 HRCWL_VCO_1X2 |\
500 HRCWL_CORE_TO_CSB_2X1)
501
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200502#ifdef CONFIG_SYS_LOWBOOT
503#define CONFIG_SYS_HRCW_HIGH (\
Timur Tabi054838e2006-10-31 18:44:42 -0600504 HRCWH_PCI_HOST |\
Timur Tabi435e3a72007-01-31 15:54:29 -0600505 HRCWH_32_BIT_PCI |\
Timur Tabi054838e2006-10-31 18:44:42 -0600506 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi435e3a72007-01-31 15:54:29 -0600507 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi054838e2006-10-31 18:44:42 -0600508 HRCWH_CORE_ENABLE |\
509 HRCWH_FROM_0X00000100 |\
510 HRCWH_BOOTSEQ_DISABLE |\
511 HRCWH_SW_WATCHDOG_DISABLE |\
512 HRCWH_ROM_LOC_LOCAL_16BIT |\
513 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500514 HRCWH_TSEC2M_IN_GMII)
Timur Tabi054838e2006-10-31 18:44:42 -0600515#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200516#define CONFIG_SYS_HRCW_HIGH (\
Timur Tabi054838e2006-10-31 18:44:42 -0600517 HRCWH_PCI_HOST |\
518 HRCWH_32_BIT_PCI |\
519 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi435e3a72007-01-31 15:54:29 -0600520 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi054838e2006-10-31 18:44:42 -0600521 HRCWH_CORE_ENABLE |\
522 HRCWH_FROM_0XFFF00100 |\
523 HRCWH_BOOTSEQ_DISABLE |\
524 HRCWH_SW_WATCHDOG_DISABLE |\
525 HRCWH_ROM_LOC_LOCAL_16BIT |\
526 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500527 HRCWH_TSEC2M_IN_GMII)
Timur Tabi054838e2006-10-31 18:44:42 -0600528#endif
529
Timur Tabi435e3a72007-01-31 15:54:29 -0600530/*
531 * System performance
532 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200533#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500534#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200535#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
536#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
537#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
538#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
Valeriy Glushkovce9d5852009-06-30 15:48:41 +0300539#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
540#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
Timur Tabi054838e2006-10-31 18:44:42 -0600541
Timur Tabi435e3a72007-01-31 15:54:29 -0600542/*
543 * System IO Config
544 */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500545/* Needed for gigabit to work on TSEC 1 */
546#define CONFIG_SYS_SICRH SICRH_TSOBI1
547 /* USB DR as device + USB MPH as host */
548#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
Timur Tabi054838e2006-10-31 18:44:42 -0600549
Kim Phillipsf3c7cd92010-04-20 19:37:54 -0500550#define CONFIG_SYS_HID0_INIT 0x00000000
551#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
Timur Tabi054838e2006-10-31 18:44:42 -0600552
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200553#define CONFIG_SYS_HID2 HID2_HBE
Becky Bruce03ea1be2008-05-08 19:02:12 -0500554#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Timur Tabi054838e2006-10-31 18:44:42 -0600555
Timur Tabi435e3a72007-01-31 15:54:29 -0600556/* DDR */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500557#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500558 | BATL_PP_RW \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500559 | BATL_MEMCOHERENCE)
560#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
561 | BATU_BL_256M \
562 | BATU_VS \
563 | BATU_VP)
Timur Tabi054838e2006-10-31 18:44:42 -0600564
Timur Tabi435e3a72007-01-31 15:54:29 -0600565/* PCI */
Timur Tabi054838e2006-10-31 18:44:42 -0600566#ifdef CONFIG_PCI
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500567#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500568 | BATL_PP_RW \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500569 | BATL_MEMCOHERENCE)
570#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
571 | BATU_BL_256M \
572 | BATU_VS \
573 | BATU_VP)
574#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500575 | BATL_PP_RW \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500576 | BATL_CACHEINHIBIT \
577 | BATL_GUARDEDSTORAGE)
578#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
579 | BATU_BL_256M \
580 | BATU_VS \
581 | BATU_VP)
Timur Tabi054838e2006-10-31 18:44:42 -0600582#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200583#define CONFIG_SYS_IBAT1L 0
584#define CONFIG_SYS_IBAT1U 0
585#define CONFIG_SYS_IBAT2L 0
586#define CONFIG_SYS_IBAT2U 0
Timur Tabi054838e2006-10-31 18:44:42 -0600587#endif
588
589#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500590#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500591 | BATL_PP_RW \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500592 | BATL_MEMCOHERENCE)
593#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
594 | BATU_BL_256M \
595 | BATU_VS \
596 | BATU_VP)
597#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500598 | BATL_PP_RW \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500599 | BATL_CACHEINHIBIT \
600 | BATL_GUARDEDSTORAGE)
601#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
602 | BATU_BL_256M \
603 | BATU_VS \
604 | BATU_VP)
Timur Tabi054838e2006-10-31 18:44:42 -0600605#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200606#define CONFIG_SYS_IBAT3L 0
607#define CONFIG_SYS_IBAT3U 0
608#define CONFIG_SYS_IBAT4L 0
609#define CONFIG_SYS_IBAT4U 0
Timur Tabi054838e2006-10-31 18:44:42 -0600610#endif
611
612/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500613#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500614 | BATL_PP_RW \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500615 | BATL_CACHEINHIBIT \
616 | BATL_GUARDEDSTORAGE)
617#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
618 | BATU_BL_256M \
619 | BATU_VS \
620 | BATU_VP)
Timur Tabi054838e2006-10-31 18:44:42 -0600621
622/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500623#define CONFIG_SYS_IBAT6L (0xF0000000 \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500624 | BATL_PP_RW \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500625 | BATL_MEMCOHERENCE \
626 | BATL_GUARDEDSTORAGE)
627#define CONFIG_SYS_IBAT6U (0xF0000000 \
628 | BATU_BL_256M \
629 | BATU_VS \
630 | BATU_VP)
Timur Tabi054838e2006-10-31 18:44:42 -0600631
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200632#define CONFIG_SYS_IBAT7L 0
633#define CONFIG_SYS_IBAT7U 0
Timur Tabi054838e2006-10-31 18:44:42 -0600634
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200635#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
636#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
637#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
638#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
639#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
640#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
641#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
642#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
643#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
644#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
645#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
646#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
647#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
648#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
649#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
650#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Timur Tabi054838e2006-10-31 18:44:42 -0600651
Jon Loeliger3b7116d2007-07-04 22:30:06 -0500652#if defined(CONFIG_CMD_KGDB)
Timur Tabi054838e2006-10-31 18:44:42 -0600653#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Timur Tabi054838e2006-10-31 18:44:42 -0600654#endif
655
Timur Tabi054838e2006-10-31 18:44:42 -0600656/*
657 * Environment Configuration
658 */
659#define CONFIG_ENV_OVERWRITE
660
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500661#define CONFIG_NETDEV "eth0"
Timur Tabi054838e2006-10-31 18:44:42 -0600662
Timur Tabi435e3a72007-01-31 15:54:29 -0600663/* Default path and filenames */
Joe Hershberger257ff782011-10-13 13:03:47 +0000664#define CONFIG_ROOTPATH "/nfsroot/rootfs"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000665#define CONFIG_BOOTFILE "uImage"
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500666 /* U-Boot image on TFTP server */
667#define CONFIG_UBOOTPATH "u-boot.bin"
Timur Tabi054838e2006-10-31 18:44:42 -0600668
Timur Tabi435e3a72007-01-31 15:54:29 -0600669#ifdef CONFIG_MPC8349ITX
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500670#define CONFIG_FDTFILE "mpc8349emitx.dtb"
Timur Tabi054838e2006-10-31 18:44:42 -0600671#else
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500672#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
Timur Tabi054838e2006-10-31 18:44:42 -0600673#endif
674
Timur Tabi435e3a72007-01-31 15:54:29 -0600675
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +0100676#define CONFIG_EXTRA_ENV_SETTINGS \
Simon Glassa406b692016-10-17 20:12:38 -0600677 "console=" __stringify(CONSOLE) "\0" \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500678 "netdev=" CONFIG_NETDEV "\0" \
679 "uboot=" CONFIG_UBOOTPATH "\0" \
Wolfgang Denka1be4762008-05-20 16:00:29 +0200680 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200681 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
682 " +$filesize; " \
683 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
684 " +$filesize; " \
685 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
686 " $filesize; " \
687 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
688 " +$filesize; " \
689 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
690 " $filesize\0" \
Kim Phillips73060b52009-08-26 21:27:37 -0500691 "fdtaddr=780000\0" \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500692 "fdtfile=" CONFIG_FDTFILE "\0"
Kim Phillips774e1b52006-11-01 00:10:40 -0600693
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +0100694#define CONFIG_NFSBOOTCOMMAND \
Timur Tabi435e3a72007-01-31 15:54:29 -0600695 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500696 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
Timur Tabi435e3a72007-01-31 15:54:29 -0600697 " console=$console,$baudrate $othbootargs; " \
698 "tftp $loadaddr $bootfile;" \
699 "tftp $fdtaddr $fdtfile;" \
700 "bootm $loadaddr - $fdtaddr"
Kim Phillips774e1b52006-11-01 00:10:40 -0600701
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +0100702#define CONFIG_RAMBOOTCOMMAND \
Timur Tabi435e3a72007-01-31 15:54:29 -0600703 "setenv bootargs root=/dev/ram rw" \
704 " console=$console,$baudrate $othbootargs; " \
705 "tftp $ramdiskaddr $ramdiskfile;" \
706 "tftp $loadaddr $bootfile;" \
707 "tftp $fdtaddr $fdtfile;" \
708 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Timur Tabi054838e2006-10-31 18:44:42 -0600709
Timur Tabi054838e2006-10-31 18:44:42 -0600710#endif